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ZhouShuya
OpenXG-RAN
Commits
b0f5a37f
Commit
b0f5a37f
authored
4 years ago
by
masayuki.harada
Browse files
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Browse Files
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Plain Diff
Fix indentation, merge miss and remove unnecessary comment.
parent
88699deb
Changes
8
Hide whitespace changes
Inline
Side-by-side
Showing
8 changed files
with
395 additions
and
1905 deletions
+395
-1905
common/utils/asn1_conversions.h
common/utils/asn1_conversions.h
+4
-20
openair1/PHY/TOOLS/dB_routines.c
openair1/PHY/TOOLS/dB_routines.c
+299
-299
openair1/PHY/TOOLS/signal_energy.c
openair1/PHY/TOOLS/signal_energy.c
+81
-188
openair1/SCHED/fapi_l1.c
openair1/SCHED/fapi_l1.c
+9
-10
openair2/LAYER2/MAC/defs.h
openair2/LAYER2/MAC/defs.h
+0
-1359
openair2/LAYER2/MAC/eNB_scheduler_RA.c
openair2/LAYER2/MAC/eNB_scheduler_RA.c
+0
-7
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
+1
-3
openair2/RRC/LTE/rrc_eNB.c
openair2/RRC/LTE/rrc_eNB.c
+1
-19
No files found.
common/utils/asn1_conversions.h
View file @
b0f5a37f
...
@@ -33,11 +33,7 @@
...
@@ -33,11 +33,7 @@
*\return the extracted value.
*\return the extracted value.
*/
*/
static
inline
uint8_t
BIT_STRING_to_uint8
(
BIT_STRING_t
*
asn
)
{
static
inline
uint8_t
BIT_STRING_to_uint8
(
BIT_STRING_t
*
asn
)
{
//DevCheck ((asn->size == 1), asn->size, 0, 0);
DevCheck
((
asn
->
size
==
1
),
asn
->
size
,
0
,
0
);
if
(
!
(
asn
->
size
==
1
))
{
printf
(
"BIT_STRING_to_uint8 size %ld
\n
"
,
asn
->
size
);
return
0
;
}
return
asn
->
buf
[
0
]
>>
asn
->
bits_unused
;
return
asn
->
buf
[
0
]
>>
asn
->
bits_unused
;
}
}
...
@@ -51,11 +47,7 @@ static inline uint16_t BIT_STRING_to_uint16(BIT_STRING_t *asn) {
...
@@ -51,11 +47,7 @@ static inline uint16_t BIT_STRING_to_uint16(BIT_STRING_t *asn) {
uint16_t
result
=
0
;
uint16_t
result
=
0
;
int
index
=
0
;
int
index
=
0
;
//DevCheck ((asn->size > 0) && (asn->size <= 2), asn->size, 0, 0);
DevCheck
((
asn
->
size
>
0
)
&&
(
asn
->
size
<=
2
),
asn
->
size
,
0
,
0
);
if
(
!
((
asn
->
size
>
0
)
&&
(
asn
->
size
<=
2
)))
{
printf
(
"BIT_STRING_to_uint16 size %ld
\n
"
,
asn
->
size
);
return
0
;
}
switch
(
asn
->
size
)
{
switch
(
asn
->
size
)
{
case
2
:
case
2
:
...
@@ -82,11 +74,7 @@ static inline uint32_t BIT_STRING_to_uint32(BIT_STRING_t *asn) {
...
@@ -82,11 +74,7 @@ static inline uint32_t BIT_STRING_to_uint32(BIT_STRING_t *asn) {
int
index
;
int
index
;
int
shift
;
int
shift
;
//DevCheck ((asn->size > 0) && (asn->size <= 4), asn->size, 0, 0);
DevCheck
((
asn
->
size
>
0
)
&&
(
asn
->
size
<=
4
),
asn
->
size
,
0
,
0
);
if
(
!
((
asn
->
size
>
0
)
&&
(
asn
->
size
<=
4
)))
{
printf
(
"BIT_STRING_to_uint32 size %ld
\n
"
,
asn
->
size
);
return
0
;
}
shift
=
((
asn
->
size
-
1
)
*
8
)
-
asn
->
bits_unused
;
shift
=
((
asn
->
size
-
1
)
*
8
)
-
asn
->
bits_unused
;
for
(
index
=
0
;
index
<
(
asn
->
size
-
1
);
index
++
)
{
for
(
index
=
0
;
index
<
(
asn
->
size
-
1
);
index
++
)
{
...
@@ -109,11 +97,7 @@ static inline uint64_t BIT_STRING_to_uint64(BIT_STRING_t *asn) {
...
@@ -109,11 +97,7 @@ static inline uint64_t BIT_STRING_to_uint64(BIT_STRING_t *asn) {
int
index
;
int
index
;
int
shift
;
int
shift
;
//DevCheck ((asn->size > 0) && (asn->size <= 8), asn->size, 0, 0);
DevCheck
((
asn
->
size
>
0
)
&&
(
asn
->
size
<=
8
),
asn
->
size
,
0
,
0
);
if
(
!
((
asn
->
size
>
0
)
&&
(
asn
->
size
<=
8
)))
{
printf
(
"BIT_STRING_to_uint64 size %ld
\n
"
,
asn
->
size
);
return
0
;
}
shift
=
((
asn
->
size
-
1
)
*
8
)
-
asn
->
bits_unused
;
shift
=
((
asn
->
size
-
1
)
*
8
)
-
asn
->
bits_unused
;
for
(
index
=
0
;
index
<
(
asn
->
size
-
1
);
index
++
)
{
for
(
index
=
0
;
index
<
(
asn
->
size
-
1
);
index
++
)
{
...
...
This diff is collapsed.
Click to expand it.
openair1/PHY/TOOLS/dB_routines.c
View file @
b0f5a37f
...
@@ -543,284 +543,284 @@ int16_t dB_table_times10[256] = {
...
@@ -543,284 +543,284 @@ int16_t dB_table_times10[256] = {
uint32_t
bit_seach_mask
[
32
]
=
{
uint32_t
bit_seach_mask
[
32
]
=
{
0x80000000
,
0x40000000
,
0x20000000
,
0x10000000
,
0x80000000
,
0x40000000
,
0x20000000
,
0x10000000
,
0x08000000
,
0x04000000
,
0x02000000
,
0x01000000
,
0x08000000
,
0x04000000
,
0x02000000
,
0x01000000
,
0x00800000
,
0x00400000
,
0x00200000
,
0x00100000
,
0x00800000
,
0x00400000
,
0x00200000
,
0x00100000
,
0x00080000
,
0x00040000
,
0x00020000
,
0x00010000
,
0x00080000
,
0x00040000
,
0x00020000
,
0x00010000
,
0x00008000
,
0x00004000
,
0x00002000
,
0x00001000
,
0x00008000
,
0x00004000
,
0x00002000
,
0x00001000
,
0x00000800
,
0x00000400
,
0x00000200
,
0x00000100
,
0x00000800
,
0x00000400
,
0x00000200
,
0x00000100
,
0x00000080
,
0x00000040
,
0x00000020
,
0x00000010
,
0x00000080
,
0x00000040
,
0x00000020
,
0x00000010
,
0x00000008
,
0x00000004
,
0x00000002
,
0x00000001
0x00000008
,
0x00000004
,
0x00000002
,
0x00000001
};
};
uint32_t
bit_seach_res
[
32
]
=
{
uint32_t
bit_seach_res
[
32
]
=
{
31
,
30
,
29
,
28
,
31
,
30
,
29
,
28
,
27
,
26
,
25
,
24
,
27
,
26
,
25
,
24
,
23
,
22
,
21
,
20
,
23
,
22
,
21
,
20
,
19
,
18
,
17
,
16
,
19
,
18
,
17
,
16
,
15
,
14
,
13
,
12
,
15
,
14
,
13
,
12
,
11
,
10
,
9
,
8
,
11
,
10
,
9
,
8
,
7
,
6
,
5
,
4
,
7
,
6
,
5
,
4
,
3
,
2
,
1
,
0
3
,
2
,
1
,
0
};
};
uint32_t
dB_fix_x10_tbl
[
128
]
=
{
uint32_t
dB_fix_x10_tbl
[
128
]
=
{
0
,
0
,
0
,
0
,
1
,
1
,
1
,
1
,
1
,
1
,
2
,
2
,
2
,
2
,
2
,
2
,
3
,
3
,
3
,
3
,
3
,
3
,
4
,
4
,
4
,
4
,
4
,
4
,
5
,
5
,
5
,
5
,
5
,
5
,
5
,
5
,
6
,
6
,
6
,
6
,
6
,
6
,
7
,
7
,
7
,
7
,
7
,
7
,
7
,
7
,
8
,
8
,
8
,
8
,
8
,
8
,
9
,
9
,
9
,
9
,
9
,
9
,
9
,
9
,
10
,
10
,
10
,
10
,
10
,
10
,
10
,
10
,
11
,
11
,
11
,
11
,
11
,
11
,
12
,
12
,
12
,
12
,
12
,
12
,
12
,
12
,
13
,
13
,
13
,
13
,
13
,
13
,
13
,
13
,
14
,
14
,
14
,
14
,
14
,
14
,
14
,
14
,
15
,
15
,
15
,
15
,
15
,
15
,
15
,
15
,
16
,
16
,
16
,
16
,
16
,
16
,
16
,
16
,
16
,
16
,
17
,
17
,
17
,
17
,
17
,
17
,
17
,
17
,
18
,
18
,
18
,
18
,
18
,
18
,
18
,
18
,
19
,
19
,
19
,
19
,
19
,
19
,
19
,
19
,
19
,
19
,
20
,
20
,
20
,
20
,
20
,
20
,
20
,
20
,
20
,
20
,
21
,
21
,
21
,
21
,
21
,
21
,
21
,
21
,
22
,
22
,
22
,
22
,
22
,
22
,
22
,
22
,
22
,
22
,
23
,
23
,
23
,
23
,
23
,
23
,
23
,
23
,
23
,
23
,
24
,
24
,
24
,
24
,
24
,
24
,
24
,
24
,
24
,
24
,
24
,
24
,
25
,
25
,
25
,
25
,
25
,
25
,
25
,
25
,
25
,
25
,
26
,
26
,
26
,
26
,
26
,
26
,
26
,
26
,
26
,
26
,
27
,
27
,
27
,
27
,
27
,
27
,
27
,
27
,
27
,
27
,
27
,
27
,
28
,
28
,
28
,
28
,
28
,
28
,
28
,
28
,
28
,
28
,
29
,
29
,
29
,
29
,
29
,
29
,
29
,
29
,
29
,
29
,
29
,
29
,
30
,
30
,
30
,
30
,
30
30
};
};
uint32_t
dB_fix_x10_tbl_low
[
128
]
=
{
uint32_t
dB_fix_x10_tbl_low
[
128
]
=
{
0
,
0
,
0
,
0
,
30
,
30
,
48
,
48
,
60
,
60
,
70
,
70
,
78
,
78
,
85
,
85
,
90
,
90
,
95
,
95
,
100
,
100
,
104
,
104
,
108
,
108
,
111
,
111
,
115
,
115
,
118
,
118
,
120
,
120
,
123
,
123
,
126
,
126
,
128
,
128
,
130
,
130
,
132
,
132
,
134
,
134
,
136
,
136
,
138
,
138
,
140
,
140
,
141
,
141
,
143
,
143
,
145
,
145
,
146
,
146
,
148
,
148
,
149
,
149
,
151
,
151
,
152
,
152
,
153
,
153
,
154
,
154
,
156
,
156
,
157
,
157
,
158
,
158
,
159
,
159
,
160
,
160
,
161
,
161
,
162
,
162
,
163
,
163
,
164
,
164
,
165
,
165
,
166
,
166
,
167
,
167
,
168
,
168
,
169
,
169
,
170
,
170
,
171
,
171
,
172
,
172
,
172
,
172
,
173
,
173
,
174
,
174
,
175
,
175
,
176
,
176
,
176
,
176
,
177
,
177
,
178
,
178
,
179
,
179
,
179
,
179
,
180
,
180
,
181
,
181
,
181
,
181
,
182
,
182
,
183
,
183
,
183
,
183
,
184
,
184
,
185
,
185
,
185
,
185
,
186
,
186
,
186
,
186
,
187
,
187
,
188
,
188
,
188
,
188
,
189
,
189
,
189
,
189
,
190
,
190
,
190
,
190
,
191
,
191
,
191
,
191
,
192
,
192
,
192
,
192
,
193
,
193
,
193
,
193
,
194
,
194
,
194
,
194
,
195
,
195
,
195
,
195
,
196
,
196
,
196
,
196
,
197
,
197
,
197
,
197
,
198
,
198
,
198
,
198
,
199
,
199
,
199
,
199
,
200
,
200
,
200
,
200
,
200
,
200
,
201
,
201
,
201
,
201
,
202
,
202
,
202
,
202
,
203
,
203
,
203
,
203
,
203
,
203
,
204
,
204
,
204
,
204
,
205
,
205
,
205
,
205
,
205
,
205
,
206
,
206
,
206
,
206
,
206
,
206
,
207
,
207
,
207
,
207
,
208
,
208
,
208
,
208
,
208
,
208
,
209
,
209
,
209
,
209
,
209
,
209
,
210
,
210
,
210
,
210
,
210
210
};
};
/*
/*
...
@@ -855,35 +855,35 @@ int8_t dB_fixed(int x) {
...
@@ -855,35 +855,35 @@ int8_t dB_fixed(int x) {
*/
*/
int16_t
dB_fixed_x10
(
uint32_t
x
)
{
int16_t
dB_fixed_x10
(
uint32_t
x
)
{
int16_t
dB_power
=
0
;
int16_t
dB_power
=
0
;
//for new algorithm
//for new algorithm
uint32_t
cnt
;
uint32_t
cnt
;
uint32_t
Exponent
;
uint32_t
Exponent
;
uint32_t
Mantissa
;
uint32_t
Mantissa
;
uint32_t
shift_right
;
uint32_t
shift_right
;
uint32_t
tbl_resolution
=
7
;
uint32_t
tbl_resolution
=
7
;
uint32_t
tbl_addr_mask
;
uint32_t
tbl_addr_mask
;
if
(
x
<
128
){
//OAI alogrithm
if
(
x
<
128
){
//OAI alogrithm
dB_power
=
dB_fix_x10_tbl_low
[
x
];
dB_power
=
dB_fix_x10_tbl_low
[
x
];
}
}
else
{
//new algorithm
else
{
//new algorithm
tbl_addr_mask
=
0x0000007Fu
;
// (1 << tbl_resolution) - 1;//i.e. 0x0000007F
tbl_addr_mask
=
0x0000007Fu
;
// (1 << tbl_resolution) - 1;//i.e. 0x0000007F
Mantissa
=
0
;
Mantissa
=
0
;
Exponent
=
0
;
Exponent
=
0
;
for
(
cnt
=
0
;
cnt
<
32
;
cnt
++
)
{
for
(
cnt
=
0
;
cnt
<
32
;
cnt
++
)
{
if
((
bit_seach_mask
[
cnt
]
&
x
)
!=
0
)
{
if
((
bit_seach_mask
[
cnt
]
&
x
)
!=
0
)
{
Exponent
=
bit_seach_res
[
cnt
];
Exponent
=
bit_seach_res
[
cnt
];
Mantissa
=
x
&
(
~
bit_seach_mask
[
cnt
]);
Mantissa
=
x
&
(
~
bit_seach_mask
[
cnt
]);
break
;
break
;
}
}
}
}
shift_right
=
Exponent
-
tbl_resolution
;
shift_right
=
Exponent
-
tbl_resolution
;
Mantissa
=
(
Mantissa
>>
shift_right
)
&
tbl_addr_mask
;
Mantissa
=
(
Mantissa
>>
shift_right
)
&
tbl_addr_mask
;
dB_power
=
dB_fix_x10_tbl
[
Mantissa
]
+
Exponent
*
30u
;
dB_power
=
dB_fix_x10_tbl
[
Mantissa
]
+
Exponent
*
30u
;
}
}
return
dB_power
;
return
dB_power
;
}
}
int16_t
dB_fixed_times10
(
uint32_t
x
)
int16_t
dB_fixed_times10
(
uint32_t
x
)
...
...
This diff is collapsed.
Click to expand it.
openair1/PHY/TOOLS/signal_energy.c
View file @
b0f5a37f
...
@@ -68,86 +68,39 @@ int32_t subcarrier_energy(int32_t *input,uint32_t length, int32_t *subcarrier_en
...
@@ -68,86 +68,39 @@ int32_t subcarrier_energy(int32_t *input,uint32_t length, int32_t *subcarrier_en
}
}
#endif
#endif
//int32_t signal_energy(int32_t *input,uint32_t length)
//{
//
// int32_t i;
// int32_t temp,temp2;
// register __m64 mm0,mm1,mm2,mm3;
// __m64 *in = (__m64 *)input;
//
//
// mm0 = _mm_setzero_si64();//pxor(mm0,mm0);
// mm3 = _mm_setzero_si64();//pxor(mm3,mm3);
//
// for (i=0; i<length>>1; i++) {
//
// mm1 = in[i];
// mm2 = mm1;
// mm1 = _m_pmaddwd(mm1,mm1);
// mm1 = _m_psradi(mm1,shift);// shift any 32 bits blocs of the word by the value shift
// mm0 = _m_paddd(mm0,mm1);// add the two 64 bits words 4 bytes by 4 bytes
// // mm2 = _m_psrawi(mm2,shift_DC);
// mm3 = _m_paddw(mm3,mm2);// add the two 64 bits words 2 bytes by 2 bytes
// }
//
// mm1 = mm0;
// mm0 = _m_psrlqi(mm0,32);
// mm0 = _m_paddd(mm0,mm1);
// temp = _m_to_int(mm0);
// temp/=length;
// temp<<=shift; // this is the average of x^2
//
// // now remove the DC component
//
//
// mm2 = _m_psrlqi(mm3,32);
// mm2 = _m_paddw(mm2,mm3);
// mm2 = _m_pmaddwd(mm2,mm2);
// temp2 = _m_to_int(mm2);
// temp2/=(length*length);
// // temp2<<=(2*shift_DC);
// temp -= temp2;
//
// _mm_empty();
// _m_empty();
//
// return((temp>0)?temp:1);
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Average Power calculation with DC removing
// Average Power calculation with DC removing
//-----------------------------------------------------------------
//-----------------------------------------------------------------
int32_t
signal_energy
(
int32_t
*
input
,
uint32_t
length
)
int32_t
signal_energy
(
int32_t
*
input
,
uint32_t
length
)
{
{
uint32_t
i
;
uint32_t
i
;
int32_t
temp
;
int32_t
temp
;
__m128i
in
,
in_clp
,
i16_min
,
coe1
;
__m128i
in
,
in_clp
,
i16_min
,
coe1
;
__m128
num0
,
num1
,
num2
,
num3
,
recp1
;
__m128
num0
,
num1
,
num2
,
num3
,
recp1
;
//init
//init
num0
=
_mm_setzero_ps
();
num0
=
_mm_setzero_ps
();
num1
=
_mm_setzero_ps
();
num1
=
_mm_setzero_ps
();
i16_min
=
_mm_set1_epi16
(
SHRT_MIN
);
i16_min
=
_mm_set1_epi16
(
SHRT_MIN
);
coe1
=
_mm_set1_epi16
(
1
);
coe1
=
_mm_set1_epi16
(
1
);
recp1
=
_mm_rcp_ps
(
_mm_cvtepi32_ps
(
_mm_set1_epi32
(
length
)));
recp1
=
_mm_rcp_ps
(
_mm_cvtepi32_ps
(
_mm_set1_epi32
(
length
)));
//Acc
//Acc
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
in_clp
=
_mm_subs_epi16
(
in
,
_mm_cmpeq_epi16
(
in
,
i16_min
));
//if in=SHRT_MIN in+1, else in
in_clp
=
_mm_subs_epi16
(
in
,
_mm_cmpeq_epi16
(
in
,
i16_min
));
//if in=SHRT_MIN in+1, else in
num0
=
_mm_add_ps
(
num0
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in_clp
,
in_clp
)));
num0
=
_mm_add_ps
(
num0
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in_clp
,
in_clp
)));
num1
=
_mm_add_ps
(
num1
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in
,
coe1
)));
//DC
num1
=
_mm_add_ps
(
num1
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in
,
coe1
)));
//DC
input
+=
4
;
input
+=
4
;
}
}
//Ave
//Ave
num2
=
_mm_dp_ps
(
num0
,
recp1
,
0xFF
);
//AC power
num2
=
_mm_dp_ps
(
num0
,
recp1
,
0xFF
);
//AC power
num3
=
_mm_dp_ps
(
num1
,
recp1
,
0xFF
);
//DC
num3
=
_mm_dp_ps
(
num1
,
recp1
,
0xFF
);
//DC
num3
=
_mm_mul_ps
(
num3
,
num3
);
//DC power
num3
=
_mm_mul_ps
(
num3
,
num3
);
//DC power
//remove DC
//remove DC
temp
=
_mm_cvtsi128_si32
(
_mm_cvttps_epi32
(
_mm_sub_ps
(
num2
,
num3
)));
temp
=
_mm_cvtsi128_si32
(
_mm_cvttps_epi32
(
_mm_sub_ps
(
num2
,
num3
)));
return
temp
;
return
temp
;
}
}
int32_t
signal_energy_amp_shift
(
int32_t
*
input
,
uint32_t
length
)
int32_t
signal_energy_amp_shift
(
int32_t
*
input
,
uint32_t
length
)
...
@@ -198,64 +151,6 @@ int32_t signal_energy_amp_shift(int32_t *input,uint32_t length)
...
@@ -198,64 +151,6 @@ int32_t signal_energy_amp_shift(int32_t *input,uint32_t length)
int32_t
signal_energy_nodc
(
int32_t
*
input
,
uint32_t
length
)
int32_t
signal_energy_nodc
(
int32_t
*
input
,
uint32_t
length
)
{
{
// int32_t i;
// int32_t temp;
// register __m64 mm0,mm1;//,mm2,mm3;
// __m64 *in = (__m64 *)input;
//
//#ifdef MAIN
// int16_t *printb;
//#endif
//
// mm0 = _mm_setzero_si64();//_pxor(mm0,mm0);
// // mm3 = _mm_setzero_si64();//pxor(mm3,mm3);
//
// for (i=0; i<length>>1; i++) {
//
// mm1 = in[i];
// mm1 = _m_pmaddwd(mm1,mm1);// SIMD complex multiplication
// mm1 = _m_psradi(mm1,shift);
// mm0 = _m_paddd(mm0,mm1);
// // temp2 = mm0;
// // printf("%d %d\n",((int *)&in[i])[0],((int *)&in[i])[1]);
//
//
// // printb = (int16_t *)&mm2;
// // printf("mm2 %d : %d %d %d %d\n",i,printb[0],printb[1],printb[2],printb[3]);
//
//
// }
//
// /*
// #ifdef MAIN
// printb = (int16_t *)&mm3;
// printf("%d %d %d %d\n",printb[0],printb[1],printb[2],printb[3]);
// #endif
// */
// mm1 = mm0;
//
// mm0 = _m_psrlqi(mm0,32);
//
// mm0 = _m_paddd(mm0,mm1);
//
// temp = _m_to_int(mm0);
//
// temp/=length;
// temp<<=shift; // this is the average of x^2
//
//#ifdef MAIN
// printf("E x^2 = %d\n",temp);
//#endif
// _mm_empty();
// _m_empty();
//
//
//
// return((temp>0)?temp:1);
int32_t
i
;
int32_t
i
;
int32_t
temp
;
int32_t
temp
;
...
@@ -266,9 +161,9 @@ int32_t signal_energy_nodc(int32_t *input,uint32_t length)
...
@@ -266,9 +161,9 @@ int32_t signal_energy_nodc(int32_t *input,uint32_t length)
mm0
=
_mm_setzero_ps
();
mm0
=
_mm_setzero_ps
();
//Acc
//Acc
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
mm0
=
_mm_add_ps
(
mm0
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in
,
in
)));
mm0
=
_mm_add_ps
(
mm0
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in
,
in
)));
input
+=
4
;
input
+=
4
;
}
}
//Ave
//Ave
temp
=
(
int
)((((
float
*
)
&
mm0
)[
0
]
+
temp
=
(
int
)((((
float
*
)
&
mm0
)[
0
]
+
...
@@ -277,8 +172,6 @@ int32_t signal_energy_nodc(int32_t *input,uint32_t length)
...
@@ -277,8 +172,6 @@ int32_t signal_energy_nodc(int32_t *input,uint32_t length)
((
float
*
)
&
mm0
)[
3
])
/
(
float
)
length
);
((
float
*
)
&
mm0
)[
3
])
/
(
float
)
length
);
return
temp
;
return
temp
;
}
}
#elif defined(__arm__)
#elif defined(__arm__)
...
@@ -429,62 +322,62 @@ main(int argc,char **argv)
...
@@ -429,62 +322,62 @@ main(int argc,char **argv)
int32_t
signal_power
(
int32_t
*
input
,
uint32_t
length
)
int32_t
signal_power
(
int32_t
*
input
,
uint32_t
length
)
{
{
uint32_t
i
;
uint32_t
i
;
int32_t
temp
;
int32_t
temp
;
__m128i
in
,
in_clp
,
i16_min
;
__m128i
in
,
in_clp
,
i16_min
;
__m128
num0
,
num1
;
__m128
num0
,
num1
;
__m128
recp1
;
__m128
recp1
;
//init
//init
num0
=
_mm_setzero_ps
();
num0
=
_mm_setzero_ps
();
i16_min
=
_mm_set1_epi16
(
SHRT_MIN
);
i16_min
=
_mm_set1_epi16
(
SHRT_MIN
);
recp1
=
_mm_rcp_ps
(
_mm_cvtepi32_ps
(
_mm_set1_epi32
(
length
)));
recp1
=
_mm_rcp_ps
(
_mm_cvtepi32_ps
(
_mm_set1_epi32
(
length
)));
//Acc
//Acc
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
in_clp
=
_mm_subs_epi16
(
in
,
_mm_cmpeq_epi16
(
in
,
i16_min
));
//if in=SHRT_MIN in+1, else in
in_clp
=
_mm_subs_epi16
(
in
,
_mm_cmpeq_epi16
(
in
,
i16_min
));
//if in=SHRT_MIN in+1, else in
num0
=
_mm_add_ps
(
num0
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in_clp
,
in_clp
)));
num0
=
_mm_add_ps
(
num0
,
_mm_cvtepi32_ps
(
_mm_madd_epi16
(
in_clp
,
in_clp
)));
input
+=
4
;
input
+=
4
;
}
}
//Ave
//Ave
num1
=
_mm_dp_ps
(
num0
,
recp1
,
0xFF
);
num1
=
_mm_dp_ps
(
num0
,
recp1
,
0xFF
);
temp
=
_mm_cvtsi128_si32
(
_mm_cvttps_epi32
(
num1
));
temp
=
_mm_cvtsi128_si32
(
_mm_cvttps_epi32
(
num1
));
return
temp
;
return
temp
;
}
}
int32_t
interference_power
(
int32_t
*
input
,
uint32_t
length
)
int32_t
interference_power
(
int32_t
*
input
,
uint32_t
length
)
{
{
uint32_t
i
;
uint32_t
i
;
int32_t
temp
;
int32_t
temp
;
__m128i
in
,
in_clp
,
i16_min
;
__m128i
in
,
in_clp
,
i16_min
;
__m128i
num0
,
num1
,
num2
,
num3
;
__m128i
num0
,
num1
,
num2
,
num3
;
__m128
num4
,
num5
,
num6
;
__m128
num4
,
num5
,
num6
;
__m128
recp1
;
__m128
recp1
;
//init
//init
i16_min
=
_mm_set1_epi16
(
SHRT_MIN
);
i16_min
=
_mm_set1_epi16
(
SHRT_MIN
);
num5
=
_mm_setzero_ps
();
num5
=
_mm_setzero_ps
();
recp1
=
_mm_rcp_ps
(
_mm_cvtepi32_ps
(
_mm_set1_epi32
(
length
>>
2
)));
// 1/n, n= length/4
recp1
=
_mm_rcp_ps
(
_mm_cvtepi32_ps
(
_mm_set1_epi32
(
length
>>
2
)));
// 1/n, n= length/4
//Acc
//Acc
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
for
(
i
=
0
;
i
<
(
length
>>
2
);
i
++
)
{
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
in
=
_mm_loadu_si128
((
__m128i
*
)
input
);
in_clp
=
_mm_subs_epi16
(
in
,
_mm_cmpeq_epi16
(
in
,
i16_min
));
//if in=SHRT_MIN, in+1, else in
in_clp
=
_mm_subs_epi16
(
in
,
_mm_cmpeq_epi16
(
in
,
i16_min
));
//if in=SHRT_MIN, in+1, else in
num0
=
_mm_cvtepi16_epi32
(
in_clp
);
//lower 2 complex [0], [1]
num0
=
_mm_cvtepi16_epi32
(
in_clp
);
//lower 2 complex [0], [1]
num1
=
_mm_cvtepi16_epi32
(
_mm_shuffle_epi32
(
in_clp
,
0x4E
));
//upper 2 complex [2], [3]
num1
=
_mm_cvtepi16_epi32
(
_mm_shuffle_epi32
(
in_clp
,
0x4E
));
//upper 2 complex [2], [3]
num2
=
_mm_srai_epi32
(
_mm_add_epi32
(
num0
,
num1
),
0x01
);
//average A=complex( [0] + [2] ) / 2, B=complex( [1] + [3] ) / 2
num2
=
_mm_srai_epi32
(
_mm_add_epi32
(
num0
,
num1
),
0x01
);
//average A=complex( [0] + [2] ) / 2, B=complex( [1] + [3] ) / 2
num3
=
_mm_sub_epi32
(
num2
,
_mm_shuffle_epi32
(
num2
,
0x4E
));
//complexA-complexB, B-A
num3
=
_mm_sub_epi32
(
num2
,
_mm_shuffle_epi32
(
num2
,
0x4E
));
//complexA-complexB, B-A
num4
=
_mm_dp_ps
(
_mm_cvtepi32_ps
(
num3
),
_mm_cvtepi32_ps
(
num3
),
0x3F
);
//C = num3 lower complex power, C, C, C
num4
=
_mm_dp_ps
(
_mm_cvtepi32_ps
(
num3
),
_mm_cvtepi32_ps
(
num3
),
0x3F
);
//C = num3 lower complex power, C, C, C
num5
=
_mm_add_ps
(
num5
,
num4
);
//Acc Cn, Cn, Cn, Cn,
num5
=
_mm_add_ps
(
num5
,
num4
);
//Acc Cn, Cn, Cn, Cn,
input
+=
4
;
input
+=
4
;
}
}
//Interference ve
//Interference ve
num6
=
_mm_mul_ps
(
num5
,
recp1
);
//Cn / n
num6
=
_mm_mul_ps
(
num5
,
recp1
);
//Cn / n
temp
=
_mm_cvtsi128_si32
(
_mm_cvttps_epi32
(
num6
));
temp
=
_mm_cvtsi128_si32
(
_mm_cvttps_epi32
(
num6
));
return
temp
;
return
temp
;
}
}
This diff is collapsed.
Click to expand it.
openair1/SCHED/fapi_l1.c
View file @
b0f5a37f
...
@@ -1008,16 +1008,15 @@ void schedule_response(Sched_Rsp_t *Sched_INFO, L1_rxtx_proc_t *proc) {
...
@@ -1008,16 +1008,15 @@ void schedule_response(Sched_Rsp_t *Sched_INFO, L1_rxtx_proc_t *proc) {
UL_req
->
ul_config_request_body
.
number_of_pdus
=
0
;
UL_req
->
ul_config_request_body
.
number_of_pdus
=
0
;
number_ul_pdu
=
0
;
number_ul_pdu
=
0
;
}
else
if
(
RC
.
mac
[
Mod_id
]
->
scheduler_mode
==
SCHED_MODE_FAIR_RR
)
{
}
else
if
(
RC
.
mac
[
Mod_id
]
->
scheduler_mode
==
SCHED_MODE_FAIR_RR
)
{
if
(
ulsch_pdu_num
<=
RC
.
rrc
[
Mod_id
]
->
configuration
.
radioresourceconfig
[
CC_id
].
ue_multiple_max
){
if
(
ulsch_pdu_num
<=
RC
.
rrc
[
Mod_id
]
->
configuration
.
radioresourceconfig
[
CC_id
].
ue_multiple_max
){
//LOG_D(PHY, "UL_CONFIG to send to PNF\n");
UL_req
->
sfn_sf
=
frame
<<
4
|
subframe
;
UL_req
->
sfn_sf
=
frame
<<
4
|
subframe
;
oai_nfapi_ul_config_req
(
UL_req
);
oai_nfapi_ul_config_req
(
UL_req
);
UL_req
->
ul_config_request_body
.
number_of_pdus
=
0
;
UL_req
->
ul_config_request_body
.
number_of_pdus
=
0
;
number_ul_pdu
=
0
;
number_ul_pdu
=
0
;
}
else
{
}
else
{
LOG_E
(
MAC
,
"NFAPI: frame %d subframe %d ul_req num %d ul pdu %d
\n
"
,
LOG_E
(
MAC
,
"NFAPI: frame %d subframe %d ul_req num %d ul pdu %d
\n
"
,
frame
,
subframe
,
number_ul_pdu
,
ulsch_pdu_num
);
frame
,
subframe
,
number_ul_pdu
,
ulsch_pdu_num
);
}
}
}
}
}
}
}
else
{
}
else
{
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/MAC/defs.h
deleted
100644 → 0
View file @
88699deb
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.1 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file LAYER2/MAC/defs.h
* \brief MAC data structures, constant, and function prototype
* \author Navid Nikaein and Raymond Knopp
* \date 2011
* \version 0.5
* \email navid.nikaein@eurecom.fr
*/
/** @defgroup _oai2 openair2 Reference Implementation
* @ingroup _ref_implementation_
* @{
*/
/*@}*/
#ifndef __LAYER2_MAC_DEFS_H__
#define __LAYER2_MAC_DEFS_H__
#ifdef USER_MODE
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#endif
//#include "COMMON/openair_defs.h"
#include "PHY/defs.h"
#include "PHY/LTE_TRANSPORT/defs.h"
#include "COMMON/platform_constants.h"
#include "BCCH-BCH-Message.h"
#include "RadioResourceConfigCommon.h"
#include "RadioResourceConfigDedicated.h"
#include "MeasGapConfig.h"
#include "SchedulingInfoList.h"
#include "TDD-Config.h"
#include "RACH-ConfigCommon.h"
#include "MeasObjectToAddModList.h"
#include "MobilityControlInfo.h"
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
#include "MBSFN-AreaInfoList-r9.h"
#include "MBSFN-SubframeConfigList.h"
#include "PMCH-InfoList-r9.h"
#include "SCellToAddMod-r10.h"
#endif
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
#include "SystemInformationBlockType1-v1310-IEs.h"
#endif
#include "nfapi_interface.h"
#include "PHY_INTERFACE/IF_Module.h"
/** @defgroup _mac MAC
* @ingroup _oai2
* @{
*/
#define BCCH_PAYLOAD_SIZE_MAX 128
#define CCCH_PAYLOAD_SIZE_MAX 128
#define PCCH_PAYLOAD_SIZE_MAX 128
#define RAR_PAYLOAD_SIZE_MAX 128
#define SCH_PAYLOAD_SIZE_MAX 4096
/// Logical channel ids from 36-311 (Note BCCH is not specified in 36-311, uses the same as first DRB)
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
// Mask for identifying subframe for MBMS
#define MBSFN_TDD_SF3 0x80// for TDD
#define MBSFN_TDD_SF4 0x40
#define MBSFN_TDD_SF7 0x20
#define MBSFN_TDD_SF8 0x10
#define MBSFN_TDD_SF9 0x08
#define MBSFN_FDD_SF1 0x80// for FDD
#define MBSFN_FDD_SF2 0x40
#define MBSFN_FDD_SF3 0x20
#define MBSFN_FDD_SF6 0x10
#define MBSFN_FDD_SF7 0x08
#define MBSFN_FDD_SF8 0x04
#define MAX_MBSFN_AREA 8
#define MAX_PMCH_perMBSFN 15
/*!\brief MAX MCCH payload size */
#define MCCH_PAYLOAD_SIZE_MAX 128
//#define MCH_PAYLOAD_SIZE_MAX 16384// this value is using in case mcs and TBS index are high
#endif
#ifdef USER_MODE
#define printk printf
#endif //USER_MODE
/*!\brief Maximum number of logical channl group IDs */
#define MAX_NUM_LCGID 4
/*!\brief logical channl group ID 0 */
#define LCGID0 0
/*!\brief logical channl group ID 1 */
#define LCGID1 1
/*!\brief logical channl group ID 2 */
#define LCGID2 2
/*!\brief logical channl group ID 3 */
#define LCGID3 3
/*!\brief Maximum number of logical chanels */
#define MAX_NUM_LCID 11
/*!\brief Maximum number od control elemenets */
#define MAX_NUM_CE 5
/*!\brief Maximum number of random access process */
#define NB_RA_PROC_MAX 4
/*!\brief size of buffer status report table */
#define BSR_TABLE_SIZE 64
/*!\brief The power headroom reporting range is from -23 ...+40 dB and beyond, with step 1 */
#define PHR_MAPPING_OFFSET 23 // if ( x>= -23 ) val = floor (x + 23)
/*!\brief maximum number of resource block groups */
#define N_RBG_MAX 25 // for 20MHz channel BW
/*!\brief minimum value for channel quality indicator */
#define MIN_CQI_VALUE 0
/*!\brief maximum value for channel quality indicator */
#define MAX_CQI_VALUE 15
/*!\briefmaximum number of supported bandwidth (1.4, 5, 10, 20 MHz) */
#define MAX_SUPPORTED_BW 4
/*!\brief CQI values range from 1 to 15 (4 bits) */
#define CQI_VALUE_RANGE 16
/*!\brief value for indicating BSR Timer is not running */
#define MAC_UE_BSR_TIMER_NOT_RUNNING (0xFFFF)
#define LCID_EMPTY 0
#define LCID_NOT_EMPTY 1
/*!\brief minimum RLC PDU size to be transmitted = min RLC Status PDU or RLC UM PDU SN 5 bits */
#define MIN_RLC_PDU_SIZE (2)
/*!\brief minimum MAC data needed for transmitting 1 min RLC PDU size + 1 byte MAC subHeader */
#define MIN_MAC_HDR_RLC_SIZE (1 + MIN_RLC_PDU_SIZE)
/*!\brief maximum number of slices / groups */
#define MAX_NUM_SLICES 4
/*
* eNB part
*/
/*
* UE/ENB common part
*/
/*!\brief MAC header of Random Access Response for Random access preamble identifier (RAPID) */
typedef
struct
{
uint8_t
RAPID
:
6
;
uint8_t
T
:
1
;
uint8_t
E
:
1
;
}
__attribute__
((
__packed__
))
RA_HEADER_RAPID
;
/*!\brief MAC header of Random Access Response for backoff indicator (BI)*/
typedef
struct
{
uint8_t
BI
:
4
;
uint8_t
R
:
2
;
uint8_t
T
:
1
;
uint8_t
E
:
1
;
}
__attribute__
((
__packed__
))
RA_HEADER_BI
;
/*
typedef struct {
uint64_t padding:16;
uint64_t t_crnti:16;
uint64_t hopping_flag:1;
uint64_t rb_alloc:10;
uint64_t mcs:4;
uint64_t TPC:3;
uint64_t UL_delay:1;
uint64_t cqi_req:1;
uint64_t Timing_Advance_Command:11; // first/2nd octet LSB
uint64_t R:1; // octet MSB
} __attribute__((__packed__))RAR_PDU;
typedef struct {
uint64_t padding:16;
uint64_t R:1; // octet MSB
uint64_t Timing_Advance_Command:11; // first/2nd octet LSB
uint64_t cqi_req:1;
uint64_t UL_delay:1;
uint64_t TPC:3;
uint64_t mcs:4;
uint64_t rb_alloc:10;
uint64_t hopping_flag:1;
uint64_t t_crnti:16;
} __attribute__((__packed__))RAR_PDU;
#define sizeof_RAR_PDU 6
*/
/*!\brief MAC subheader short with 7bit Length field */
typedef
struct
{
uint8_t
LCID
:
5
;
// octet 1 LSB
uint8_t
E
:
1
;
uint8_t
R
:
2
;
// octet 1 MSB
uint8_t
L
:
7
;
// octet 2 LSB
uint8_t
F
:
1
;
// octet 2 MSB
}
__attribute__
((
__packed__
))
SCH_SUBHEADER_SHORT
;
/*!\brief MAC subheader long with 15bit Length field */
typedef
struct
{
uint8_t
LCID
:
5
;
// octet 1 LSB
uint8_t
E
:
1
;
uint8_t
R
:
2
;
// octet 1 MSB
uint8_t
L_MSB
:
7
;
uint8_t
F
:
1
;
// octet 2 MSB
uint8_t
L_LSB
:
8
;
uint8_t
padding
;
}
__attribute__
((
__packed__
))
SCH_SUBHEADER_LONG
;
/*!\brief MAC subheader short without length field */
typedef
struct
{
uint8_t
LCID
:
5
;
uint8_t
E
:
1
;
uint8_t
R
:
2
;
}
__attribute__
((
__packed__
))
SCH_SUBHEADER_FIXED
;
/*!\brief mac control element: short buffer status report for a specific logical channel group ID*/
typedef
struct
{
uint8_t
Buffer_size
:
6
;
// octet 1 LSB
uint8_t
LCGID
:
2
;
// octet 1 MSB
}
__attribute__
((
__packed__
))
BSR_SHORT
;
typedef
BSR_SHORT
BSR_TRUNCATED
;
/*!\brief mac control element: long buffer status report for all logical channel group ID*/
typedef
struct
{
uint8_t
Buffer_size3
:
6
;
uint8_t
Buffer_size2
:
6
;
uint8_t
Buffer_size1
:
6
;
uint8_t
Buffer_size0
:
6
;
}
__attribute__
((
__packed__
))
BSR_LONG
;
#define BSR_LONG_SIZE (sizeof(BSR_LONG))
/*!\brief mac control element: timing advance */
typedef
struct
{
uint8_t
TA
:
6
;
uint8_t
R
:
2
;
}
__attribute__
((
__packed__
))
TIMING_ADVANCE_CMD
;
/*!\brief mac control element: power headroom report */
typedef
struct
{
uint8_t
PH
:
6
;
uint8_t
R
:
2
;
}
__attribute__
((
__packed__
))
POWER_HEADROOM_CMD
;
/*! \brief MIB payload */
typedef
struct
{
uint8_t
payload
[
3
]
;
}
__attribute__
((
__packed__
))
MIB_PDU
;
/*! \brief CCCH payload */
typedef
struct
{
uint8_t
payload
[
CCCH_PAYLOAD_SIZE_MAX
]
;
}
__attribute__
((
__packed__
))
CCCH_PDU
;
/*! \brief BCCH payload */
typedef
struct
{
uint8_t
payload
[
BCCH_PAYLOAD_SIZE_MAX
]
;
}
__attribute__
((
__packed__
))
BCCH_PDU
;
/*! \brief RAR payload */
typedef
struct
{
uint8_t
payload
[
RAR_PAYLOAD_SIZE_MAX
];
}
__attribute__
((
__packed__
))
RAR_PDU
;
/*! \brief BCCH payload */
typedef
struct
{
uint8_t
payload
[
PCCH_PAYLOAD_SIZE_MAX
]
;
}
__attribute__
((
__packed__
))
PCCH_PDU
;
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
/*! \brief MCCH payload */
typedef
struct
{
uint8_t
payload
[
MCCH_PAYLOAD_SIZE_MAX
]
;
}
__attribute__
((
__packed__
))
MCCH_PDU
;
/*!< \brief MAC control element for activation and deactivation of component carriers */
typedef
struct
{
uint8_t
C7
:
1
;
/*!< \brief Component carrier 7 */
uint8_t
C6
:
1
;
/*!< \brief Component carrier 6 */
uint8_t
C5
:
1
;
/*!< \brief Component carrier 5 */
uint8_t
C4
:
1
;
/*!< \brief Component carrier 4 */
uint8_t
C3
:
1
;
/*!< \brief Component carrier 3 */
uint8_t
C2
:
1
;
/*!< \brief Component carrier 2 */
uint8_t
C1
:
1
;
/*!< \brief Component carrier 1 */
uint8_t
R
:
1
;
/*!< \brief Reserved */
}
__attribute__
((
__packed__
))
CC_ELEMENT
;
/*! \brief MAC control element: MCH Scheduling Information */
typedef
struct
{
uint8_t
stop_sf_MSB
:
3
;
// octet 1 LSB
uint8_t
lcid
:
5
;
// octet 2 MSB
uint8_t
stop_sf_LSB
:
8
;
}
__attribute__
((
__packed__
))
MSI_ELEMENT
;
#endif
/*! \brief Values of CCCH LCID for DLSCH */
#define CCCH_LCHANID 0
/*!\brief Values of BCCH logical channel (fake)*/
#define BCCH 3 // SI
/*!\brief Values of PCCH logical channel (fake)*/
#define PCCH 4 // Paging
/*!\brief Values of PCCH logical channel (fake) */
#define MIBCH 5 // MIB
/*!\brief Values of BCCH SIB1_BR logical channel (fake) */
#define BCCH_SIB1_BR 6 // SIB1_BR
/*!\brief Values of BCCH SIB_BR logical channel (fake) */
#define BCCH_SI_BR 7 // SI-BR
/*!\brief Value of CCCH / SRB0 logical channel */
#define CCCH 0 // srb0
/*!\brief DCCH / SRB1 logical channel */
#define DCCH 1 // srb1
/*!\brief DCCH1 / SRB2 logical channel */
#define DCCH1 2 // srb2
/*!\brief DTCH DRB1 logical channel */
#define DTCH 3 // LCID
/*!\brief MCCH logical channel */
#define MCCH 4
/*!\brief MTCH logical channel */
#define MTCH 1
// DLSCH LCHAN ID
/*!\brief LCID of UE contention resolution identity for DLSCH*/
#define UE_CONT_RES 28
/*!\brief LCID of timing advance for DLSCH */
#define TIMING_ADV_CMD 29
/*!\brief LCID of discontinous reception mode for DLSCH */
#define DRX_CMD 30
/*!\brief LCID of padding LCID for DLSCH */
#define SHORT_PADDING 31
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
// MCH LCHAN IDs (table6.2.1-4 TS36.321)
/*!\brief LCID of MCCH for DL */
#define MCCH_LCHANID 0
/*!\brief LCID of MCH scheduling info for DL */
#define MCH_SCHDL_INFO 3
/*!\brief LCID of Carrier component activation/deactivation */
#define CC_ACT_DEACT 27
#endif
// ULSCH LCHAN IDs
/*!\brief LCID of extended power headroom for ULSCH */
#define EXTENDED_POWER_HEADROOM 25
/*!\brief LCID of power headroom for ULSCH */
#define POWER_HEADROOM 26
/*!\brief LCID of CRNTI for ULSCH */
#define CRNTI 27
/*!\brief LCID of truncated BSR for ULSCH */
#define TRUNCATED_BSR 28
/*!\brief LCID of short BSR for ULSCH */
#define SHORT_BSR 29
/*!\brief LCID of long BSR for ULSCH */
#define LONG_BSR 30
/*!\bitmaps for BSR Triggers */
#define BSR_TRIGGER_NONE (0)
/* No BSR Trigger */
#define BSR_TRIGGER_REGULAR (1)
/* For Regular and ReTxBSR Expiry Triggers */
#define BSR_TRIGGER_PERIODIC (2)
/* For BSR Periodic Timer Expiry Trigger */
#define BSR_TRIGGER_PADDING (4)
/* For Padding BSR Trigger */
/*! \brief Downlink SCH PDU Structure */
typedef
struct
{
uint8_t
payload
[
8
][
SCH_PAYLOAD_SIZE_MAX
];
uint16_t
Pdu_size
[
8
];
}
__attribute__
((
__packed__
))
DLSCH_PDU
;
/*! \brief MCH PDU Structure */
typedef
struct
{
int8_t
payload
[
SCH_PAYLOAD_SIZE_MAX
];
uint16_t
Pdu_size
;
uint8_t
mcs
;
uint8_t
sync_area
;
uint8_t
msi_active
;
uint8_t
mcch_active
;
uint8_t
mtch_active
;
}
__attribute__
((
__packed__
))
MCH_PDU
;
/*! \brief Uplink SCH PDU Structure */
typedef
struct
{
int8_t
payload
[
SCH_PAYLOAD_SIZE_MAX
];
/*!< \brief SACH payload */
uint16_t
Pdu_size
;
}
__attribute__
((
__packed__
))
ULSCH_PDU
;
#include "PHY/impl_defs_top.h"
/*!\brief UE ULSCH scheduling states*/
typedef
enum
{
S_UL_NONE
=
0
,
S_UL_WAITING
,
S_UL_SCHEDULED
,
S_UL_BUFFERED
,
S_UL_NUM_STATUS
}
UE_ULSCH_STATUS
;
/*!\brief UE DLSCH scheduling states*/
typedef
enum
{
S_DL_NONE
=
0
,
S_DL_WAITING
,
S_DL_SCHEDULED
,
S_DL_BUFFERED
,
S_DL_NUM_STATUS
}
UE_DLSCH_STATUS
;
/*!\brief scheduling policy for the contention-based access */
typedef
enum
{
CBA_ES
=
0
,
/// equal share of RB among groups w
CBA_ES_S
,
/// equal share of RB among groups with small allocation
CBA_PF
,
/// proportional fair (kind of)
CBA_PF_S
,
/// proportional fair (kind of) with small RB allocation
CBA_RS
/// random allocation
}
CBA_POLICY
;
/*! \brief temporary struct for ULSCH sched */
typedef
struct
{
rnti_t
rnti
;
uint16_t
subframe
;
uint16_t
serving_num
;
UE_ULSCH_STATUS
status
;
}
eNB_ULSCH_INFO
;
/*! \brief temp struct for DLSCH sched */
typedef
struct
{
rnti_t
rnti
;
uint16_t
weight
;
uint16_t
subframe
;
uint16_t
serving_num
;
UE_DLSCH_STATUS
status
;
}
eNB_DLSCH_INFO
;
/*! \brief eNB overall statistics */
typedef
struct
{
/// num BCCH PDU per CC
uint32_t
total_num_bcch_pdu
;
/// BCCH buffer size
uint32_t
bcch_buffer
;
/// total BCCH buffer size
uint32_t
total_bcch_buffer
;
/// BCCH MCS
uint32_t
bcch_mcs
;
/// num CCCH PDU per CC
uint32_t
total_num_ccch_pdu
;
/// BCCH buffer size
uint32_t
ccch_buffer
;
/// total BCCH buffer size
uint32_t
total_ccch_buffer
;
/// BCCH MCS
uint32_t
ccch_mcs
;
/// num active users
uint16_t
num_dlactive_UEs
;
/// available number of PRBs for a give SF
uint16_t
available_prbs
;
/// total number of PRB available for the user plane
uint32_t
total_available_prbs
;
/// aggregation
/// total avilable nccc : num control channel element
uint16_t
available_ncces
;
// only for a new transmission, should be extended for retransmission
// current dlsch bit rate for all transport channels
uint32_t
dlsch_bitrate
;
//
uint32_t
dlsch_bytes_tx
;
//
uint32_t
dlsch_pdus_tx
;
//
uint32_t
total_dlsch_bitrate
;
//
uint32_t
total_dlsch_bytes_tx
;
//
uint32_t
total_dlsch_pdus_tx
;
// here for RX
//
uint32_t
ulsch_bitrate
;
//
uint32_t
ulsch_bytes_rx
;
//
uint64_t
ulsch_pdus_rx
;
uint32_t
total_ulsch_bitrate
;
//
uint32_t
total_ulsch_bytes_rx
;
//
uint32_t
total_ulsch_pdus_rx
;
/// MAC agent-related stats
/// total number of scheduling decisions
int
sched_decisions
;
/// missed deadlines
int
missed_deadlines
;
}
eNB_STATS
;
/*! \brief eNB statistics for the connected UEs*/
typedef
struct
{
/// CRNTI of UE
rnti_t
crnti
;
///user id (rnti) of connected UEs
// rrc status
uint8_t
rrc_status
;
/// harq pid
uint8_t
harq_pid
;
/// harq rounf
uint8_t
harq_round
;
/// total available number of PRBs for a new transmission
uint16_t
rbs_used
;
/// total available number of PRBs for a retransmission
uint16_t
rbs_used_retx
;
/// total nccc used for a new transmission: num control channel element
uint16_t
ncce_used
;
/// total avilable nccc for a retransmission: num control channel element
uint16_t
ncce_used_retx
;
// mcs1 before the rate adaptaion
uint8_t
dlsch_mcs1
;
/// Target mcs2 after rate-adaptation
uint8_t
dlsch_mcs2
;
// current TBS with mcs2
uint32_t
TBS
;
// total TBS with mcs2
// uint32_t total_TBS;
// total rb used for a new transmission
uint32_t
total_rbs_used
;
// total rb used for retransmission
uint32_t
total_rbs_used_retx
;
/// TX
/// Num pkt
uint32_t
num_pdu_tx
[
NB_RB_MAX
];
/// num bytes
uint32_t
num_bytes_tx
[
NB_RB_MAX
];
/// num retransmission / harq
uint32_t
num_retransmission
;
/// instantaneous tx throughput for each TTI
// uint32_t tti_throughput[NB_RB_MAX];
/// overall
//
uint32_t
dlsch_bitrate
;
//total
uint32_t
total_dlsch_bitrate
;
/// headers+ CE + padding bytes for a MAC PDU
uint64_t
overhead_bytes
;
/// headers+ CE + padding bytes for a MAC PDU
uint64_t
total_overhead_bytes
;
/// headers+ CE + padding bytes for a MAC PDU
uint64_t
avg_overhead_bytes
;
// MAC multiplexed payload
uint64_t
total_sdu_bytes
;
// total MAC pdu bytes
uint64_t
total_pdu_bytes
;
// total num pdu
uint32_t
total_num_pdus
;
//
// uint32_t avg_pdu_size;
/// RX
/// PUCCH1a/b power (dBm)
int32_t
Po_PUCCH_dBm
;
/// Indicator that Po_PUCCH has been updated by PHY
int32_t
Po_PUCCH_update
;
/// Uplink measured RSSI
int32_t
UL_rssi
;
/// preassigned mcs after rate adaptation
uint8_t
ulsch_mcs1
;
/// adjusted mcs
uint8_t
ulsch_mcs2
;
/// estimated average pdu inter-departure time
uint32_t
avg_pdu_idt
;
/// estimated average pdu size
uint32_t
avg_pdu_ps
;
///
uint32_t
aggregated_pdu_size
;
uint32_t
aggregated_pdu_arrival
;
/// uplink transport block size
uint32_t
ulsch_TBS
;
/// total rb used for a new uplink transmission
uint32_t
num_retransmission_rx
;
/// total rb used for a new uplink transmission
uint32_t
rbs_used_rx
;
/// total rb used for a new uplink retransmission
uint32_t
rbs_used_retx_rx
;
/// total rb used for a new uplink transmission
uint32_t
total_rbs_used_rx
;
/// snr
int32_t
snr
;
/// target snr
int32_t
target_snr
;
/// num rx pdu
uint32_t
num_pdu_rx
[
NB_RB_MAX
];
/// num bytes rx
uint32_t
num_bytes_rx
[
NB_RB_MAX
];
/// instantaneous rx throughput for each TTI
// uint32_t tti_goodput[NB_RB_MAX];
/// errors
uint32_t
num_errors_rx
;
uint64_t
overhead_bytes_rx
;
/// headers+ CE + padding bytes for a MAC PDU
uint64_t
total_overhead_bytes_rx
;
/// headers+ CE + padding bytes for a MAC PDU
uint64_t
avg_overhead_bytes_rx
;
//
uint32_t
ulsch_bitrate
;
//total
uint32_t
total_ulsch_bitrate
;
/// overall
/// MAC pdu bytes
uint64_t
pdu_bytes_rx
;
/// total MAC pdu bytes
uint64_t
total_pdu_bytes_rx
;
/// total num pdu
uint32_t
total_num_pdus_rx
;
/// num of error pdus
uint32_t
total_num_errors_rx
;
}
eNB_UE_STATS
;
/*! \brief eNB template for UE context information */
typedef
struct
{
/// C-RNTI of UE
rnti_t
rnti
;
/// NDI from last scheduling
uint8_t
oldNDI
[
8
];
/// mcs1 from last scheduling
uint8_t
oldmcs1
[
8
];
/// mcs2 from last scheduling
uint8_t
oldmcs2
[
8
];
/// NDI from last UL scheduling
uint8_t
oldNDI_UL
[
8
];
/// mcs from last UL scheduling
uint8_t
mcs_UL
[
8
];
/// TBS from last UL scheduling
uint8_t
TBS_UL
[
8
];
/// CQI_req from last scheduling
uint8_t
oldCQI_UL
[
8
];
/// TPC from last scheduling
uint8_t
oldTPC_UL
[
8
];
/// Flag to indicate UL has been scheduled at least once
boolean_t
ul_active
;
/// Flag to indicate UE has been configured (ACK from RRCConnectionSetup received)
boolean_t
configured
;
/// MCS from last scheduling
uint8_t
mcs
[
8
];
/// TPC from last scheduling
uint8_t
oldTPC
[
8
];
// PHY interface info
/// Number of Allocated RBs for DL after scheduling (prior to frequency allocation)
uint16_t
nb_rb
[
8
];
// num_max_harq
/// Number of Allocated RBs for UL after scheduling
uint16_t
nb_rb_ul
[
8
];
// num_max_harq
/// Number of Allocated RBs for UL after scheduling
uint16_t
first_rb_ul
[
8
];
// num_max_harq
/// Is CQI requested for UL after scheduling 1st transmission
uint8_t
cqi_req
[
8
];
// num_max_harq
/// Cyclic shift for DMRS after scheduling
uint16_t
cshift
[
8
];
// num_max_harq
/// Number of Allocated RBs by the ulsch preprocessor
uint8_t
pre_allocated_nb_rb_ul
;
/// index of Allocated RBs by the ulsch preprocessor
int8_t
pre_allocated_rb_table_index_ul
;
/// total allocated RBs
int8_t
total_allocated_rbs
;
/// pre-assigned MCS by the ulsch preprocessor
uint8_t
pre_assigned_mcs_ul
;
/// assigned MCS by the ulsch scheduler
uint8_t
assigned_mcs_ul
;
/// DL DAI
uint8_t
DAI
;
/// UL DAI
uint8_t
DAI_ul
[
10
];
/// UL Scheduling Request Received
uint8_t
ul_SR
;
///Resource Block indication for each sub-band in MU-MIMO
uint8_t
rballoc_subband
[
8
][
50
];
// Logical channel info for link with RLC
/// Last received UE BSR info for each logical channel group id
uint8_t
bsr_info
[
MAX_NUM_LCGID
];
/// LCGID mapping
long
lcgidmap
[
11
];
/// phr information
int8_t
phr_info
;
/// phr information
int8_t
phr_info_configured
;
///dl buffer info
uint32_t
dl_buffer_info
[
MAX_NUM_LCID
];
/// total downlink buffer info
uint32_t
dl_buffer_total
;
/// total downlink pdus
uint32_t
dl_pdus_total
;
/// downlink pdus for each LCID
uint32_t
dl_pdus_in_buffer
[
MAX_NUM_LCID
];
/// creation time of the downlink buffer head for each LCID
uint32_t
dl_buffer_head_sdu_creation_time
[
MAX_NUM_LCID
];
/// maximum creation time of the downlink buffer head across all LCID
uint32_t
dl_buffer_head_sdu_creation_time_max
;
/// a flag indicating that the downlink head SDU is segmented
uint8_t
dl_buffer_head_sdu_is_segmented
[
MAX_NUM_LCID
];
/// size of remaining size to send for the downlink head SDU
uint32_t
dl_buffer_head_sdu_remaining_size_to_send
[
MAX_NUM_LCID
];
/// total uplink buffer size
uint32_t
ul_total_buffer
;
/// uplink buffer creation time for each LCID
uint32_t
ul_buffer_creation_time
[
MAX_NUM_LCGID
];
/// maximum uplink buffer creation time across all the LCIDs
uint32_t
ul_buffer_creation_time_max
;
/// uplink buffer size per LCID
uint32_t
ul_buffer_info
[
MAX_NUM_LCGID
];
/// UE tx power
int32_t
ue_tx_power
;
/// stores the frame where the last TPC was transmitted
uint32_t
pusch_tpc_tx_frame
;
uint32_t
pusch_tpc_tx_subframe
;
uint32_t
pucch_tpc_tx_frame
;
uint32_t
pucch_tpc_tx_subframe
;
/// stores the frame where the last bler was calculated
uint32_t
pusch_bler_calc_frame
;
uint32_t
pusch_bler_calc_subframe
;
#ifdef LOCALIZATION
eNB_UE_estimated_distances
distance
;
#endif
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
uint8_t
rach_resource_type
;
uint16_t
mpdcch_repetition_cnt
;
struct
PhysicalConfigDedicated
*
physicalConfigDedicated
;
frame_t
Msg2_frame
;
sub_frame_t
Msg2_subframe
;
#endif
}
UE_TEMPLATE
;
/*! \brief scheduling control information set through an API (not used)*/
typedef
struct
{
///UL transmission bandwidth in RBs
uint8_t
ul_bandwidth
[
MAX_NUM_LCID
];
///DL transmission bandwidth in RBs
uint8_t
dl_bandwidth
[
MAX_NUM_LCID
];
//To do GBR bearer
uint8_t
min_ul_bandwidth
[
MAX_NUM_LCID
];
uint8_t
min_dl_bandwidth
[
MAX_NUM_LCID
];
///aggregated bit rate of non-gbr bearer per UE
uint64_t
ue_AggregatedMaximumBitrateDL
;
///aggregated bit rate of non-gbr bearer per UE
uint64_t
ue_AggregatedMaximumBitrateUL
;
///CQI scheduling interval in subframes.
uint16_t
cqiSchedInterval
;
///Contention resolution timer used during random access
uint8_t
mac_ContentionResolutionTimer
;
uint16_t
max_allowed_rbs
[
MAX_NUM_LCID
];
uint8_t
max_mcs
[
MAX_NUM_LCID
];
uint16_t
priority
[
MAX_NUM_LCID
];
// resource scheduling information
/// Current DL harq round per harq_pid on each CC
uint8_t
round
[
MAX_NUM_CCs
][
10
];
/// Current Active TBs per harq_pid on each CC
uint8_t
tbcnt
[
MAX_NUM_CCs
][
10
];
/// Current UL harq round per harq_pid on each CC
uint8_t
round_UL
[
MAX_NUM_CCs
][
8
];
uint8_t
dl_pow_off
[
MAX_NUM_CCs
];
uint16_t
pre_nb_available_rbs
[
MAX_NUM_CCs
];
unsigned
char
rballoc_sub_UE
[
MAX_NUM_CCs
][
N_RBG_MAX
];
uint16_t
ta_timer
;
double
ta_update_f
;
int16_t
ta_update
;
uint16_t
ul_consecutive_errors
;
int32_t
context_active_timer
;
int32_t
cqi_req_timer
;
int32_t
ul_inactivity_timer
;
int32_t
ul_failure_timer
;
int32_t
ul_scheduled
;
int32_t
ra_pdcch_order_sent
;
int32_t
ul_out_of_sync
;
int32_t
phr_received
;
uint8_t
periodic_ri_received
[
NFAPI_CC_MAX
];
uint8_t
aperiodic_ri_received
[
NFAPI_CC_MAX
];
uint32_t
pucch_tpc_accumulated
[
NFAPI_CC_MAX
];
int16_t
pucch1_cqi_update
[
NFAPI_CC_MAX
];
int16_t
pucch1_snr
[
NFAPI_CC_MAX
];
int16_t
pucch2_cqi_update
[
NFAPI_CC_MAX
];
int16_t
pucch2_snr
[
NFAPI_CC_MAX
];
int16_t
pucch3_cqi_update
[
NFAPI_CC_MAX
];
int16_t
pucch3_snr
[
NFAPI_CC_MAX
];
double
pusch_cqi_f
[
NFAPI_CC_MAX
];
int16_t
pusch_cqi
[
NFAPI_CC_MAX
];
int16_t
pusch_snr
[
NFAPI_CC_MAX
];
int16_t
pusch_snr_avg
[
NFAPI_CC_MAX
];
uint64_t
pusch_rx_num
[
NFAPI_CC_MAX
];
uint64_t
pusch_rx_num_old
[
NFAPI_CC_MAX
];
uint64_t
pusch_rx_error_num
[
NFAPI_CC_MAX
];
uint64_t
pusch_rx_error_num_old
[
NFAPI_CC_MAX
];
double
pusch_bler
[
NFAPI_CC_MAX
];
uint8_t
mcs_offset
[
NFAPI_CC_MAX
];
uint16_t
feedback_cnt
[
NFAPI_CC_MAX
];
uint16_t
timing_advance
;
uint16_t
timing_advance_r9
;
uint8_t
periodic_wideband_cqi
[
NFAPI_CC_MAX
];
uint8_t
periodic_wideband_spatial_diffcqi
[
NFAPI_CC_MAX
];
uint8_t
periodic_wideband_pmi
[
NFAPI_CC_MAX
];
uint8_t
periodic_subband_cqi
[
NFAPI_CC_MAX
][
16
];
uint8_t
periodic_subband_spatial_diffcqi
[
NFAPI_CC_MAX
][
16
];
uint8_t
aperiodic_subband_cqi0
[
NFAPI_CC_MAX
][
25
];
uint8_t
aperiodic_subband_pmi
[
NFAPI_CC_MAX
][
25
];
uint8_t
aperiodic_subband_diffcqi0
[
NFAPI_CC_MAX
][
25
];
uint8_t
aperiodic_subband_cqi1
[
NFAPI_CC_MAX
][
25
];
uint8_t
aperiodic_subband_diffcqi1
[
NFAPI_CC_MAX
][
25
];
uint8_t
aperiodic_wideband_cqi0
[
NFAPI_CC_MAX
];
uint8_t
aperiodic_wideband_pmi
[
NFAPI_CC_MAX
];
uint8_t
aperiodic_wideband_cqi1
[
NFAPI_CC_MAX
];
uint8_t
aperiodic_wideband_pmi1
[
NFAPI_CC_MAX
];
uint8_t
dl_cqi
[
NFAPI_CC_MAX
];
}
UE_sched_ctrl
;
/*! \brief eNB template for the Random access information */
typedef
struct
{
/// Flag to indicate this process is active
boolean_t
RA_active
;
/// Size of DCI for RA-Response (bytes)
uint8_t
RA_dci_size_bytes1
;
/// Size of DCI for RA-Response (bits)
uint8_t
RA_dci_size_bits1
;
/// Actual DCI to transmit for RA-Response
uint8_t
RA_alloc_pdu1
[(
MAX_DCI_SIZE_BITS
>>
3
)
+
1
];
/// DCI format for RA-Response (should be 1A)
uint8_t
RA_dci_fmt1
;
/// Size of DCI for Msg4/ContRes (bytes)
uint8_t
RA_dci_size_bytes2
;
/// Size of DCI for Msg4/ContRes (bits)
uint8_t
RA_dci_size_bits2
;
/// Actual DCI to transmit for Msg4/ContRes
uint8_t
RA_alloc_pdu2
[(
MAX_DCI_SIZE_BITS
>>
3
)
+
1
];
/// DCI format for Msg4/ContRes (should be 1A)
uint8_t
RA_dci_fmt2
;
/// Flag to indicate the eNB should generate RAR. This is triggered by detection of PRACH
uint8_t
generate_rar
;
/// Subframe where preamble was received
uint8_t
preamble_subframe
;
/// Subframe where Msg2 is to be sent
uint8_t
Msg2_subframe
;
/// Frame where Msg2 is to be sent
frame_t
Msg2_frame
;
/// Subframe where Msg3 is to be sent
sub_frame_t
Msg3_subframe
;
/// Frame where Msg3 is to be sent
frame_t
Msg3_frame
;
/// Subframe where Msg4 is to be sent
sub_frame_t
Msg4_subframe
;
/// Frame where Msg4 is to be sent
frame_t
Msg4_frame
;
/// Flag to indicate the eNB should generate Msg4 upon reception of SDU from RRC. This is triggered by first ULSCH reception at eNB for new user.
uint8_t
generate_Msg4
;
/// Flag to indicate that eNB is waiting for ACK that UE has received Msg3.
uint8_t
wait_ack_Msg4
;
/// harq_pid used for Msg4 transmission
uint8_t
harq_pid
;
/// UE RNTI allocated during RAR
rnti_t
rnti
;
/// RA RNTI allocated from received PRACH
uint16_t
RA_rnti
;
/// Received preamble_index
uint8_t
preamble_index
;
/// Received UE Contention Resolution Identifier
uint8_t
cont_res_id
[
6
];
/// Timing offset indicated by PHY
int16_t
timing_offset
;
/// Timeout for RRC connection
int16_t
RRC_timer
;
/// Msg3 first RB
uint8_t
msg3_first_rb
;
/// Msg3 number of RB
uint8_t
msg3_nb_rb
;
/// Msg3 MCS
uint8_t
msg3_mcs
;
/// Msg3 TPC command
uint8_t
msg3_TPC
;
/// Msg3 ULdelay command
uint8_t
msg3_ULdelay
;
/// Msg3 cqireq command
uint8_t
msg3_cqireq
;
/// Round of Msg3 HARQ
uint8_t
msg3_round
;
/// TBS used for Msg4
int
msg4_TBsize
;
/// MCS used for Msg4
int
msg4_mcs
;
/// size off piggybacked RRC SDU
uint8_t
msg4_rrc_sdu_length
;
uint32_t
msg4_delay
;
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
uint8_t
rach_resource_type
;
uint8_t
msg2_mpdcch_repetition_cnt
;
uint8_t
msg2_mpdcch_done
;
uint8_t
msg4_mpdcch_repetition_cnt
;
uint8_t
msg4_mpdcch_done
;
uint8_t
msg2_narrowband
;
uint32_t
msg34_narrowband
;
#endif
}
RA_TEMPLATE
;
/*! \brief subband bitmap confguration (for ALU icic algo purpose), in test phase */
typedef
struct
{
uint8_t
sbmap
[
NUMBER_OF_SUBBANDS_MAX
];
//13 = number of SB MAX for 100 PRB
uint8_t
periodicity
;
uint8_t
first_subframe
;
uint8_t
sb_size
;
uint8_t
nb_active_sb
;
}
SBMAP_CONF
;
/*! \brief UE list used by eNB to order UEs/CC for scheduling*/
typedef
struct
{
/// Dedicated information for UEs
struct
PhysicalConfigDedicated
*
physicalConfigDedicated
[
MAX_NUM_CCs
][
NUMBER_OF_UE_MAX
];
/// DLSCH pdu
DLSCH_PDU
DLSCH_pdu
[
MAX_NUM_CCs
][
2
][
NUMBER_OF_UE_MAX
];
/// DCI template and MAC connection parameters for UEs
UE_TEMPLATE
UE_template
[
MAX_NUM_CCs
][
NUMBER_OF_UE_MAX
];
/// DCI template and MAC connection for RA processes
int
pCC_id
[
NUMBER_OF_UE_MAX
];
/// sorted downlink component carrier for the scheduler
int
ordered_CCids
[
MAX_NUM_CCs
][
NUMBER_OF_UE_MAX
];
/// number of downlink active component carrier
int
numactiveCCs
[
NUMBER_OF_UE_MAX
];
/// sorted uplink component carrier for the scheduler
int
ordered_ULCCids
[
MAX_NUM_CCs
][
NUMBER_OF_UE_MAX
];
/// number of uplink active component carrier
int
numactiveULCCs
[
NUMBER_OF_UE_MAX
];
/// number of downlink active component carrier
uint8_t
dl_CC_bitmap
[
NUMBER_OF_UE_MAX
];
/// eNB to UE statistics
eNB_UE_STATS
eNB_UE_stats
[
MAX_NUM_CCs
][
NUMBER_OF_UE_MAX
];
/// scheduling control info
UE_sched_ctrl
UE_sched_ctrl
[
NUMBER_OF_UE_MAX
];
int
next
[
NUMBER_OF_UE_MAX
];
int
head
;
int
next_ul
[
NUMBER_OF_UE_MAX
];
int
head_ul
;
int
avail
;
int
num_UEs
;
boolean_t
active
[
NUMBER_OF_UE_MAX
];
}
UE_list_t
;
/*! \brief eNB common channels */
typedef
struct
{
int
physCellId
;
int
p_eNB
;
int
Ncp
;
int
eutra_band
;
uint32_t
dl_CarrierFreq
;
BCCH_BCH_Message_t
*
mib
;
RadioResourceConfigCommonSIB_t
*
radioResourceConfigCommon
;
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
RadioResourceConfigCommonSIB_t
*
radioResourceConfigCommon_BR
;
#endif
TDD_Config_t
*
tdd_Config
;
SchedulingInfoList_t
*
schedulingInfoList
;
ARFCN_ValueEUTRA_t
ul_CarrierFreq
;
long
ul_Bandwidth
;
/// Outgoing MIB PDU for PHY
MIB_PDU
MIB_pdu
;
/// Outgoing BCCH pdu for PHY
BCCH_PDU
BCCH_pdu
;
/// Outgoing BCCH DCI allocation
uint32_t
BCCH_alloc_pdu
;
/// Outgoing CCCH pdu for PHY
CCCH_PDU
CCCH_pdu
;
/// Outgoing RAR pdu for PHY
RAR_PDU
RAR_pdu
;
/// Template for RA computations
RA_TEMPLATE
RA_template
[
NB_RA_PROC_MAX
];
/// VRB map for common channels
uint8_t
vrb_map
[
100
];
/// VRB map for common channels and retransmissions by PHICH
uint8_t
vrb_map_UL
[
100
];
/// MBSFN SubframeConfig
struct
MBSFN_SubframeConfig
*
mbsfn_SubframeConfig
[
8
];
/// number of subframe allocation pattern available for MBSFN sync area
uint8_t
num_sf_allocation_pattern
;
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
/// MBMS Flag
uint8_t
MBMS_flag
;
/// Outgoing MCCH pdu for PHY
MCCH_PDU
MCCH_pdu
;
/// MCCH active flag
uint8_t
msi_active
;
/// MCCH active flag
uint8_t
mcch_active
;
/// MTCH active flag
uint8_t
mtch_active
;
/// number of active MBSFN area
uint8_t
num_active_mbsfn_area
;
/// MBSFN Area Info
struct
MBSFN_AreaInfo_r9
*
mbsfn_AreaInfo
[
MAX_MBSFN_AREA
];
/// PMCH Config
struct
PMCH_Config_r9
*
pmch_Config
[
MAX_PMCH_perMBSFN
];
/// MBMS session info list
struct
MBMS_SessionInfoList_r9
*
mbms_SessionList
[
MAX_PMCH_perMBSFN
];
/// Outgoing MCH pdu for PHY
MCH_PDU
MCH_pdu
;
#endif
#if (LTE_RRC_VERSION >= MAKE_VERSION(14, 0, 0))
/// Rel13 parameters from SIB1
SystemInformationBlockType1_v1310_IEs_t
*
sib1_v13ext
;
/// Counter for SIB1-BR scheduling
int
SIB1_BR_cnt
;
/// Outgoing BCCH-BR pdu for PHY
BCCH_PDU
BCCH_BR_pdu
[
20
];
#endif
}
COMMON_channels_t
;
/*! \brief top level eNB MAC structure */
typedef
struct
eNB_MAC_INST_s
{
/// Ethernet parameters for northbound midhaul interface
eth_params_t
eth_params_n
;
/// Ethernet parameters for fronthaul interface
eth_params_t
eth_params_s
;
///
module_id_t
Mod_id
;
/// frame counter
frame_t
frame
;
/// subframe counter
sub_frame_t
subframe
;
/// Pointer to IF module instance for PHY
IF_Module_t
*
if_inst
;
/// Common cell resources
COMMON_channels_t
common_channels
[
MAX_NUM_CCs
];
/// current PDU index (BCH,MCH,DLSCH)
uint16_t
pdu_index
[
MAX_NUM_CCs
];
/// NFAPI Config Request Structure
nfapi_config_request_t
config
[
MAX_NUM_CCs
];
/// Preallocated DL pdu list
nfapi_dl_config_request_pdu_t
dl_config_pdu_list
[
MAX_NUM_CCs
][
MAX_NUM_DL_PDU
];
/// NFAPI DL Config Request Structure
nfapi_dl_config_request_t
DL_req
[
MAX_NUM_CCs
];
/// Preallocated UL pdu list
nfapi_ul_config_request_pdu_t
ul_config_pdu_list
[
MAX_NUM_CCs
][
MAX_NUM_UL_PDU
];
/// Preallocated UL pdu list for ULSCH (n+k delay)
nfapi_ul_config_request_pdu_t
ul_config_pdu_list_tmp
[
MAX_NUM_CCs
][
10
][
MAX_NUM_UL_PDU
];
/// NFAPI UL Config Request Structure, send to L1 4 subframes before processing takes place
nfapi_ul_config_request_t
UL_req
[
MAX_NUM_CCs
];
/// NFAPI "Temporary" UL Config Request Structure, holds future UL_config requests
nfapi_ul_config_request_t
UL_req_tmp
[
MAX_NUM_CCs
][
10
];
/// Preallocated HI_DCI0 pdu list
nfapi_hi_dci0_request_pdu_t
hi_dci0_pdu_list
[
MAX_NUM_CCs
][
MAX_NUM_HI_DCI0_PDU
];
/// NFAPI HI/DCI0 Config Request Structure
nfapi_hi_dci0_request_t
HI_DCI0_req
[
MAX_NUM_CCs
];
/// Prealocated TX pdu list
nfapi_tx_request_pdu_t
tx_request_pdu
[
MAX_NUM_CCs
][
MAX_NUM_TX_REQUEST_PDU
];
/// NFAPI DL PDU structure
nfapi_tx_request_t
TX_req
[
MAX_NUM_CCs
];
/// UL handle
uint32_t
ul_handle
;
UE_list_t
UE_list
;
///subband bitmap configuration
SBMAP_CONF
sbmap_conf
;
/// CCE table used to build DCI scheduling information
int
CCE_table
[
MAX_NUM_CCs
][
800
];
/// active flag for Other lcid
uint8_t
lcid_active
[
NB_RB_MAX
];
/// eNB stats
eNB_STATS
eNB_stats
[
MAX_NUM_CCs
];
// MAC function execution peformance profiler
/// processing time of eNB scheduler
time_stats_t
eNB_scheduler
;
/// processing time of eNB scheduler for SI
time_stats_t
schedule_si
;
/// processing time of eNB scheduler for Random access
time_stats_t
schedule_ra
;
/// processing time of eNB ULSCH scheduler
time_stats_t
schedule_ulsch
;
/// processing time of eNB DCI generation
time_stats_t
fill_DLSCH_dci
;
/// processing time of eNB MAC preprocessor
time_stats_t
schedule_dlsch_preprocessor
;
/// processing time of eNB DLSCH scheduler
time_stats_t
schedule_dlsch
;
// include rlc_data_req + MAC header + preprocessor
/// processing time of eNB MCH scheduler
time_stats_t
schedule_mch
;
/// processing time of eNB ULSCH reception
time_stats_t
rx_ulsch_sdu
;
// include rlc_data_ind
}
eNB_MAC_INST
;
/*
* UE part
*/
typedef
enum
{
TYPE0
,
TYPE1
,
TYPE1A
,
TYPE2
,
TYPE2A
,
TYPEUESPEC
}
MPDCCH_TYPES_t
;
/*!\brief UE layer 2 status */
typedef
enum
{
CONNECTION_OK
=
0
,
CONNECTION_LOST
,
PHY_RESYNCH
,
PHY_HO_PRACH
}
UE_L2_STATE_t
;
/*!\brief UE scheduling info */
typedef
struct
{
/// buffer status for each lcgid
uint8_t
BSR
[
MAX_NUM_LCGID
];
// should be more for mesh topology
/// keep the number of bytes in rlc buffer for each lcgid
int32_t
BSR_bytes
[
MAX_NUM_LCGID
];
/// after multiplexing buffer remain for each lcid
int32_t
LCID_buffer_remain
[
MAX_NUM_LCID
];
/// sum of all lcid buffer size
uint16_t
All_lcid_buffer_size_lastTTI
;
/// buffer status for each lcid
uint8_t
LCID_status
[
MAX_NUM_LCID
];
/// SR pending as defined in 36.321
uint8_t
SR_pending
;
/// SR_COUNTER as defined in 36.321
uint16_t
SR_COUNTER
;
/// logical channel group ide for each LCID
uint8_t
LCGID
[
MAX_NUM_LCID
];
/// retxBSR-Timer, default value is sf2560
uint16_t
retxBSR_Timer
;
/// retxBSR_SF, number of subframe before triggering a regular BSR
uint16_t
retxBSR_SF
;
/// periodicBSR-Timer, default to infinity
uint16_t
periodicBSR_Timer
;
/// periodicBSR_SF, number of subframe before triggering a periodic BSR
uint16_t
periodicBSR_SF
;
/// default value is 0: not configured
uint16_t
sr_ProhibitTimer
;
/// sr ProhibitTime running
uint8_t
sr_ProhibitTimer_Running
;
/// default value to n5
uint16_t
maxHARQ_Tx
;
/// default value is false
uint16_t
ttiBundling
;
/// default value is release
struct
DRX_Config
*
drx_config
;
/// default value is release
struct
MAC_MainConfig__phr_Config
*
phr_config
;
///timer before triggering a periodic PHR
uint16_t
periodicPHR_Timer
;
///timer before triggering a prohibit PHR
uint16_t
prohibitPHR_Timer
;
///DL Pathloss change value
uint16_t
PathlossChange
;
///number of subframe before triggering a periodic PHR
int16_t
periodicPHR_SF
;
///number of subframe before triggering a prohibit PHR
int16_t
prohibitPHR_SF
;
///DL Pathloss Change in db
uint16_t
PathlossChange_db
;
/// default value is false
uint16_t
extendedBSR_Sizes_r10
;
/// default value is false
uint16_t
extendedPHR_r10
;
//Bj bucket usage per lcid
int16_t
Bj
[
MAX_NUM_LCID
];
// Bucket size per lcid
int16_t
bucket_size
[
MAX_NUM_LCID
];
}
UE_SCHEDULING_INFO
;
/*!\brief Top level UE MAC structure */
typedef
struct
{
uint16_t
Node_id
;
/// RX frame counter
frame_t
rxFrame
;
/// RX subframe counter
sub_frame_t
rxSubframe
;
/// TX frame counter
frame_t
txFrame
;
/// TX subframe counter
sub_frame_t
txSubframe
;
/// C-RNTI of UE
uint16_t
crnti
;
/// C-RNTI of UE before HO
rnti_t
crnti_before_ho
;
///user id (rnti) of connected UEs
/// uplink active flag
uint8_t
ul_active
;
/// pointer to RRC PHY configuration
RadioResourceConfigCommonSIB_t
*
radioResourceConfigCommon
;
/// pointer to RACH_ConfigDedicated (NULL when not active, i.e. upon HO completion or T304 expiry)
struct
RACH_ConfigDedicated
*
rach_ConfigDedicated
;
/// pointer to RRC PHY configuration
struct
PhysicalConfigDedicated
*
physicalConfigDedicated
;
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
/// pointer to RRC PHY configuration SCEll
struct
PhysicalConfigDedicatedSCell_r10
*
physicalConfigDedicatedSCell_r10
;
#endif
/// pointer to TDD Configuration (NULL for FDD)
TDD_Config_t
*
tdd_Config
;
/// Number of adjacent cells to measure
uint8_t
n_adj_cells
;
/// Array of adjacent physical cell ids
uint32_t
adj_cell_id
[
6
];
/// Pointer to RRC MAC configuration
MAC_MainConfig_t
*
macConfig
;
/// Pointer to RRC Measurement gap configuration
MeasGapConfig_t
*
measGapConfig
;
/// Pointers to LogicalChannelConfig indexed by LogicalChannelIdentity. Note NULL means LCHAN is inactive.
LogicalChannelConfig_t
*
logicalChannelConfig
[
MAX_NUM_LCID
];
/// Scheduling Information
UE_SCHEDULING_INFO
scheduling_info
;
/// Outgoing CCCH pdu for PHY
CCCH_PDU
CCCH_pdu
;
/// Outgoing RAR pdu for PHY
RAR_PDU
RAR_pdu
;
/// Incoming DLSCH pdu for PHY
DLSCH_PDU
DLSCH_pdu
[
NUMBER_OF_UE_MAX
][
2
];
/// number of attempt for rach
uint8_t
RA_attempt_number
;
/// Random-access procedure flag
uint8_t
RA_active
;
/// Random-access window counter
int8_t
RA_window_cnt
;
/// Random-access Msg3 size in bytes
uint8_t
RA_Msg3_size
;
/// Random-access prachMaskIndex
uint8_t
RA_prachMaskIndex
;
/// Flag indicating Preamble set (A,B) used for first Msg3 transmission
uint8_t
RA_usedGroupA
;
/// Random-access Resources
PRACH_RESOURCES_t
RA_prach_resources
;
/// Random-access PREAMBLE_TRANSMISSION_COUNTER
uint8_t
RA_PREAMBLE_TRANSMISSION_COUNTER
;
/// Random-access backoff counter
int16_t
RA_backoff_cnt
;
/// Random-access variable for window calculation (frame of last change in window counter)
uint32_t
RA_tx_frame
;
/// Random-access variable for window calculation (subframe of last change in window counter)
uint8_t
RA_tx_subframe
;
/// Random-access Group B maximum path-loss
/// Random-access variable for backoff (frame of last change in backoff counter)
uint32_t
RA_backoff_frame
;
/// Random-access variable for backoff (subframe of last change in backoff counter)
uint8_t
RA_backoff_subframe
;
/// Random-access Group B maximum path-loss
uint16_t
RA_maxPL
;
/// Random-access Contention Resolution Timer active flag
uint8_t
RA_contention_resolution_timer_active
;
/// Random-access Contention Resolution Timer count value
uint8_t
RA_contention_resolution_cnt
;
/// power headroom reporitng reconfigured
uint8_t
PHR_reconfigured
;
/// power headroom state as configured by the higher layers
uint8_t
PHR_state
;
/// power backoff due to power management (as allowed by P-MPRc) for this cell
uint8_t
PHR_reporting_active
;
/// power backoff due to power management (as allowed by P-MPRc) for this cell
uint8_t
power_backoff_db
[
NUMBER_OF_eNB_MAX
];
/// BSR report falg management
uint8_t
BSR_reporting_active
;
/// retxBSR-Timer expires flag
uint8_t
retxBSRTimer_expires_flag
;
/// periodBSR-Timer expires flag
uint8_t
periodBSRTimer_expires_flag
;
/// MBSFN_Subframe Configuration
struct
MBSFN_SubframeConfig
*
mbsfn_SubframeConfig
[
8
];
// FIXME replace 8 by MAX_MBSFN_AREA?
/// number of subframe allocation pattern available for MBSFN sync area
uint8_t
num_sf_allocation_pattern
;
#if (LTE_RRC_VERSION >= MAKE_VERSION(10, 0, 0))
/// number of active MBSFN area
uint8_t
num_active_mbsfn_area
;
/// MBSFN Area Info
struct
MBSFN_AreaInfo_r9
*
mbsfn_AreaInfo
[
MAX_MBSFN_AREA
];
/// PMCH Config
struct
PMCH_Config_r9
*
pmch_Config
[
MAX_PMCH_perMBSFN
];
/// MCCH status
uint8_t
mcch_status
;
/// MSI status
uint8_t
msi_status
;
// could be an array if there are >1 MCH in one MBSFN area
#endif
//#ifdef CBA
/// CBA RNTI for each group
uint16_t
cba_rnti
[
NUM_MAX_CBA_GROUP
];
/// last SFN for CBA channel access
uint8_t
cba_last_access
[
NUM_MAX_CBA_GROUP
];
//#endif
/// total UE scheduler processing time
time_stats_t
ue_scheduler
;
// total
/// UE ULSCH tx processing time inlcuding RLC interface (rlc_data_req) and mac header generation
time_stats_t
tx_ulsch_sdu
;
/// UE DLSCH rx processing time inlcuding RLC interface (mac_rrc_data_ind or mac_rlc_status_ind+mac_rlc_data_ind) and mac header parser
time_stats_t
rx_dlsch_sdu
;
/// UE query for MCH subframe processing time
time_stats_t
ue_query_mch
;
/// UE MCH rx processing time
time_stats_t
rx_mch_sdu
;
/// UE BCCH rx processing time including RLC interface (mac_rrc_data_ind)
time_stats_t
rx_si
;
/// UE PCCH rx processing time including RLC interface (mac_rrc_data_ind)
time_stats_t
rx_p
;
}
UE_MAC_INST
;
/*! \brief ID of the neighboring cells used for HO*/
typedef
struct
{
uint16_t
cell_ids
[
6
];
uint8_t
n_adj_cells
;
}
neigh_cell_id_t
;
#include "proto.h"
/*@}*/
#endif
/*__LAYER2_MAC_DEFS_H__ */
This diff is collapsed.
Click to expand it.
openair2/LAYER2/MAC/eNB_scheduler_RA.c
View file @
b0f5a37f
...
@@ -212,13 +212,6 @@ add_msg3(module_id_t module_idP, int CC_id, RA_t *ra, frame_t frameP,
...
@@ -212,13 +212,6 @@ add_msg3(module_id_t module_idP, int CC_id, RA_t *ra, frame_t frameP,
hi_dci0_req
->
sfn_sf
=
sfnsf_add_subframe
(
frameP
,
subframeP
,
sf_ahead_dl
);
hi_dci0_req
->
sfn_sf
=
sfnsf_add_subframe
(
frameP
,
subframeP
,
sf_ahead_dl
);
hi_dci0_req
->
header
.
message_id
=
NFAPI_HI_DCI0_REQUEST
;
hi_dci0_req
->
header
.
message_id
=
NFAPI_HI_DCI0_REQUEST
;
//if (NFAPI_MODE != NFAPI_MONOLITHIC) {
// oai_nfapi_hi_dci0_req(hi_dci0_req);
// hi_dci0_req_body->number_of_hi=0;
//}
//LOG_D(MAC, "MSG3: HI_DCI0 SFN/SF:%d number_of_dci:%d number_of_hi:%d\n", NFAPI_SFNSF2DEC(hi_dci0_req->sfn_sf), hi_dci0_req_body->number_of_dci, hi_dci0_req_body->number_of_hi);
// save UL scheduling information for preprocessor
// save UL scheduling information for preprocessor
for
(
j
=
0
;
j
<
ra
->
msg3_nb_rb
;
j
++
)
for
(
j
=
0
;
j
<
ra
->
msg3_nb_rb
;
j
++
)
cc
->
vrb_map_UL
[
ra
->
msg3_first_rb
+
j
]
=
1
;
cc
->
vrb_map_UL
[
ra
->
msg3_first_rb
+
j
]
=
1
;
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/MAC/eNB_scheduler_ulsch.c
View file @
b0f5a37f
...
@@ -202,7 +202,7 @@ rx_sdu(const module_id_t enb_mod_idP,
...
@@ -202,7 +202,7 @@ rx_sdu(const module_id_t enb_mod_idP,
}
}
}
else
{
// sduP == NULL => error
}
else
{
// sduP == NULL => error
UE_scheduling_control
->
pusch_rx_error_num
[
CC_idP
]
++
;
UE_scheduling_control
->
pusch_rx_error_num
[
CC_idP
]
++
;
LOG_
D
(
MAC
,
"[eNB %d][PUSCH %d] CC_id %d %d.%d ULSCH in error in round %d, ul_cqi %d, UE_id %d, RNTI %x (len %d)
\n
"
,
LOG_
W
(
MAC
,
"[eNB %d][PUSCH %d] CC_id %d %d.%d ULSCH in error in round %d, ul_cqi %d, UE_id %d, RNTI %x (len %d)
\n
"
,
enb_mod_idP
,
enb_mod_idP
,
harq_pid
,
harq_pid
,
CC_idP
,
CC_idP
,
...
@@ -1656,11 +1656,9 @@ schedule_ulsch_rnti(module_id_t module_idP,
...
@@ -1656,11 +1656,9 @@ schedule_ulsch_rnti(module_id_t module_idP,
UE_template_ptr
->
cshift
[
harq_pid
]
=
cshift
;
UE_template_ptr
->
cshift
[
harq_pid
]
=
cshift
;
/* Setting DCI0 NFAPI struct */
/* Setting DCI0 NFAPI struct */
hi_dci0_pdu
=
&
hi_dci0_req_body
->
hi_dci0_pdu_list
[
dci_ul_pdu_idx
];
hi_dci0_pdu
=
&
hi_dci0_req_body
->
hi_dci0_pdu_list
[
dci_ul_pdu_idx
];
//memset((void *) hi_dci0_pdu, 0,sizeof(nfapi_hi_dci0_request_pdu_t));
hi_dci0_pdu
->
pdu_type
=
NFAPI_HI_DCI0_DCI_PDU_TYPE
;
hi_dci0_pdu
->
pdu_type
=
NFAPI_HI_DCI0_DCI_PDU_TYPE
;
hi_dci0_pdu
->
pdu_size
=
2
+
sizeof
(
nfapi_hi_dci0_dci_pdu
);
hi_dci0_pdu
->
pdu_size
=
2
+
sizeof
(
nfapi_hi_dci0_dci_pdu
);
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
dci_format
=
NFAPI_UL_DCI_FORMAT_0
;
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
dci_format
=
NFAPI_UL_DCI_FORMAT_0
;
//hi_dci0_pdu->dci_pdu.dci_pdu_rel8.aggregation_level = aggregation;
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
rnti
=
rnti
;
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
rnti
=
rnti
;
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
transmission_power
=
6000
;
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
transmission_power
=
6000
;
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
resource_block_start
=
UE_template_ptr
->
pre_first_nb_rb_ul
;
hi_dci0_pdu
->
dci_pdu
.
dci_pdu_rel8
.
resource_block_start
=
UE_template_ptr
->
pre_first_nb_rb_ul
;
...
...
This diff is collapsed.
Click to expand it.
openair2/RRC/LTE/rrc_eNB.c
View file @
b0f5a37f
...
@@ -6711,25 +6711,7 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
...
@@ -6711,25 +6711,7 @@ rrc_eNB_process_RRCConnectionReconfigurationComplete(
);
);
}
}
}
else
{
// remove LCHAN from MAC/PHY
}
else
{
// remove LCHAN from MAC/PHY
#if 0
if
(
DRB_configList
->
list
.
array
[
i
]
->
logicalChannelIdentity
)
{
if (ue_context_pP->ue_context.DRB_active[drb_id] == 1) {
// DRB has just been removed so remove RLC + PDCP for DRB
/* rrc_pdcp_config_req (ctxt_pP->module_id, frameP, 1, CONFIG_ACTION_REMOVE,
(ue_mod_idP * NB_RB_MAX) + DRB2LCHAN[i],UNDEF_SECURITY_MODE);
*/
if (!NODE_IS_CU(RC.rrc[ctxt_pP->module_id]->node_type)) {
rrc_rlc_config_req(ctxt_pP,
SRB_FLAG_NO,
MBMS_FLAG_NO,
CONFIG_ACTION_REMOVE,
DRB2LCHAN[i],
Rlc_info_um);
}
}
ue_context_pP->ue_context.DRB_active[drb_id] = 0;
#endif
if
(
DRB_configList
->
list
.
array
[
i
]
->
logicalChannelIdentity
)
{
DRB2LCHAN
[
i
]
=
(
uint8_t
)
*
DRB_configList
->
list
.
array
[
i
]
->
logicalChannelIdentity
;
DRB2LCHAN
[
i
]
=
(
uint8_t
)
*
DRB_configList
->
list
.
array
[
i
]
->
logicalChannelIdentity
;
}
}
...
...
This diff is collapsed.
Click to expand it.
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