Commit ed8915bc authored by Florian Kaltenberger's avatar Florian Kaltenberger

Merge remote-tracking branch 'origin/NR_DLUL_PF' into benetel_driver_update

parents a0e5be24 a0446132
...@@ -52,7 +52,7 @@ ...@@ -52,7 +52,7 @@
<testCase id="090102"> <testCase id="090102">
<class>Initialize_OAI_UE</class> <class>Initialize_OAI_UE</class>
<desc>Initialize NR UE USRP</desc> <desc>Initialize NR UE USRP</desc>
<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 75 --threadoffset 16 --rrc_config_path .</Initialize_OAI_UE_args> <Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 75 --rrc_config_path .</Initialize_OAI_UE_args>
<air_interface>NR</air_interface> <air_interface>NR</air_interface>
</testCase> </testCase>
......
...@@ -52,7 +52,7 @@ ...@@ -52,7 +52,7 @@
<testCase id="090104"> <testCase id="090104">
<class>Initialize_OAI_UE</class> <class>Initialize_OAI_UE</class>
<desc>Initialize NR UE USRP</desc> <desc>Initialize NR UE USRP</desc>
<Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 75 --threadoffset 16 --rrc_config_path .</Initialize_OAI_UE_args> <Initialize_OAI_UE_args>--phy-test --usrp-args "addr=192.168.30.2,second_addr=192.168.50.2,clock_source=external,time_source=external" --ue-rxgain 75 --rrc_config_path .</Initialize_OAI_UE_args>
<air_interface>NR</air_interface> <air_interface>NR</air_interface>
</testCase> </testCase>
......
...@@ -3232,6 +3232,7 @@ add_executable(nr_dlschsim ...@@ -3232,6 +3232,7 @@ add_executable(nr_dlschsim
${OPENAIR_DIR}/common/utils/system.c ${OPENAIR_DIR}/common/utils/system.c
${OPENAIR_DIR}/common/utils/nr/nr_common.c ${OPENAIR_DIR}/common/utils/nr/nr_common.c
${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/utils.c
${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c
${UTIL_SRC} ${UTIL_SRC}
${T_SOURCE} ${T_SOURCE}
${SHLIB_LOADER_SOURCES} ${SHLIB_LOADER_SOURCES}
...@@ -3246,6 +3247,7 @@ add_executable(nr_pbchsim ...@@ -3246,6 +3247,7 @@ add_executable(nr_pbchsim
${OPENAIR_DIR}/common/utils/system.c ${OPENAIR_DIR}/common/utils/system.c
${OPENAIR_DIR}/common/utils/nr/nr_common.c ${OPENAIR_DIR}/common/utils/nr/nr_common.c
${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/utils.c
${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c
${UTIL_SRC} ${UTIL_SRC}
${T_SOURCE} ${T_SOURCE}
${SHLIB_LOADER_SOURCES} ${SHLIB_LOADER_SOURCES}
...@@ -3262,6 +3264,7 @@ add_executable(nr_pucchsim ...@@ -3262,6 +3264,7 @@ add_executable(nr_pucchsim
${OPENAIR_DIR}/common/utils/nr/nr_common.c ${OPENAIR_DIR}/common/utils/nr/nr_common.c
${OPENAIR_DIR}/common/utils/system.c ${OPENAIR_DIR}/common/utils/system.c
${OPENAIR_DIR}/common/utils/utils.c ${OPENAIR_DIR}/common/utils/utils.c
${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c
${UTIL_SRC} ${UTIL_SRC}
${T_SOURCE} ${T_SOURCE}
${SHLIB_LOADER_SOURCES} ${SHLIB_LOADER_SOURCES}
...@@ -3280,6 +3283,7 @@ add_executable(nr_dlsim ...@@ -3280,6 +3283,7 @@ add_executable(nr_dlsim
${OPENAIR2_DIR}/RRC/NAS/nas_config.c ${OPENAIR2_DIR}/RRC/NAS/nas_config.c
${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c
${NFAPI_USER_DIR}/nfapi.c ${NFAPI_USER_DIR}/nfapi.c
${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c
${UTIL_SRC} ${UTIL_SRC}
${T_SOURCE} ${T_SOURCE}
${SHLIB_LOADER_SOURCES} ${SHLIB_LOADER_SOURCES}
...@@ -3299,6 +3303,7 @@ add_executable(nr_prachsim ...@@ -3299,6 +3303,7 @@ add_executable(nr_prachsim
${OPENAIR2_DIR}/RRC/NAS/nas_config.c ${OPENAIR2_DIR}/RRC/NAS/nas_config.c
${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c ${OPENAIR1_DIR}/SIMULATION/ETH_TRANSPORT/netlink_init.c
${NFAPI_USER_DIR}/nfapi.c ${NFAPI_USER_DIR}/nfapi.c
${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c
${UTIL_SRC} ${UTIL_SRC}
${T_SOURCE} ${T_SOURCE}
${SHLIB_LOADER_SOURCES}) ${SHLIB_LOADER_SOURCES})
......
...@@ -148,6 +148,7 @@ extern "C" { ...@@ -148,6 +148,7 @@ extern "C" {
#define DEBUG_SECURITY (1<<11) #define DEBUG_SECURITY (1<<11)
#define DEBUG_NAS (1<<12) #define DEBUG_NAS (1<<12)
#define DEBUG_RLC (1<<13) #define DEBUG_RLC (1<<13)
#define DEBUG_DLSCH_DECOD (1<<14)
#define UE_TIMING (1<<20) #define UE_TIMING (1<<20)
...@@ -166,6 +167,7 @@ extern "C" { ...@@ -166,6 +167,7 @@ extern "C" {
{"SECURITY", DEBUG_SECURITY},\ {"SECURITY", DEBUG_SECURITY},\
{"NAS", DEBUG_NAS},\ {"NAS", DEBUG_NAS},\
{"RLC", DEBUG_RLC},\ {"RLC", DEBUG_RLC},\
{"DLSCH_DECOD", DEBUG_DLSCH_DECOD},\
{"UE_TIMING", UE_TIMING},\ {"UE_TIMING", UE_TIMING},\
{NULL,-1}\ {NULL,-1}\
} }
......
...@@ -92,7 +92,7 @@ void *one_thread(void *arg) { ...@@ -92,7 +92,7 @@ void *one_thread(void *arg) {
} while (true); } while (true);
} }
void initTpool(char *params,tpool_t *pool, bool performanceMeas) { void initNamedTpool(char *params,tpool_t *pool, bool performanceMeas, char *name) {
memset(pool,0,sizeof(*pool)); memset(pool,0,sizeof(*pool));
char *measr=getenv("threadPoolMeasurements"); char *measr=getenv("threadPoolMeasurements");
pool->measurePerf=performanceMeas; pool->measurePerf=performanceMeas;
...@@ -116,6 +116,7 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) { ...@@ -116,6 +116,7 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) {
pool->restrictRNTI=false; pool->restrictRNTI=false;
curptr=strtok_r(parms_cpy,",",&saveptr); curptr=strtok_r(parms_cpy,",",&saveptr);
struct one_thread * ptr; struct one_thread * ptr;
char *tname = (name == NULL ? "Tpool" : name);
while ( curptr!=NULL ) { while ( curptr!=NULL ) {
int c=toupper(curptr[0]); int c=toupper(curptr[0]);
...@@ -138,7 +139,7 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) { ...@@ -138,7 +139,7 @@ void initTpool(char *params,tpool_t *pool, bool performanceMeas) {
pool->allthreads->pool=pool; pool->allthreads->pool=pool;
//Configure the thread scheduler policy for Linux //Configure the thread scheduler policy for Linux
// set the thread name for debugging // set the thread name for debugging
sprintf(pool->allthreads->name,"Tpool_%d",pool->allthreads->coreID); sprintf(pool->allthreads->name,"%s%d_%d",tname,pool->nbThreads,pool->allthreads->coreID);
threadCreate(&pool->allthreads->threadID, one_thread, (void *)pool->allthreads, threadCreate(&pool->allthreads->threadID, one_thread, (void *)pool->allthreads,
pool->allthreads->name, pool->allthreads->coreID, OAI_PRIORITY_RT); pool->allthreads->name, pool->allthreads->coreID, OAI_PRIORITY_RT);
pool->nbThreads++; pool->nbThreads++;
......
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
#define condwait(condition, mutex) AssertFatal(pthread_cond_wait(&condition, &mutex)==0,""); #define condwait(condition, mutex) AssertFatal(pthread_cond_wait(&condition, &mutex)==0,"");
#define condbroadcast(signal) AssertFatal(pthread_cond_broadcast(&signal)==0,""); #define condbroadcast(signal) AssertFatal(pthread_cond_broadcast(&signal)==0,"");
#define condsignal(signal) AssertFatal(pthread_cond_broadcast(&signal)==0,""); #define condsignal(signal) AssertFatal(pthread_cond_broadcast(&signal)==0,"");
#define tpool_nbthreads(tpool) (tpool.nbThreads)
typedef struct notifiedFIFO_elt_s { typedef struct notifiedFIFO_elt_s {
struct notifiedFIFO_elt_s *next; struct notifiedFIFO_elt_s *next;
uint64_t key; //To filter out elements uint64_t key; //To filter out elements
...@@ -294,6 +294,6 @@ static inline int abortTpool(tpool_t *t, uint64_t key) { ...@@ -294,6 +294,6 @@ static inline int abortTpool(tpool_t *t, uint64_t key) {
mutexunlock(nf->lockF); mutexunlock(nf->lockF);
return nbRemoved; return nbRemoved;
} }
void initTpool(char *params,tpool_t *pool, bool performanceMeas); void initNamedTpool(char *params,tpool_t *pool, bool performanceMeas, char *name);
#define initTpool(PARAMPTR,TPOOLPTR, MEASURFLAG) initNamedTpool(PARAMPTR,TPOOLPTR, MEASURFLAG, NULL)
#endif #endif
...@@ -112,13 +112,13 @@ No delete() call, same principle as not thread safe queues ...@@ -112,13 +112,13 @@ No delete() call, same principle as not thread safe queues
# Thread pools # Thread pools
## initialization ## initialization
The clients can create one or more thread pools with init_tpool() The clients can create one or more thread pools with `initTpool(char *params,tpool_t *pool, bool performanceMeas )` or `initNamedTpool(char *params,tpool_t *pool, bool performanceMeas , char *name)`
the params string structure: describes a list of cores, separated by "," that run a worker thread the params string structure: describes a list of cores, separated by "," that run a worker thread
If the core exists on the CPU, the thread pool initialization sets the affinity between this thread and the related code (use negative values is allowed, so the thread will never be mapped on a specific core). If the core exists on the CPU, the thread pool initialization sets the affinity between this thread and the related code (use negative values is allowed, so the thread will never be mapped on a specific core).
The threads are all Linux real time scheduler, their name is set automatically is "Tpool_<core id>" The threads are all Linux real time scheduler, their name is set automatically to `Tpool<thread index>_<core id>` if initTpool is used or to `<name><thread index>_<core id>` when initNamedTpool is used.
## adding jobs ## adding jobs
The client create their jobs messages as a notifiedFIFO_elt_t, then they push it with pushTpool() (that internally calls push_notifiedFIFO()) The client create their jobs messages as a notifiedFIFO_elt_t, then they push it with pushTpool() (that internally calls push_notifiedFIFO())
...@@ -132,11 +132,13 @@ A abort service abortTpool() allows to abort all jobs that match a key (see jobs ...@@ -132,11 +132,13 @@ A abort service abortTpool() allows to abort all jobs that match a key (see jobs
Nevertheless, jobs already performed before the return of abortTpool() are pushed in the response Fifo queue. Nevertheless, jobs already performed before the return of abortTpool() are pushed in the response Fifo queue.
## API details ## API details
Each thread pool (there can be several in the same process) should be initialized Each thread pool (there can be several in the same process) should be initialized once using one of the two API's:
### initTpool(char *params,tpool_t *pool, bool performanceMeas) is to be called oncepool ### initNamedTpool(char *params,tpool_t *pool, bool performanceMeas,char *name)
the configuration parameter is a string, elements separated by ",": ### initTpool(char *params,tpool_t *pool, bool performanceMeas)
`params`: the configuration parameter is a string, elements separator is a comma ",". An element can be:
* N: if a N is in the parameter list, no threads are created * N: if a N is in the parameter list, no threads are created
The purpose is to keep the same API in any case The purpose is to keep the same API in any case
...@@ -151,9 +153,11 @@ example: "-1,-1,-1" ...@@ -151,9 +153,11 @@ example: "-1,-1,-1"
as there is no core number -1, the thread pool is made of 3 floating threads as there is no core number -1, the thread pool is made of 3 floating threads
be careful with fix allocation: it is hard to be more clever than Linux kernel be careful with fix allocation: it is hard to be more clever than Linux kernel
pool is the memory you allocated before to store the thread pool internal state (same concept as above queues) `pool` is the memory you allocated before to store the thread pool internal state (same concept as above queues)
`performanceMeas` is a flag to enable measurements (well described in documentation)
performanceMeas is a flag to enable measurements (well described in documentation) `name` is used to build the thread names.
### pushTpool(tpool_t *t, notifiedFIFO_elt_t *msg) ### pushTpool(tpool_t *t, notifiedFIFO_elt_t *msg)
......
...@@ -295,6 +295,7 @@ The following features are valid for the gNB and the 5G-NR UE. ...@@ -295,6 +295,7 @@ The following features are valid for the gNB and the 5G-NR UE.
- NR RRC (38.331) Rel 15 messages using new asn1c - NR RRC (38.331) Rel 15 messages using new asn1c
- LTE RRC (36.331) also updated to Rel 15 - LTE RRC (36.331) also updated to Rel 15
- Generation of CellGroupConfig (for eNB) and MIB - Generation of CellGroupConfig (for eNB) and MIB
- Generation of system information block 1 (SIB1)
- Application to read configuration file and program gNB RRC - Application to read configuration file and program gNB RRC
- RRC can configure PDCP, RLC, MAC - RRC can configure PDCP, RLC, MAC
...@@ -305,7 +306,8 @@ The following features are valid for the gNB and the 5G-NR UE. ...@@ -305,7 +306,8 @@ The following features are valid for the gNB and the 5G-NR UE.
**gNB MAC** **gNB MAC**
- MAC -> PHY configuration using NR FAPI P5 interface - MAC -> PHY configuration using NR FAPI P5 interface
- MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU - MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU
- Scheduler for RA procedreat gNB - Scheduler procedures for SIB1
- Scheduler procedures for RA
- MAC downlink scheduler (fixed allocations) - MAC downlink scheduler (fixed allocations)
- MAC header generation (including timing advance) - MAC header generation (including timing advance)
- ACK / NACK handling and HARQ procedures for downlink - ACK / NACK handling and HARQ procedures for downlink
...@@ -350,11 +352,13 @@ The following features are valid for the gNB and the 5G-NR UE. ...@@ -350,11 +352,13 @@ The following features are valid for the gNB and the 5G-NR UE.
## UE Higher Layers ## ## UE Higher Layers ##
**gNB MAC** **UE MAC**
- Initial sync and MIB detection * Minimum system information (MSI)
- MAC -> PHY configuration of PHY via UE FAPI P5 interface - Initial sync and MIB detection
- Basic MAC to control PHY via UE FAPI P7 interface - System information block 1 (SIB1) reception
- Random access procedure * MAC -> PHY configuration of PHY via UE FAPI P5 interface
* Basic MAC to control PHY via UE FAPI P7 interface
* Random access procedure
**RLC** **RLC**
......
...@@ -132,6 +132,40 @@ With the RF simulator (on the same machine): ...@@ -132,6 +132,40 @@ With the RF simulator (on the same machine):
`sudo RFSIMULATOR=127.0.0.1 ./nr-uesoftmodem --do-ra --rfsim --parallel-config PARALLEL_SINGLE_THREAD` `sudo RFSIMULATOR=127.0.0.1 ./nr-uesoftmodem --do-ra --rfsim --parallel-config PARALLEL_SINGLE_THREAD`
## sa setup with OAI
The sa flag is used to run gNB in standalone mode. Currently OAI in NR standalone mode transmits and receives SIB1.
In order to run gNB in standalone mode, the following flag is needed at gNB:
`--sa`
### Run OAI in sa mode
At the gNB the --sa flag does the following
- it reads the RRC configuration from the configuration file
- it encodes the RRCConfiguration and the RBconfig message and stores them in the binary files rbconfig.raw and reconfig.raw
- the RRC encodes SIB1 according the configuration file and transmits it through PDSCH
At the UE the --sa flag will
- read the binary files rbconfig.raw and reconfig.raw from the current directory (a different directory can be specified with the flag --rrc_config_path) and process them.
From the `cmake_targets/ran_build/build` folder:
gNB on machine 1:
`sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf --sa`
UE on machine 2:
`sudo ./nr-uesoftmodem --rrc_config_path . --sa`
With the RF simulator (on the same machine):
`sudo ./nr-softmodem -O ../../../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.usrpb210.conf --rfsim --sa`
`sudo ./nr-uesoftmodem --rrc_config_path . --rfsim --sa`
## IF setup with OAI ## IF setup with OAI
The -C and -CO flags can be used together at UE side to set custom downlink and uplink FR1 intermediate frequencies for the IF equipment. The -C and -CO flags can be used together at UE side to set custom downlink and uplink FR1 intermediate frequencies for the IF equipment.
......
...@@ -186,7 +186,7 @@ development], for FR2 does not exist yet. ...@@ -186,7 +186,7 @@ development], for FR2 does not exist yet.
3) allocate a CCE for the UE (and return if it is not possible) 3) allocate a CCE for the UE (and return if it is not possible)
4) Calculate DMRS stuff (nr_save_pusch_fields()) and the TBS. 4) Calculate DMRS stuff (nr_save_pusch_fields()) and the TBS.
5) Mark used resources in vrb_map_UL. 5) Mark used resources in vrb_map_UL.
* loop through all users: get a free HARQ PID using select_ul_harq_pid() and * loop through all users: get a free HARQ PID and
update statistics. Fill nFAPI structures directly for PUSCH, and call update statistics. Fill nFAPI structures directly for PUSCH, and call
config_uldci() and fill_dci_pdu_rel15() for DCI filling and PDCCH messages. config_uldci() and fill_dci_pdu_rel15() for DCI filling and PDCCH messages.
......
...@@ -300,87 +300,11 @@ void exit_function(const char *file, const char *function, const int line, const ...@@ -300,87 +300,11 @@ void exit_function(const char *file, const char *function, const int line, const
} }
void *l2l1_task(void *arg) {
MessageDef *message_p = NULL;
int result;
itti_set_task_real_time(TASK_L2L1);
itti_mark_task_ready(TASK_L2L1);
/* Wait for the initialize message */
printf("Wait for the ITTI initialize message\n");
do {
if (message_p != NULL) {
result = itti_free (ITTI_MSG_ORIGIN_ID(message_p), message_p);
AssertFatal (result == EXIT_SUCCESS, "Failed to free memory (%d)!\n", result);
}
itti_receive_msg (TASK_L2L1, &message_p);
switch (ITTI_MSG_ID(message_p)) {
case INITIALIZE_MESSAGE:
/* Start gNB thread */
LOG_D(EMU, "L2L1 TASK received %s\n", ITTI_MSG_NAME(message_p));
start_gNB = 1;
break;
case TERMINATE_MESSAGE:
printf("received terminate message\n");
oai_exit=1;
start_gNB = 0;
itti_exit_task ();
break;
default:
LOG_E(EMU, "Received unexpected message %s\n", ITTI_MSG_NAME(message_p));
break;
}
} while (ITTI_MSG_ID(message_p) != INITIALIZE_MESSAGE);
result = itti_free (ITTI_MSG_ORIGIN_ID(message_p), message_p);
AssertFatal (result == EXIT_SUCCESS, "Failed to free memory (%d)!\n", result);
/* ???? no else but seems to be UE only ???
do {
// Wait for a message
itti_receive_msg (TASK_L2L1, &message_p);
switch (ITTI_MSG_ID(message_p)) {
case TERMINATE_MESSAGE:
oai_exit=1;
itti_exit_task ();
break;
case ACTIVATE_MESSAGE:
start_UE = 1;
break;
case DEACTIVATE_MESSAGE:
start_UE = 0;
break;
case MESSAGE_TEST:
LOG_I(EMU, "Received %s\n", ITTI_MSG_NAME(message_p));
break;
default:
LOG_E(EMU, "Received unexpected message %s\n", ITTI_MSG_NAME(message_p));
break;
}
result = itti_free (ITTI_MSG_ORIGIN_ID(message_p), message_p);
AssertFatal (result == EXIT_SUCCESS, "Failed to free memory (%d)!\n", result);
} while(!oai_exit);
*/
return NULL;
}
int create_gNB_tasks(uint32_t gnb_nb) { int create_gNB_tasks(uint32_t gnb_nb) {
LOG_D(GNB_APP, "%s(gnb_nb:%d)\n", __FUNCTION__, gnb_nb); LOG_D(GNB_APP, "%s(gnb_nb:%d)\n", __FUNCTION__, gnb_nb);
itti_wait_ready(1); itti_wait_ready(1);
if (itti_create_task (TASK_L2L1, l2l1_task, NULL) < 0) {
LOG_E(PDCP, "Create task for L2L1 failed\n");
return -1;
}
if (gnb_nb > 0) { if (gnb_nb > 0) {
/* Last task to create, others task must be ready before its start */ /* Last task to create, others task must be ready before its start */
...@@ -419,7 +343,7 @@ int create_gNB_tasks(uint32_t gnb_nb) { ...@@ -419,7 +343,7 @@ int create_gNB_tasks(uint32_t gnb_nb) {
} }
if (AMF_MODE_ENABLED && (get_softmodem_params()->phy_test==0 && get_softmodem_params()->do_ra==0)) { if (AMF_MODE_ENABLED && (get_softmodem_params()->phy_test==0 && get_softmodem_params()->do_ra==0 && get_softmodem_params()->sa==0)) {
if (gnb_nb > 0) { if (gnb_nb > 0) {
/* /*
if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) { if (itti_create_task (TASK_SCTP, sctp_eNB_task, NULL) < 0) {
...@@ -717,7 +641,6 @@ int stop_L1L2(module_id_t gnb_id) { ...@@ -717,7 +641,6 @@ int stop_L1L2(module_id_t gnb_id) {
/* these tasks need to pick up new configuration */ /* these tasks need to pick up new configuration */
terminate_task(TASK_RRC_ENB, gnb_id); terminate_task(TASK_RRC_ENB, gnb_id);
terminate_task(TASK_L2L1, gnb_id);
LOG_I(GNB_APP, "calling kill_gNB_proc() for instance %d\n", gnb_id); LOG_I(GNB_APP, "calling kill_gNB_proc() for instance %d\n", gnb_id);
kill_gNB_proc(gnb_id); kill_gNB_proc(gnb_id);
LOG_I(GNB_APP, "calling kill_NR_RU_proc() for instance %d\n", gnb_id); LOG_I(GNB_APP, "calling kill_NR_RU_proc() for instance %d\n", gnb_id);
...@@ -753,13 +676,6 @@ int restart_L1L2(module_id_t gnb_id) { ...@@ -753,13 +676,6 @@ int restart_L1L2(module_id_t gnb_id) {
rrc_enb_init(); rrc_enb_init();
itti_mark_task_ready(TASK_RRC_ENB); itti_mark_task_ready(TASK_RRC_ENB);
if (itti_create_task (TASK_L2L1, l2l1_task, NULL) < 0) {
LOG_E(PDCP, "Create task for L2L1 failed\n");
return -1;
} else {
LOG_I(PDCP, "Re-created task for L2L1 successfully\n");
}
/* pass a reconfiguration request which will configure everything down to /* pass a reconfiguration request which will configure everything down to
* RC.eNB[i][j]->frame_parms, too */ * RC.eNB[i][j]->frame_parms, too */
msg_p = itti_alloc_new_message(TASK_ENB_APP, RRC_CONFIGURATION_REQ); msg_p = itti_alloc_new_message(TASK_ENB_APP, RRC_CONFIGURATION_REQ);
...@@ -851,6 +767,9 @@ int main( int argc, char **argv ) ...@@ -851,6 +767,9 @@ int main( int argc, char **argv )
if (get_softmodem_params()->do_ra) if (get_softmodem_params()->do_ra)
AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n"); AssertFatal(get_softmodem_params()->phy_test == 0,"RA and phy_test are mutually exclusive\n");
if (get_softmodem_params()->sa)
AssertFatal(get_softmodem_params()->phy_test == 0,"Standalone mode and phy_test are mutually exclusive\n");
#if T_TRACER #if T_TRACER
T_Config_Init(); T_Config_Init();
#endif #endif
......
...@@ -411,7 +411,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) { ...@@ -411,7 +411,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL ); phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL );
#else #else
uint64_t a=rdtsc(); uint64_t a=rdtsc();
phy_procedures_nrUE_RX( UE, proc, 0, UE->mode); phy_procedures_nrUE_RX( UE, proc, 0, UE->mode,get_nrUE_params()->nr_dlsch_parallel);
LOG_D(PHY,"phy_procedures_nrUE_RX: slot:%d, time %lu\n", proc->nr_slot_rx, (rdtsc()-a)/3500); LOG_D(PHY,"phy_procedures_nrUE_RX: slot:%d, time %lu\n", proc->nr_slot_rx, (rdtsc()-a)/3500);
//printf(">>> nr_ue_pdcch_procedures ended\n"); //printf(">>> nr_ue_pdcch_procedures ended\n");
#endif #endif
...@@ -603,7 +603,7 @@ void *UE_thread(void *arg) { ...@@ -603,7 +603,7 @@ void *UE_thread(void *arg) {
while (!oai_exit) { while (!oai_exit) {
if (syncRunning) { if (syncRunning) {
notifiedFIFO_elt_t *res=tryPullTpool(&nf, Tpool); notifiedFIFO_elt_t *res=tryPullTpool(&nf,&(get_nrUE_params()->Tpool));
if (res) { if (res) {
syncRunning=false; syncRunning=false;
...@@ -629,7 +629,7 @@ void *UE_thread(void *arg) { ...@@ -629,7 +629,7 @@ void *UE_thread(void *arg) {
syncData_t *syncMsg=(syncData_t *)NotifiedFifoData(Msg); syncData_t *syncMsg=(syncData_t *)NotifiedFifoData(Msg);
syncMsg->UE=UE; syncMsg->UE=UE;
memset(&syncMsg->proc, 0, sizeof(syncMsg->proc)); memset(&syncMsg->proc, 0, sizeof(syncMsg->proc));
pushTpool(Tpool, Msg); pushTpool(&(get_nrUE_params()->Tpool), Msg);
trashed_frames=0; trashed_frames=0;
syncRunning=true; syncRunning=true;
continue; continue;
...@@ -739,20 +739,19 @@ void *UE_thread(void *arg) { ...@@ -739,20 +739,19 @@ void *UE_thread(void *arg) {
notifiedFIFO_elt_t *res; notifiedFIFO_elt_t *res;
while (nbSlotProcessing >= RX_NB_TH) { while (nbSlotProcessing >= RX_NB_TH) {
res=pullTpool(&nf, Tpool); res=pullTpool(&nf, &(get_nrUE_params()->Tpool));
nbSlotProcessing--; nbSlotProcessing--;
processingData_t *tmp=(processingData_t *)res->msgData; processingData_t *tmp=(processingData_t *)res->msgData;
if (tmp->proc.decoded_frame_rx != -1) if (tmp->proc.decoded_frame_rx != -1)
decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx); decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx);
//decoded_frame_rx=tmp->proc.decoded_frame_rx; else
decoded_frame_rx=-1;
pushNotifiedFIFO_nothreadSafe(&freeBlocks,res); pushNotifiedFIFO_nothreadSafe(&freeBlocks,res);
} }
if ( (decoded_frame_rx != curMsg->proc.frame_rx) && if ( decoded_frame_rx>0 && decoded_frame_rx != curMsg->proc.frame_rx)
(((decoded_frame_rx+1) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx) &&
(((decoded_frame_rx+2) % MAX_FRAME_NUMBER) != curMsg->proc.frame_rx))
LOG_E(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n", LOG_E(PHY,"Decoded frame index (%d) is not compatible with current context (%d), UE should go back to synch mode\n",
decoded_frame_rx, curMsg->proc.frame_rx ); decoded_frame_rx, curMsg->proc.frame_rx );
...@@ -779,18 +778,20 @@ void *UE_thread(void *arg) { ...@@ -779,18 +778,20 @@ void *UE_thread(void *arg) {
nbSlotProcessing++; nbSlotProcessing++;
msgToPush->key=slot_nr; msgToPush->key=slot_nr;
pushTpool(Tpool, msgToPush); pushTpool(&(get_nrUE_params()->Tpool), msgToPush);
if (IS_SOFTMODEM_RFSIM || IS_SOFTMODEM_NOS1) { //getenv("RFSIMULATOR") if ( IS_SOFTMODEM_RFSIM || IS_SOFTMODEM_NOS1) { //getenv("RFSIMULATOR")
// FixMe: Wait previous thread is done, because race conditions seems too bad // FixMe: Wait previous thread is done, because race conditions seems too bad
// in case of actual RF board, the overlap between threads mitigate the issue // in case of actual RF board, the overlap between threads mitigate the issue
// We must receive one message, that proves the slot processing is done // We must receive one message, that proves the slot processing is done
res=pullTpool(&nf, Tpool); res=pullTpool(&nf, &(get_nrUE_params()->Tpool));
nbSlotProcessing--; nbSlotProcessing--;
processingData_t *tmp=(processingData_t *)res->msgData; processingData_t *tmp=(processingData_t *)res->msgData;
if (tmp->proc.decoded_frame_rx != -1) if (tmp->proc.decoded_frame_rx != -1)
decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx); decoded_frame_rx=(((mac->mib->systemFrameNumber.buf[0] >> mac->mib->systemFrameNumber.bits_unused)<<4) | tmp->proc.decoded_frame_rx);
else
decoded_frame_rx=-1;
//decoded_frame_rx=tmp->proc.decoded_frame_rx; //decoded_frame_rx=tmp->proc.decoded_frame_rx;
pushNotifiedFIFO_nothreadSafe(&freeBlocks,res); pushNotifiedFIFO_nothreadSafe(&freeBlocks,res);
...@@ -841,11 +842,11 @@ void init_NR_UE_threads(int nb_inst) { ...@@ -841,11 +842,11 @@ void init_NR_UE_threads(int nb_inst) {
LOG_I(PHY,"Intializing UE Threads for instance %d (%p,%p)...\n",inst,PHY_vars_UE_g[inst],PHY_vars_UE_g[inst][0]); LOG_I(PHY,"Intializing UE Threads for instance %d (%p,%p)...\n",inst,PHY_vars_UE_g[inst],PHY_vars_UE_g[inst][0]);
threadCreate(&threads[inst], UE_thread, (void *)UE, "UEthread", -1, OAI_PRIORITY_RT_MAX); threadCreate(&threads[inst], UE_thread, (void *)UE, "UEthread", -1, OAI_PRIORITY_RT_MAX);
#ifdef UE_DLSCH_PARALLELISATION if(get_nrUE_params()->nr_dlsch_parallel)
{
pthread_t dlsch0_threads; pthread_t dlsch0_threads;
threadCreate(&dlsch0_threads, dlsch_thread, (void *)UE, "DLthread", -1, OAI_PRIORITY_RT_MAX-1); threadCreate(&dlsch0_threads, dlsch_thread, (void *)UE, "DLthread", -1, OAI_PRIORITY_RT_MAX-1);
#endif }
} }
} }
......
This diff is collapsed.
This diff is collapsed.
...@@ -56,6 +56,7 @@ extern "C" ...@@ -56,6 +56,7 @@ extern "C"
#define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n" #define CONFIG_HLP_UELOOP "get softmodem (UE) to loop through memory instead of acquiring from HW\n"
#define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n" #define CONFIG_HLP_PHYTST "test UE phy layer, mac disabled\n"
#define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n" #define CONFIG_HLP_DORA "test gNB and UE with RA procedures\n"
#define CONFIG_HLP_SA "run gNB in standalone mode\n"
#define CONFIG_HLP_EXTS "tells hardware to use an external timing reference\n" #define CONFIG_HLP_EXTS "tells hardware to use an external timing reference\n"
#define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0" #define CONFIG_HLP_DMRSSYNC "tells RU to insert DMRS in subframe 1 slot 0"
#define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n" #define CONFIG_HLP_CLK "tells hardware to use a clock reference (0:internal, 1:external, 2:gpsdo)\n"
...@@ -100,6 +101,7 @@ extern "C" ...@@ -100,6 +101,7 @@ extern "C"
#define TP_CONFIG softmodem_params.threadPoolConfig #define TP_CONFIG softmodem_params.threadPoolConfig
#define PHY_TEST softmodem_params.phy_test #define PHY_TEST softmodem_params.phy_test
#define DO_RA softmodem_params.do_ra #define DO_RA softmodem_params.do_ra
#define SA softmodem_params.sa
#define WAIT_FOR_SYNC softmodem_params.wait_for_sync #define WAIT_FOR_SYNC softmodem_params.wait_for_sync
#define SINGLE_THREAD_FLAG softmodem_params.single_thread_flag #define SINGLE_THREAD_FLAG softmodem_params.single_thread_flag
#define CHAIN_OFFSET softmodem_params.chain_offset #define CHAIN_OFFSET softmodem_params.chain_offset
...@@ -119,6 +121,7 @@ extern "C" ...@@ -119,6 +121,7 @@ extern "C"
{"thread-pool", CONFIG_HLP_TPOOL, 0, strptr:(char **)&TP_CONFIG, defstrval:"n", TYPE_STRING, sizeof(TP_CONFIG)}, \ {"thread-pool", CONFIG_HLP_TPOOL, 0, strptr:(char **)&TP_CONFIG, defstrval:"n", TYPE_STRING, sizeof(TP_CONFIG)}, \
{"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, iptr:&PHY_TEST, defintval:0, TYPE_INT, 0}, \ {"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, iptr:&PHY_TEST, defintval:0, TYPE_INT, 0}, \
{"do-ra", CONFIG_HLP_DORA, PARAMFLAG_BOOL, iptr:&DO_RA, defintval:0, TYPE_INT, 0}, \ {"do-ra", CONFIG_HLP_DORA, PARAMFLAG_BOOL, iptr:&DO_RA, defintval:0, TYPE_INT, 0}, \
{"sa", CONFIG_HLP_SA, PARAMFLAG_BOOL, iptr:&SA, defintval:0, TYPE_INT, 0}, \
{"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \ {"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \
{"clock-source", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \ {"clock-source", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \
{"time-source", CONFIG_HLP_TME, 0, uptr:&TIMING_SOURCE, defintval:0, TYPE_UINT, 0}, \ {"time-source", CONFIG_HLP_TME, 0, uptr:&TIMING_SOURCE, defintval:0, TYPE_UINT, 0}, \
...@@ -213,6 +216,7 @@ typedef struct { ...@@ -213,6 +216,7 @@ typedef struct {
char threadPoolConfig[1024]; char threadPoolConfig[1024];
int phy_test; int phy_test;
int do_ra; int do_ra;
int sa;
uint8_t usim_test; uint8_t usim_test;
int emulate_rf; int emulate_rf;
int wait_for_sync; //eNodeB only int wait_for_sync; //eNodeB only
......
...@@ -44,7 +44,7 @@ ...@@ -44,7 +44,7 @@
#define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01 #define FAPI_NR_DL_CONFIG_TYPE_DCI 0x01
#define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02 #define FAPI_NR_DL_CONFIG_TYPE_DLSCH 0x02
#define FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH 0x03 #define FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH 0x03
#define FAPI_NR_DL_CONFIG_TYPE_SI_DLSCH 0x04
#define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01 #define FAPI_NR_CCE_REG_MAPPING_TYPE_INTERLEAVED 0x01
#define FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02 #define FAPI_NR_CCE_REG_MAPPING_TYPE_NON_INTERLEAVED 0x02
......
...@@ -630,30 +630,30 @@ typedef struct { ...@@ -630,30 +630,30 @@ typedef struct {
typedef struct { typedef struct {
// The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535. // The RNTI used for identifying the UE when receiving the PDU Value: 1 -> 65535.
uint16_t RNTI[MAX_DCI_CORESET]; uint16_t RNTI;
// For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured, // For a UE-specific search space it equals the higher-layer parameter PDCCH-DMRSScrambling-ID if configured,
// otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535 // otherwise it should be set to the phy cell ID. [TS38.211, sec 7.3.2.3] Value: 0->65535
uint16_t ScramblingId[MAX_DCI_CORESET]; uint16_t ScramblingId;
// For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI. // For a UE-specific search space where PDCCH-DMRSScrambling- ID is configured This param equals the CRNTI.
// Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535 // Otherwise, it should be set to 0. [TS38.211, sec 7.3.2.3] Value: 0 -> 65535
uint16_t ScramblingRNTI[MAX_DCI_CORESET]; uint16_t ScramblingRNTI;
// CCE start Index used to send the DCI Value: 0->135 // CCE start Index used to send the DCI Value: 0->135
uint8_t CceIndex[MAX_DCI_CORESET]; uint8_t CceIndex;
// Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16 // Aggregation level used [TS38.211, sec 7.3.2.1] Value: 1,2,4,8,16
uint8_t AggregationLevel[MAX_DCI_CORESET]; uint8_t AggregationLevel;
// Precoding and Beamforming structure See Table 3-43 // Precoding and Beamforming structure See Table 3-43
nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming[MAX_DCI_CORESET]; nfapi_nr_tx_precoding_and_beamforming_t precodingAndBeamforming;
// PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI. // PDCCH power value used for PDCCH Format 1_0 with CRC scrambled by SI-RNTI, PI-RNTI or RA-RNTI.
// This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1] // This is ratio of SSB/PBCH EPRE to PDCCH and PDCCH DMRS EPRE [TS38.213, sec 4.1]
// Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps // Value :0->17 Report title: 5G FAPI: PHY API Specification Issue date: 29 June 2019 Version: 222.10.17 68 Field Type Description representing -8 to 8 dB in 1dB steps
uint8_t beta_PDCCH_1_0[MAX_DCI_CORESET]; uint8_t beta_PDCCH_1_0;
// PDCCH power value used for all other PDCCH Formats. // PDCCH power value used for all other PDCCH Formats.
// This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB // This is ratio of SSB/PBCH block EPRE to PDCCH and PDCCH DMRS EPRE [TS38.214, sec 4.1] Values: 0: -3dB,1: 0dB,2: 3dB,3: 6dB
uint8_t powerControlOffsetSS[MAX_DCI_CORESET]; uint8_t powerControlOffsetSS;
// The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BYTE_LEN*8 // The total DCI length (in bits) including padding bits [TS38.212 sec 7.3.1] Range 0->DCI_PAYLOAD_BYTE_LEN*8
uint16_t PayloadSizeBits[MAX_DCI_CORESET]; uint16_t PayloadSizeBits;
// DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB // DCI payload, where the actual size is defined by PayloadSizeBits. The bit order is as following bit0-bit7 are mapped to first byte of MSB - LSB
uint8_t Payload[MAX_DCI_CORESET][DCI_PAYLOAD_BYTE_LEN]; uint8_t Payload[DCI_PAYLOAD_BYTE_LEN];
} nfapi_nr_dl_dci_pdu_t; } nfapi_nr_dl_dci_pdu_t;
...@@ -698,7 +698,7 @@ typedef struct { ...@@ -698,7 +698,7 @@ typedef struct {
///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot ///Number of DCIs in this CORESET.Value: 0->MaxDciPerSlot
uint16_t numDlDci; uint16_t numDlDci;
///DL DCI PDU ///DL DCI PDU
nfapi_nr_dl_dci_pdu_t dci_pdu; nfapi_nr_dl_dci_pdu_t dci_pdu[MAX_DCI_CORESET];
} nfapi_nr_dl_tti_pdcch_pdu_rel15_t; } nfapi_nr_dl_tti_pdcch_pdu_rel15_t;
typedef struct { typedef struct {
......
...@@ -134,6 +134,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, ...@@ -134,6 +134,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
nr_generate_modulation_table(); nr_generate_modulation_table();
nr_init_pdcch_dmrs(gNB, cfg->cell_config.phy_cell_id.value); nr_init_pdcch_dmrs(gNB, cfg->cell_config.phy_cell_id.value);
nr_init_pbch_interleaver(gNB->nr_pbch_interleaver); nr_init_pbch_interleaver(gNB->nr_pbch_interleaver);
//PDSCH DMRS init //PDSCH DMRS init
gNB->nr_gold_pdsch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***)); gNB->nr_gold_pdsch_dmrs = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***));
uint32_t ****pdsch_dmrs = gNB->nr_gold_pdsch_dmrs; uint32_t ****pdsch_dmrs = gNB->nr_gold_pdsch_dmrs;
...@@ -257,9 +258,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, ...@@ -257,9 +258,7 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value; int N_RB_UL = cfg->carrier_config.ul_grid_size[cfg->ssb_config.scs_common.value].value;
printf("Before ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]);
for (int ULSCH_id=0; ULSCH_id<NUMBER_OF_NR_ULSCH_MAX; ULSCH_id++) { for (int ULSCH_id=0; ULSCH_id<NUMBER_OF_NR_ULSCH_MAX; ULSCH_id++) {
printf("ULSCH_id %d : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
pusch_vars[ULSCH_id] = (NR_gNB_PUSCH *)malloc16_clear( sizeof(NR_gNB_PUSCH) ); pusch_vars[ULSCH_id] = (NR_gNB_PUSCH *)malloc16_clear( sizeof(NR_gNB_PUSCH) );
pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); pusch_vars[ULSCH_id]->rxdataF_ext = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); pusch_vars[ULSCH_id]->rxdataF_ext2 = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
...@@ -276,7 +275,6 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, ...@@ -276,7 +275,6 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16(Prx*sizeof(int32_t *) ); pusch_vars[ULSCH_id]->ul_ch_magb = (int32_t **)malloc16(Prx*sizeof(int32_t *) );
pusch_vars[ULSCH_id]->rho = (int32_t **)malloc16_clear(Prx*sizeof(int32_t*) ); pusch_vars[ULSCH_id]->rho = (int32_t **)malloc16_clear(Prx*sizeof(int32_t*) );
printf("ULSCH_id %d (before rx antenna alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
for (i=0; i<Prx; i++) { for (i=0; i<Prx; i++) {
pusch_vars[ULSCH_id]->rxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot ); pusch_vars[ULSCH_id]->rxdataF_ext[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
pusch_vars[ULSCH_id]->rxdataF_ext2[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot ); pusch_vars[ULSCH_id]->rxdataF_ext2[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*N_RB_UL*12*fp->symbols_per_slot );
...@@ -293,16 +291,13 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, ...@@ -293,16 +291,13 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
pusch_vars[ULSCH_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 ); pusch_vars[ULSCH_id]->ul_ch_magb[i] = (int32_t *)malloc16_clear( fp->symbols_per_slot*sizeof(int32_t)*N_RB_UL*12 );
pusch_vars[ULSCH_id]->rho[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*(fp->N_RB_UL*12*7*2) ); pusch_vars[ULSCH_id]->rho[i] = (int32_t *)malloc16_clear( sizeof(int32_t)*(fp->N_RB_UL*12*7*2) );
} }
printf("ULSCH_id %d (before llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
pusch_vars[ULSCH_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear pusch_vars[ULSCH_id]->llr = (int16_t *)malloc16_clear( (8*((3*8*6144)+12))*sizeof(int16_t) ); // [hna] 6144 is LTE and (8*((3*8*6144)+12)) is not clear
printf("ULSCH_id %d (after llr alloc) : %p\n",ULSCH_id,gNB->dlsch[0][0]->harq_processes[0]);
pusch_vars[ULSCH_id]->ul_valid_re_per_slot = (int16_t *)malloc16_clear( sizeof(int16_t)*fp->symbols_per_slot); pusch_vars[ULSCH_id]->ul_valid_re_per_slot = (int16_t *)malloc16_clear( sizeof(int16_t)*fp->symbols_per_slot);
} //ulsch_id } //ulsch_id
/* /*
for (ulsch_id=0; ulsch_id<NUMBER_OF_UE_MAX; ulsch_id++) for (ulsch_id=0; ulsch_id<NUMBER_OF_UE_MAX; ulsch_id++)
gNB->UE_stats_ptr[ulsch_id] = &gNB->UE_stats[ulsch_id]; gNB->UE_stats_ptr[ulsch_id] = &gNB->UE_stats[ulsch_id];
*/ */
printf("After ULSCH init : %p\n",gNB->dlsch[0][0]->harq_processes[0]);
return (0); return (0);
} }
......
...@@ -586,6 +586,40 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue, ...@@ -586,6 +586,40 @@ int init_nr_ue_signal(PHY_VARS_NR_UE *ue,
} }
} }
//PDCCH DMRS init (eNB offset = 0)
ue->nr_gold_pdcch[0] = (uint32_t ***)malloc16(fp->slots_per_frame*sizeof(uint32_t **));
uint32_t ***pdcch_dmrs = ue->nr_gold_pdcch[0];
AssertFatal(pdcch_dmrs!=NULL, "NR init: pdcch_dmrs malloc failed\n");
for (int slot=0; slot<fp->slots_per_frame; slot++) {
pdcch_dmrs[slot] = (uint32_t **)malloc16(fp->symbols_per_slot*sizeof(uint32_t *));
AssertFatal(pdcch_dmrs[slot]!=NULL, "NR init: pdcch_dmrs for slot %d - malloc failed\n", slot);
for (int symb=0; symb<fp->symbols_per_slot; symb++) {
pdcch_dmrs[slot][symb] = (uint32_t *)malloc16(NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t));
AssertFatal(pdcch_dmrs[slot][symb]!=NULL, "NR init: pdcch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb);
}
}
//PDSCH DMRS init (eNB offset = 0)
ue->nr_gold_pdsch[0] = (uint32_t ****)malloc16(fp->slots_per_frame*sizeof(uint32_t ***));
uint32_t ****pdsch_dmrs = ue->nr_gold_pdsch[0];
for (int slot=0; slot<fp->slots_per_frame; slot++) {
pdsch_dmrs[slot] = (uint32_t ***)malloc16(fp->symbols_per_slot*sizeof(uint32_t **));
AssertFatal(pdsch_dmrs[slot]!=NULL, "NR init: pdsch_dmrs for slot %d - malloc failed\n", slot);
for (int symb=0; symb<fp->symbols_per_slot; symb++) {
pdsch_dmrs[slot][symb] = (uint32_t **)malloc16(NR_MAX_NB_CODEWORDS*sizeof(uint32_t *));
AssertFatal(pdsch_dmrs[slot][symb]!=NULL, "NR init: pdsch_dmrs for slot %d symbol %d - malloc failed\n", slot, symb);
for (int q=0; q<NR_MAX_NB_CODEWORDS; q++) {
pdsch_dmrs[slot][symb][q] = (uint32_t *)malloc16(NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD*sizeof(uint32_t));
AssertFatal(pdsch_dmrs[slot][symb][q]!=NULL, "NR init: pdsch_dmrs for slot %d symbol %d codeword %d - malloc failed\n", slot, symb, q);
}
}
}
// DLSCH // DLSCH
for (eNB_id=0; eNB_id<ue->n_connected_eNB; eNB_id++) { for (eNB_id=0; eNB_id<ue->n_connected_eNB; eNB_id++) {
for (th_id=0; th_id<RX_NB_TH_MAX; th_id++) { for (th_id=0; th_id<RX_NB_TH_MAX; th_id++) {
......
...@@ -26,6 +26,7 @@ void nr_gold_pbch(PHY_VARS_NR_UE* ue) ...@@ -26,6 +26,7 @@ void nr_gold_pbch(PHY_VARS_NR_UE* ue)
unsigned int n, x1, x2; unsigned int n, x1, x2;
unsigned int Nid, i_ssb, i_ssb2; unsigned int Nid, i_ssb, i_ssb2;
unsigned char Lmax, l, n_hf, N_hf; unsigned char Lmax, l, n_hf, N_hf;
uint8_t reset;
Nid = ue->frame_parms.Nid_cell; Nid = ue->frame_parms.Nid_cell;
Lmax = ue->frame_parms.Lmax; Lmax = ue->frame_parms.Lmax;
...@@ -37,24 +38,12 @@ void nr_gold_pbch(PHY_VARS_NR_UE* ue) ...@@ -37,24 +38,12 @@ void nr_gold_pbch(PHY_VARS_NR_UE* ue)
i_ssb = l & (Lmax-1); i_ssb = l & (Lmax-1);
i_ssb2 = i_ssb + (n_hf<<2); i_ssb2 = i_ssb + (n_hf<<2);
x1 = 1 + (1<<31); reset = 1;
x2 = (1<<11) * (i_ssb2 + 1) * ((Nid>>2) + 1) + (1<<6) * (i_ssb2 + 1) + (Nid&3); x2 = (1<<11) * (i_ssb2 + 1) * ((Nid>>2) + 1) + (1<<6) * (i_ssb2 + 1) + (Nid&3);
x2 = x2 ^ ((x2 ^ (x2>>1) ^ (x2>>2) ^ (x2>>3))<<31);
// skip first 50 double words (1600 bits)
for (n = 1; n < 50; n++) {
x1 = (x1>>1) ^ (x1>>4);
x1 = x1 ^ (x1<<31) ^ (x1<<28);
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
}
for (n=0; n<NR_PBCH_DMRS_LENGTH_DWORD; n++) { for (n=0; n<NR_PBCH_DMRS_LENGTH_DWORD; n++) {
x1 = (x1>>1) ^ (x1>>4); ue->nr_gold_pbch[n_hf][l][n] = lte_gold_generic(&x1, &x2, reset);
x1 = x1 ^ (x1<<31) ^ (x1<<28); reset = 0;
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
ue->nr_gold_pbch[n_hf][l][n] = x1 ^ x2;
} }
} }
...@@ -69,38 +58,24 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue, ...@@ -69,38 +58,24 @@ void nr_gold_pdcch(PHY_VARS_NR_UE* ue,
unsigned char ns,l; unsigned char ns,l;
unsigned int n,x1,x2,x2tmp0; unsigned int n,x1,x2,x2tmp0;
unsigned int nid; unsigned int nid;
uint8_t reset;
if (n_idDMRS) if (n_idDMRS)
nid = n_idDMRS; nid = n_idDMRS;
else else
nid = ue->frame_parms.Nid_cell; nid = ue->frame_parms.Nid_cell;
for (ns=0; ns<20; ns++) { for (ns=0; ns<ue->frame_parms.slots_per_frame; ns++) {
for (l=0; l<length_dmrs; l++) { for (l=0; l<length_dmrs; l++) {
x2tmp0 = ((14*ns+l+1)*((nid<<1)+1))<<17; reset = 1;
x2tmp0 = ((ue->frame_parms.symbols_per_slot*ns+l+1)*((nid<<1)+1))<<17;
x2 = (x2tmp0+(nid<<1))%(1<<31); //cinit x2 = (x2tmp0+(nid<<1))%(1<<31); //cinit
x1 = 1+ (1<<31); for (n=0; n<NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD; n++) {
x2=x2 ^ ((x2 ^ (x2>>1) ^ (x2>>2) ^ (x2>>3))<<31); ue->nr_gold_pdcch[0][ns][l][n] = lte_gold_generic(&x1, &x2, reset);
reset = 0;
// skip first 50 double words (1600 bits)
for (n=1; n<50; n++) {
x1 = (x1>>1) ^ (x1>>4);
x1 = x1 ^ (x1<<31) ^ (x1<<28);
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
//printf("x1 : %x, x2 : %x\n",x1,x2);
}
for (n=0; n<52; n++) {
x1 = (x1>>1) ^ (x1>>4);
x1 = x1 ^ (x1<<31) ^ (x1<<28);
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
ue->nr_gold_pdcch[0][ns][l][n] = x1^x2;
// if (ns==1 && l==0) printf("n=%d : c %x\n",n,x1^x2);
} }
} }
} }
...@@ -114,6 +89,7 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue, ...@@ -114,6 +89,7 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue,
unsigned int n,x1,x2,x2tmp0; unsigned int n,x1,x2,x2tmp0;
int nscid; int nscid;
unsigned int nid; unsigned int nid;
uint8_t reset;
/// to be updated from higher layer /// to be updated from higher layer
//unsigned short lbar = 0; //unsigned short lbar = 0;
...@@ -126,32 +102,16 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue, ...@@ -126,32 +102,16 @@ void nr_gold_pdsch(PHY_VARS_NR_UE* ue,
//printf("gold pdsch nid %d lbar %d\n",nid,lbar); //printf("gold pdsch nid %d lbar %d\n",nid,lbar);
for (l=0; l<14; l++) { for (l=0; l<ue->frame_parms.symbols_per_slot; l++) {
x2tmp0 = ((14*ns+l+1)*((nid<<1)+1))<<17;
reset = 1;
x2tmp0 = ((ue->frame_parms.symbols_per_slot*ns+l+1)*((nid<<1)+1))<<17;
x2 = (x2tmp0+(nid<<1)+nscid)%(1<<31); //cinit x2 = (x2tmp0+(nid<<1)+nscid)%(1<<31); //cinit
LOG_D(PHY,"UE DMRS slot %d, symb %d, x2 %x, nscid %d\n",ns,l,x2,nscid); LOG_D(PHY,"UE DMRS slot %d, symb %d, x2 %x, nscid %d\n",ns,l,x2,nscid);
//printf("ns %d gold pdsch x2 %d\n",ns,x2);
x1 = 1+ (1<<31);
x2=x2 ^ ((x2 ^ (x2>>1) ^ (x2>>2) ^ (x2>>3))<<31);
// skip first 50 double words (1600 bits)
for (n=1; n<50; n++) {
x1 = (x1>>1) ^ (x1>>4);
x1 = x1 ^ (x1<<31) ^ (x1<<28);
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
//printf("x1 : %x, x2 : %x\n",x1,x2);
}
for (n=0; n<NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD; n++) { for (n=0; n<NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD; n++) {
x1 = (x1>>1) ^ (x1>>4); ue->nr_gold_pdsch[0][ns][l][nscid][n] = lte_gold_generic(&x1, &x2, reset);
x1 = x1 ^ (x1<<31) ^ (x1<<28); reset = 0;
x2 = (x2>>1) ^ (x2>>2) ^ (x2>>3) ^ (x2>>4);
x2 = x2 ^ (x2<<31) ^ (x2<<30) ^ (x2<<29) ^ (x2<<28);
ue->nr_gold_pdsch[nscid][ns][l][n] = x1^x2;
// if ((ns==2)&&(l==0))
//printf("n=%d : c %x\n",n,x1^x2);
} }
} }
} }
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
* \warning * \warning
*/ */
#include <LAYER2/NR_MAC_gNB/nr_mac_gNB.h>
#include "nr_dci.h" #include "nr_dci.h"
#include "nr_dlsch.h" #include "nr_dlsch.h"
#include "nr_sch_dmrs.h" #include "nr_sch_dmrs.h"
...@@ -81,23 +82,20 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -81,23 +82,20 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
int rb_offset; int rb_offset;
int n_rb; int n_rb;
// compute rb_offset and n_prb based on frequency allocation
nr_fill_cce_list(gNB,0,pdcch_pdu_rel15); nr_fill_cce_list(gNB,0,pdcch_pdu_rel15);
get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset); get_coreset_rballoc(pdcch_pdu_rel15->FreqDomainResource,&n_rb,&rb_offset);
// compute rb_offset and n_prb based on frequency allocation
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) {
cset_start_sc = frame_parms.first_carrier_offset +
(frame_parms.ssb_start_subcarrier/NR_NB_SC_PER_RB + rb_offset)*NR_NB_SC_PER_RB;
} else
cset_start_sc = frame_parms.first_carrier_offset + rb_offset*NR_NB_SC_PER_RB; cset_start_sc = frame_parms.first_carrier_offset + rb_offset*NR_NB_SC_PER_RB;
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) {
cset_start_sc = cset_start_sc + RC.nrmac[gNB->Mod_id]->type0_PDCCH_CSS_config.cset_start_rb*NR_NB_SC_PER_RB;
}
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) { for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
/*The coreset is initialised /*The coreset is initialised
* in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset for coreset 0 * in frequency: the first subcarrier is obtained by adding the first CRB overlapping the SSB and the rb_offset for coreset 0
* or the rb_offset for other coresets * or the rb_offset for other coresets
* in time: by its first slot and its first symbol*/ * in time: by its first slot and its first symbol*/
const nfapi_nr_dl_dci_pdu_t *dci_pdu = &pdcch_pdu_rel15->dci_pdu[d];
cset_start_symb = pdcch_pdu_rel15->StartSymbolIndex; cset_start_symb = pdcch_pdu_rel15->StartSymbolIndex;
cset_nsymb = pdcch_pdu_rel15->DurationSymbols; cset_nsymb = pdcch_pdu_rel15->DurationSymbols;
...@@ -105,11 +103,9 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -105,11 +103,9 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
LOG_D(PHY, "Coreset rb_offset %d, nb_rb %d\n",rb_offset,n_rb); LOG_D(PHY, "Coreset rb_offset %d, nb_rb %d\n",rb_offset,n_rb);
LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb); LOG_D(PHY, "Coreset starting subcarrier %d on symbol %d (%d symbols)\n", cset_start_sc, cset_start_symb, cset_nsymb);
// DMRS length is per OFDM symbol // DMRS length is per OFDM symbol
AssertFatal(pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED,
"Interleaved CCE REG MAPPING not supported\n");
uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)? uint32_t dmrs_length = (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED)?
(n_rb*6) : (pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE) (n_rb*6) : (dci_pdu->AggregationLevel*36/cset_nsymb); //2(QPSK)*3(per RB)*6(REG per CCE)
uint32_t encoded_length = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*108; //2(QPSK)*9(per RB)*6(REG per CCE) uint32_t encoded_length = dci_pdu->AggregationLevel*108; //2(QPSK)*9(per RB)*6(REG per CCE)
LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType); LOG_D(PHY, "DMRS length per symbol %d\t DCI encoded length %d (precoder_granularity %d,reg_mapping %d)\n", dmrs_length, encoded_length,pdcch_pdu_rel15->precoderGranularity,pdcch_pdu_rel15->CceRegMappingType);
dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset dmrs_length += rb_offset*6; // To accommodate more DMRS symbols in case of rb offset
...@@ -131,19 +127,19 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -131,19 +127,19 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
// CRC attachment + Scrambling + Channel coding + Rate matching // CRC attachment + Scrambling + Channel coding + Rate matching
uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD]; uint32_t encoder_output[NR_MAX_DCI_SIZE_DWORD];
uint16_t n_RNTI = pdcch_pdu_rel15->dci_pdu.RNTI[d]; uint16_t n_RNTI = dci_pdu->RNTI;
uint16_t Nid = pdcch_pdu_rel15->dci_pdu.ScramblingId[d]; uint16_t Nid = dci_pdu->ScramblingId;
uint16_t scrambling_RNTI = pdcch_pdu_rel15->dci_pdu.ScramblingRNTI[d]; uint16_t scrambling_RNTI = dci_pdu->ScramblingRNTI;
t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE, t_nrPolar_params *currentPtr = nr_polar_params(NR_POLAR_DCI_MESSAGE_TYPE,
pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], dci_pdu->PayloadSizeBits,
pdcch_pdu_rel15->dci_pdu.AggregationLevel[d], dci_pdu->AggregationLevel,
0,NULL); 0,NULL);
polar_encoder_fast((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d], (void*)encoder_output, n_RNTI,1,currentPtr); polar_encoder_fast((uint64_t*)dci_pdu->Payload, (void*)encoder_output, n_RNTI,1,currentPtr);
#ifdef DEBUG_CHANNEL_CODING #ifdef DEBUG_CHANNEL_CODING
printf("polar rnti %x,length %d, L %d\n",n_RNTI, pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d],pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]); printf("polar rnti %x,length %d, L %d\n",n_RNTI, dci_pdu->PayloadSizeBits,pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]);
printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n", printf("DCI PDU: [0]->0x%lx \t [1]->0x%lx\n",
((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[0], ((uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[d])[1]); ((uint64_t*)dci_pdu->Payload)[0], ((uint64_t*)dci_pdu->Payload)[1]);
printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5); printf("Encoded Payload (length:%d dwords):\n", encoded_length>>5);
for (int i=0; i<encoded_length>>5; i++) for (int i=0; i<encoded_length>>5; i++)
...@@ -176,8 +172,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -176,8 +172,8 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
cset_start_sc -= frame_parms.ofdm_symbol_size; cset_start_sc -= frame_parms.ofdm_symbol_size;
/*Reorder REG list for a freq first mapping*/ /*Reorder REG list for a freq first mapping*/
uint8_t reg_idx0 = pdcch_pdu_rel15->dci_pdu.CceIndex[d]*NR_NB_REG_PER_CCE; uint8_t reg_idx0 = dci_pdu->CceIndex*NR_NB_REG_PER_CCE;
uint8_t nb_regs = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]*NR_NB_REG_PER_CCE; uint8_t nb_regs = dci_pdu->AggregationLevel*NR_NB_REG_PER_CCE;
/*Mapping the encoded DCI along with the DMRS */ /*Mapping the encoded DCI along with the DMRS */
for (int reg_idx=reg_idx0; reg_idx<(nb_regs+reg_idx0); reg_idx++) { for (int reg_idx=reg_idx0; reg_idx<(nb_regs+reg_idx0); reg_idx++) {
...@@ -198,7 +194,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -198,7 +194,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
for (int m=0; m<NR_NB_SC_PER_RB; m++) { for (int m=0; m<NR_NB_SC_PER_RB; m++) {
if ( m == (k_prime<<2)+1) { // DMRS if not already mapped if ( m == (k_prime<<2)+1) { // DMRS if not already mapped
if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) { //if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED) {
((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15; ((int16_t *)txdataF)[(l*frame_parms.ofdm_symbol_size + k)<<1] = (amp * mod_dmrs[l][dmrs_idx<<1]) >> 15;
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15; ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (amp * mod_dmrs[l][(dmrs_idx<<1) + 1]) >> 15;
#ifdef DEBUG_PDCCH_DMRS #ifdef DEBUG_PDCCH_DMRS
...@@ -206,7 +202,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -206,7 +202,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]); ((int16_t *)txdataF)[((l*frame_parms.ofdm_symbol_size + k)<<1)+1]);
#endif #endif
dmrs_idx++; dmrs_idx++;
} //}
k_prime++; k_prime++;
} else { // DCI payload } else { // DCI payload
...@@ -226,6 +222,11 @@ void nr_generate_dci(PHY_VARS_gNB *gNB, ...@@ -226,6 +222,11 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
} // m } // m
} // reg_idx } // reg_idx
LOG_D(PHY,
"DCI: payloadSize = %d | payload = %llx\n",
dci_pdu->PayloadSizeBits,
*(unsigned long long *)dci_pdu->Payload);
} // for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) } // for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++)
} }
......
...@@ -142,7 +142,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m, nfapi_nr_dl_tti_pdcch_pdu_r ...@@ -142,7 +142,7 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m, nfapi_nr_dl_tti_pdcch_pdu_r
AssertFatal(N_reg > 0,"N_reg cannot be 0\n"); AssertFatal(N_reg > 0,"N_reg cannot be 0\n");
for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) { for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++) {
int L = pdcch_pdu_rel15->dci_pdu.AggregationLevel[d]; int L = pdcch_pdu_rel15->dci_pdu[d].AggregationLevel;
if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1) if (pdcch_pdu_rel15->CoreSetType == NFAPI_NR_CSET_CONFIG_MIB_SIB1)
AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L); AssertFatal(L>=4, "Invalid aggregation level for SIB1 configured PDCCH %d\n", L);
...@@ -153,10 +153,10 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m, nfapi_nr_dl_tti_pdcch_pdu_r ...@@ -153,10 +153,10 @@ void nr_fill_cce_list(PHY_VARS_gNB *gNB, uint8_t m, nfapi_nr_dl_tti_pdcch_pdu_r
C = N_reg/(bsize*R); C = N_reg/(bsize*R);
} }
LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->dci_pdu.CceIndex[d]); LOG_D(PHY, "CCE list generation for candidate %d: bundle size %d ilv size %d CceIndex %d\n", m, bsize, R, pdcch_pdu_rel15->dci_pdu[d].CceIndex);
for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) { for (uint8_t cce_idx=0; cce_idx<L; cce_idx++) {
cce = &gNB->cce_list[d][cce_idx]; cce = &gNB->cce_list[d][cce_idx];
cce->cce_idx = pdcch_pdu_rel15->dci_pdu.CceIndex[d] + cce_idx; cce->cce_idx = pdcch_pdu_rel15->dci_pdu[d].CceIndex + cce_idx;
LOG_D(PHY, "cce_idx %d\n", cce->cce_idx); LOG_D(PHY, "cce_idx %d\n", cce->cce_idx);
if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) { if (pdcch_pdu_rel15->CceRegMappingType == NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED) {
...@@ -236,25 +236,24 @@ void nr_fill_dci(PHY_VARS_gNB *gNB, ...@@ -236,25 +236,24 @@ void nr_fill_dci(PHY_VARS_gNB *gNB,
for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) { for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) {
//uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i]; //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu[i].Payload;
int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->dci_pdu.RNTI[i],gNB,SEARCH_EXIST_OR_FREE); int dlsch_id = find_nr_dlsch(pdcch_pdu_rel15->dci_pdu[i].RNTI,gNB,SEARCH_EXIST_OR_FREE);
if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){ if( (dlsch_id<0) || (dlsch_id>=NUMBER_OF_NR_DLSCH_MAX) ){
LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->dci_pdu.RNTI[i],dlsch_id); LOG_E(PHY,"illegal dlsch_id found!!! rnti %04x dlsch_id %d\n",(unsigned int)pdcch_pdu_rel15->dci_pdu[i].RNTI,dlsch_id);
return; return;
} }
dlsch = gNB->dlsch[dlsch_id][0]; dlsch = gNB->dlsch[dlsch_id][0];
int num_slots_tdd = (gNB->frame_parms.slots_per_frame)>>(7-gNB->gNB_config.tdd_table.tdd_period.value); int harq_pid = 0;//slot % num_slots_tdd;
int harq_pid = slot % num_slots_tdd;
dlsch->slot_tx[slot] = 1; dlsch->slot_tx[slot] = 1;
dlsch->harq_ids[frame%2][slot] = harq_pid; dlsch->harq_ids[frame%2][slot] = 0;//harq_pid;
AssertFatal(harq_pid < 8 && harq_pid >= 0, AssertFatal(harq_pid < 8 && harq_pid >= 0,
"illegal harq_pid %d\n",harq_pid); "illegal harq_pid %d\n",harq_pid);
dlsch->harq_mask |= (1<<harq_pid); dlsch->harq_mask |= (1<<harq_pid);
dlsch->rnti = pdcch_pdu_rel15->dci_pdu.RNTI[i]; dlsch->rnti = pdcch_pdu_rel15->dci_pdu[i].RNTI;
// nr_fill_cce_list(gNB,0); // nr_fill_cce_list(gNB,0);
/* /*
...@@ -300,7 +299,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB, ...@@ -300,7 +299,7 @@ void nr_fill_ul_dci(PHY_VARS_gNB *gNB,
for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) { for (int i=0;i<pdcch_pdu_rel15->numDlDci;i++) {
//uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu.Payload[i]; //uint64_t *dci_pdu = (uint64_t*)pdcch_pdu_rel15->dci_pdu[i].Payload;
// if there's no DL DCI then generate CCE list // if there's no DL DCI then generate CCE list
// nr_fill_cce_list(gNB,0); // nr_fill_cce_list(gNB,0);
......
...@@ -136,8 +136,7 @@ uint8_t nr_generate_pdsch(PHY_VARS_gNB *gNB, ...@@ -136,8 +136,7 @@ uint8_t nr_generate_pdsch(PHY_VARS_gNB *gNB,
dlsch = gNB->dlsch[dlsch_id][0]; dlsch = gNB->dlsch[dlsch_id][0];
if (dlsch->slot_tx[slot] == 0) continue; if (dlsch->slot_tx[slot] == 0) continue;
int harq_pid = dlsch->harq_ids[frame%2][slot]; NR_DL_gNB_HARQ_t *harq = &dlsch->harq_process;
NR_DL_gNB_HARQ_t *harq = dlsch->harq_processes[harq_pid];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15; nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &harq->pdsch_pdu.pdsch_pdu_rel15;
uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5]; uint32_t scrambled_output[NR_MAX_NB_CODEWORDS][NR_MAX_PDSCH_ENCODED_LENGTH>>5];
int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs; int16_t **mod_symbs = (int16_t**)dlsch->mod_symbs;
...@@ -289,7 +288,7 @@ uint8_t nr_generate_pdsch(PHY_VARS_gNB *gNB, ...@@ -289,7 +288,7 @@ uint8_t nr_generate_pdsch(PHY_VARS_gNB *gNB,
/// Resource mapping /// Resource mapping
// Non interleaved VRB to PRB mapping // Non interleaved VRB to PRB mapping
uint16_t start_sc = frame_parms->first_carrier_offset + rel15->rbStart*NR_NB_SC_PER_RB; uint16_t start_sc = frame_parms->first_carrier_offset + (rel15->rbStart+rel15->BWPStart)*NR_NB_SC_PER_RB;
if (start_sc >= frame_parms->ofdm_symbol_size) if (start_sc >= frame_parms->ofdm_symbol_size)
start_sc -= frame_parms->ofdm_symbol_size; start_sc -= frame_parms->ofdm_symbol_size;
...@@ -421,15 +420,8 @@ void dump_pdsch_stats(PHY_VARS_gNB *gNB) { ...@@ -421,15 +420,8 @@ void dump_pdsch_stats(PHY_VARS_gNB *gNB) {
for (int i=0;i<NUMBER_OF_NR_SCH_STATS_MAX;i++) for (int i=0;i<NUMBER_OF_NR_SCH_STATS_MAX;i++)
if (gNB->dlsch_stats[i].rnti > 0) if (gNB->dlsch_stats[i].rnti > 0)
LOG_I(PHY,"DLSCH RNTI %x: round_trials %d(%1.1e):%d(%1.1e):%d(%1.1e):%d, current_Qm %d, current_RI %d, total_bytes TX %d\n", LOG_D(PHY,"DLSCH RNTI %x: current_Qm %d, current_RI %d, total_bytes TX %d\n",
gNB->dlsch_stats[i].rnti, gNB->dlsch_stats[i].rnti,
gNB->dlsch_stats[i].round_trials[0],
(double)gNB->dlsch_stats[i].round_trials[1]/gNB->dlsch_stats[i].round_trials[0],
gNB->dlsch_stats[i].round_trials[1],
(double)gNB->dlsch_stats[i].round_trials[2]/gNB->dlsch_stats[i].round_trials[0],
gNB->dlsch_stats[i].round_trials[2],
(double)gNB->dlsch_stats[i].round_trials[3]/gNB->dlsch_stats[i].round_trials[0],
gNB->dlsch_stats[i].round_trials[3],
gNB->dlsch_stats[i].current_Qm, gNB->dlsch_stats[i].current_Qm,
gNB->dlsch_stats[i].current_RI, gNB->dlsch_stats[i].current_RI,
gNB->dlsch_stats[i].total_bytes_tx); gNB->dlsch_stats[i].total_bytes_tx);
......
...@@ -95,7 +95,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB, ...@@ -95,7 +95,7 @@ int nr_dlsch_encoding(PHY_VARS_gNB *gNB,
time_stats_t *dlsch_interleaving_stats, time_stats_t *dlsch_interleaving_stats,
time_stats_t *dlsch_segmentation_stats); time_stats_t *dlsch_segmentation_stats);
void init_dlsch_tpool(uint8_t nun_dlsch_threads);
void nr_emulate_dlsch_payload(uint8_t* payload, uint16_t size); void nr_emulate_dlsch_payload(uint8_t* payload, uint16_t size);
void dump_pdsch_stats(PHY_VARS_gNB *gNB); void dump_pdsch_stats(PHY_VARS_gNB *gNB);
......
This diff is collapsed.
...@@ -289,12 +289,12 @@ void nr_fill_dlsch(PHY_VARS_gNB *gNB, ...@@ -289,12 +289,12 @@ void nr_fill_dlsch(PHY_VARS_gNB *gNB,
AssertFatal( (dlsch_id>=0) && (dlsch_id<NUMBER_OF_NR_DLSCH_MAX), AssertFatal( (dlsch_id>=0) && (dlsch_id<NUMBER_OF_NR_DLSCH_MAX),
"illegal or no dlsch_id found!!! rnti %04x dlsch_id %d\n",rel15->rnti,dlsch_id); "illegal or no dlsch_id found!!! rnti %04x dlsch_id %d\n",rel15->rnti,dlsch_id);
NR_gNB_DLSCH_t *dlsch = gNB->dlsch[dlsch_id][0]; NR_gNB_DLSCH_t *dlsch = gNB->dlsch[dlsch_id][0];
NR_DL_gNB_HARQ_t **harq = dlsch->harq_processes; NR_DL_gNB_HARQ_t *harq = &dlsch->harq_process;
/// DLSCH struct /// DLSCH struct
memcpy((void*)&harq[dlsch->harq_ids[frame%2][slot]]->pdsch_pdu, (void*)pdsch_pdu, sizeof(nfapi_nr_dl_tti_pdsch_pdu)); memcpy((void*)&harq->pdsch_pdu, (void*)pdsch_pdu, sizeof(nfapi_nr_dl_tti_pdsch_pdu));
gNB->num_pdsch_rnti[slot]++; gNB->num_pdsch_rnti[slot]++;
AssertFatal(sdu!=NULL,"sdu is null\n"); AssertFatal(sdu!=NULL,"sdu is null\n");
harq[dlsch->harq_ids[frame%2][slot]]->pdu = sdu; harq->pdu = sdu;
} }
......
...@@ -393,6 +393,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, ...@@ -393,6 +393,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB,
// first bit of bitmap for sr presence and second bit for acknack presence // first bit of bitmap for sr presence and second bit for acknack presence
uci_pdu->pduBitmap = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1); uci_pdu->pduBitmap = pucch_pdu->sr_flag | ((pucch_pdu->bit_len_harq>0)<<1);
uci_pdu->pucch_format = 0; // format 0 uci_pdu->pucch_format = 0; // format 0
uci_pdu->rnti=pucch_pdu->rnti;
uci_pdu->ul_cqi = cqi; uci_pdu->ul_cqi = cqi;
uci_pdu->timing_advance = 0xffff; // currently not valid uci_pdu->timing_advance = 0xffff; // currently not valid
uci_pdu->rssi = 1280 - (10*dB_fixed(32767*32767)-dB_fixed_times10(signal_energy_nodc(&rxdataF[0][pucch_pdu->start_symbol_index*frame_parms->ofdm_symbol_size+re_offset],12))); uci_pdu->rssi = 1280 - (10*dB_fixed(32767*32767)-dB_fixed_times10(signal_energy_nodc(&rxdataF[0][pucch_pdu->start_symbol_index*frame_parms->ofdm_symbol_size+re_offset],12)));
......
...@@ -653,6 +653,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue, ...@@ -653,6 +653,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
unsigned char Ns, unsigned char Ns,
unsigned short p, unsigned short p,
unsigned char symbol, unsigned char symbol,
unsigned short BWPStart,
unsigned short bwp_start_subcarrier, unsigned short bwp_start_subcarrier,
unsigned short nb_rb_pdsch) unsigned short nb_rb_pdsch)
{ {
...@@ -686,10 +687,10 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue, ...@@ -686,10 +687,10 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
#endif #endif
// generate pilot for gNB port number 1000+p // generate pilot for gNB port number 1000+p
uint16_t rb_offset = (bwp_start_subcarrier - ue->frame_parms.first_carrier_offset) / 12; uint16_t rb_offset = (bwp_start_subcarrier - ue->frame_parms.first_carrier_offset) / 12 - BWPStart;
uint8_t config_type = ue->dmrs_DownlinkConfig.pdsch_dmrs_type; uint8_t config_type = ue->dmrs_DownlinkConfig.pdsch_dmrs_type;
int8_t delta = get_delta(p, config_type); int8_t delta = get_delta(p, config_type);
nr_pdsch_dmrs_rx(ue,Ns,ue->nr_gold_pdsch[eNB_offset][Ns][symbol], &pilot[0],1000,0,nb_rb_pdsch+rb_offset); nr_pdsch_dmrs_rx(ue,Ns,ue->nr_gold_pdsch[eNB_offset][Ns][symbol][0], &pilot[0],1000,0,nb_rb_pdsch+rb_offset);
if (config_type == pdsch_dmrs_type1){ if (config_type == pdsch_dmrs_type1){
nushift = (p>>1)&1; nushift = (p>>1)&1;
...@@ -1321,7 +1322,7 @@ void nr_pdsch_ptrs_processing(PHY_VARS_NR_UE *ue, ...@@ -1321,7 +1322,7 @@ void nr_pdsch_ptrs_processing(PHY_VARS_NR_UE *ue,
nr_slot_rx, nr_slot_rx,
symbol,frame_parms->ofdm_symbol_size, symbol,frame_parms->ofdm_symbol_size,
(int16_t*)&pdsch_vars[eNB_id]->rxdataF_comp0[aarx][(symbol * nb_re_pdsch)], (int16_t*)&pdsch_vars[eNB_id]->rxdataF_comp0[aarx][(symbol * nb_re_pdsch)],
ue->nr_gold_pdsch[eNB_id][nr_slot_rx][symbol], ue->nr_gold_pdsch[eNB_id][nr_slot_rx][symbol][0],
&phase_per_symbol[2* symbol], &phase_per_symbol[2* symbol],
&ptrs_re_symbol[symbol]); &ptrs_re_symbol[symbol]);
} }
......
...@@ -73,6 +73,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue, ...@@ -73,6 +73,7 @@ int nr_pdsch_channel_estimation(PHY_VARS_NR_UE *ue,
unsigned char Ns, unsigned char Ns,
unsigned short p, unsigned short p,
unsigned char symbol, unsigned char symbol,
unsigned short BWPStart,
unsigned short bwp_start_subcarrier, unsigned short bwp_start_subcarrier,
unsigned short nb_rb_pdsch); unsigned short nb_rb_pdsch);
......
...@@ -36,6 +36,8 @@ ...@@ -36,6 +36,8 @@
#include <string.h> #include <string.h>
#endif #endif
#include <LAYER2/NR_MAC_UE/mac_defs.h>
#include <LAYER2/NR_MAC_UE/mac_proto.h>
#include "executables/softmodem-common.h" #include "executables/softmodem-common.h"
#include "nr_transport_proto_ue.h" #include "nr_transport_proto_ue.h"
...@@ -371,7 +373,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, ...@@ -371,7 +373,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
LOG_DDD("n_BWP_start=%d, coreset_nbr_rb=%d\n",n_BWP_start,coreset_nbr_rb); LOG_DDD("n_BWP_start=%d, coreset_nbr_rb=%d\n",n_BWP_start,coreset_nbr_rb);
int c_rb_by6; int c_rb_by6;
c_rb = n_BWP_start; c_rb = 0;
for (int rb=0;rb<coreset_nbr_rb;rb++,c_rb++) { for (int rb=0;rb<coreset_nbr_rb;rb++,c_rb++) {
c_rb_by6 = c_rb/6; c_rb_by6 = c_rb/6;
// skip zeros in frequency domain bitmap // skip zeros in frequency domain bitmap
...@@ -386,7 +388,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, ...@@ -386,7 +388,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
// first we set initial conditions for pointer to rxdataF depending on the situation of the first RB within the CORESET (c_rb = n_BWP_start) // first we set initial conditions for pointer to rxdataF depending on the situation of the first RB within the CORESET (c_rb = n_BWP_start)
if ((c_rb < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) == 0)) { if ((c_rb < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) == 0)) {
//if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): even case //if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): even case
rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))]; rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))+n_BWP_start*12];
LOG_DDD("in even case c_rb (%d) is lower than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", LOG_DDD("in even case c_rb (%d) is lower than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))); c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))));
} }
...@@ -394,7 +396,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, ...@@ -394,7 +396,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
if ((c_rb >= (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) == 0)) { if ((c_rb >= (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) == 0)) {
// number of RBs is even and c_rb is higher than half system bandwidth (we don't skip DC) // number of RBs is even and c_rb is higher than half system bandwidth (we don't skip DC)
// if these conditions are true the pointer has to be situated at the 1st part of the rxdataF // if these conditions are true the pointer has to be situated at the 1st part of the rxdataF
rxF = &rxdataF[aarx][(12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol rxF = &rxdataF[aarx][(12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size)))+n_BWP_start*12]; // we point at the 1st part of the rxdataF in symbol
LOG_DDD("in even case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", LOG_DDD("in even case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size)))); c_rb,aarx,(12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size))));
//rxF = &rxdataF[aarx][(1 + 12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol //rxF = &rxdataF[aarx][(1 + 12*(c_rb - (frame_parms->N_RB_DL>>1)) + (symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol
...@@ -406,7 +408,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, ...@@ -406,7 +408,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
if ((c_rb < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { if ((c_rb < (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) {
//if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): odd case //if RB to be treated is lower than middle system bandwidth then rxdataF pointed at (offset + c_br + symbol * ofdm_symbol_size): odd case
rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))]; rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))+n_BWP_start*12];
#ifdef NR_PDCCH_DCI_DEBUG #ifdef NR_PDCCH_DCI_DEBUG
LOG_D(PHY,"in odd case c_rb (%d) is lower or equal than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", LOG_D(PHY,"in odd case c_rb (%d) is lower or equal than half N_RB_DL -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))); c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))));
...@@ -416,7 +418,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, ...@@ -416,7 +418,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
if ((c_rb > (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { if ((c_rb > (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) {
// number of RBs is odd and c_rb is higher than half system bandwidth + 1 // number of RBs is odd and c_rb is higher than half system bandwidth + 1
// if these conditions are true the pointer has to be situated at the 1st part of the rxdataF just after the first IQ symbols of the RB containing DC // if these conditions are true the pointer has to be situated at the 1st part of the rxdataF just after the first IQ symbols of the RB containing DC
rxF = &rxdataF[aarx][(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size)))]; // we point at the 1st part of the rxdataF in symbol rxF = &rxdataF[aarx][(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size)))+n_BWP_start*12]; // we point at the 1st part of the rxdataF in symbol
#ifdef NR_PDCCH_DCI_DEBUG #ifdef NR_PDCCH_DCI_DEBUG
LOG_D(PHY,"in odd case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - frame_parms->N_RB_DL) - 5 + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", LOG_D(PHY,"in odd case c_rb (%d) is higher than half N_RB_DL (not DC) -> rxF = &rxdataF[aarx = (%d)][(12*(c_rb - frame_parms->N_RB_DL) - 5 + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size)))); c_rb,aarx,(12*(c_rb - (frame_parms->N_RB_DL>>1)) - 6 + (symbol * (frame_parms->ofdm_symbol_size))));
...@@ -426,7 +428,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF, ...@@ -426,7 +428,7 @@ void nr_pdcch_extract_rbs_single(int32_t **rxdataF,
if ((c_rb == (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { // treatment of RB containing the DC if ((c_rb == (frame_parms->N_RB_DL >> 1)) && ((frame_parms->N_RB_DL & 1) != 0)) { // treatment of RB containing the DC
// if odd number RBs in system bandwidth and first RB to be treated is higher than middle system bandwidth (around DC) // if odd number RBs in system bandwidth and first RB to be treated is higher than middle system bandwidth (around DC)
// we have to treat the RB in two parts: first part from i=0 to 5, the data is at the end of rxdataF (pointing at the end of the table) // we have to treat the RB in two parts: first part from i=0 to 5, the data is at the end of rxdataF (pointing at the end of the table)
rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))]; rxF = &rxdataF[aarx][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))+n_BWP_start*12];
#ifdef NR_PDCCH_DCI_DEBUG #ifdef NR_PDCCH_DCI_DEBUG
LOG_D(PHY,"in odd case c_rb (%d) is half N_RB_DL + 1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n", LOG_D(PHY,"in odd case c_rb (%d) is half N_RB_DL + 1 we treat DC case -> rxF = &rxdataF[aarx = (%d)][(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))) = (%d)]\n",
c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size)))); c_rb,aarx,(frame_parms->first_carrier_offset + 12 * c_rb + (symbol * (frame_parms->ofdm_symbol_size))));
...@@ -887,7 +889,8 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -887,7 +889,8 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
n_rnti = rel15->rnti; n_rnti = rel15->rnti;
if (crc == n_rnti) { if (crc == n_rnti) {
LOG_D(PHY,"Decoded crc %x matches rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format_options[k]); LOG_I(PHY, "(%i.%i) Received dci indication (rnti %x,dci format %d,n_CCE %d,payloadSize %d,payload %llx)\n",
proc->frame_rx, proc->nr_slot_rx,n_rnti,rel15->dci_format_options[k],CCEind,dci_length,*(unsigned long long*)dci_estimation);
dci_ind->SFN = proc->frame_rx; dci_ind->SFN = proc->frame_rx;
dci_ind->slot = proc->nr_slot_rx; dci_ind->slot = proc->nr_slot_rx;
dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti; dci_ind->dci_list[dci_ind->number_of_dcis].rnti = n_rnti;
...@@ -898,7 +901,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue, ...@@ -898,7 +901,7 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
dci_ind->number_of_dcis++; dci_ind->number_of_dcis++;
break; // If DCI is found, no need to check for remaining DCI lengths break; // If DCI is found, no need to check for remaining DCI lengths
} else { } else {
LOG_D(PHY,"Decoded crc %x does not match rnti %x for DCI format %d\n", crc, n_rnti, rel15->dci_format_options[k]); LOG_D(PHY,"(%i.%i) Decoded crc %x does not match rnti %x for DCI format %d\n", proc->frame_rx, proc->nr_slot_rx, crc, n_rnti, rel15->dci_format_options[k]);
} }
} }
} }
......
...@@ -404,7 +404,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue, ...@@ -404,7 +404,7 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
symbol, symbol,
pilots, pilots,
config_type, config_type,
start_rb, start_rb + dlsch0_harq->BWPStart,
nb_rb_pdsch, nb_rb_pdsch,
nr_slot_rx, nr_slot_rx,
ue->high_speed_flag, ue->high_speed_flag,
...@@ -1621,6 +1621,8 @@ void nr_dlsch_channel_level(int **dl_ch_estimates_ext, ...@@ -1621,6 +1621,8 @@ void nr_dlsch_channel_level(int **dl_ch_estimates_ext,
int16_t y = (len)>>x; int16_t y = (len)>>x;
//printf("len = %d = %d * 2^(%d)\n",len,y,x); //printf("len = %d = %d * 2^(%d)\n",len,y,x);
AssertFatal(y!=0,"Cannot divide by zero: in function %s of file %s\n", __func__, __FILE__);
for (aatx=0; aatx<frame_parms->nb_antenna_ports_gNB; aatx++) for (aatx=0; aatx<frame_parms->nb_antenna_ports_gNB; aatx++)
for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) { for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++) {
//clear average level //clear average level
......
This diff is collapsed.
...@@ -94,8 +94,6 @@ typedef struct { ...@@ -94,8 +94,6 @@ typedef struct {
uint32_t frame; uint32_t frame;
/// Subframe where current HARQ round was sent /// Subframe where current HARQ round was sent
uint32_t subframe; uint32_t subframe;
/// Index of current HARQ round for this DLSCH
uint8_t round;
/// MIMO mode for this DLSCH /// MIMO mode for this DLSCH
MIMO_mode_t mimo_mode; MIMO_mode_t mimo_mode;
/// Concatenated sequences /// Concatenated sequences
...@@ -138,8 +136,8 @@ typedef struct { ...@@ -138,8 +136,8 @@ typedef struct {
} NR_gNB_SCH_STATS_t; } NR_gNB_SCH_STATS_t;
typedef struct { typedef struct {
/// Pointers to 16 HARQ processes for the DLSCH /// Pointers to variables related to DLSCH harq process
NR_DL_gNB_HARQ_t *harq_processes[NR_MAX_NB_HARQ_PROCESSES]; NR_DL_gNB_HARQ_t harq_process;
/// TX buffers for UE-spec transmission (antenna ports 5 or 7..14, prior to precoding) /// TX buffers for UE-spec transmission (antenna ports 5 or 7..14, prior to precoding)
int32_t *txdataF[NR_MAX_NB_LAYERS]; int32_t *txdataF[NR_MAX_NB_LAYERS];
/// Modulated symbols buffer /// Modulated symbols buffer
......
...@@ -889,7 +889,7 @@ typedef struct { ...@@ -889,7 +889,7 @@ typedef struct {
UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_gNB_MAX]; UE_MODE_t UE_mode[NUMBER_OF_CONNECTED_gNB_MAX];
/// cell-specific reference symbols /// cell-specific reference symbols
uint32_t lte_gold_table[7][20][2][14]; //uint32_t lte_gold_table[7][20][2][14];
#if defined(UPGRADE_RAT_NR) #if defined(UPGRADE_RAT_NR)
...@@ -903,10 +903,10 @@ typedef struct { ...@@ -903,10 +903,10 @@ typedef struct {
uint32_t nr_gold_pbch[2][64][NR_PBCH_DMRS_LENGTH_DWORD]; uint32_t nr_gold_pbch[2][64][NR_PBCH_DMRS_LENGTH_DWORD];
/// PDSCH DMRS /// PDSCH DMRS
uint32_t nr_gold_pdsch[2][20][14][NR_MAX_PDSCH_DMRS_INIT_LENGTH_DWORD]; uint32_t ****nr_gold_pdsch[NUMBER_OF_CONNECTED_eNB_MAX];
/// PDCCH DMRS /// PDCCH DMRS
uint32_t nr_gold_pdcch[7][20][3][52]; uint32_t ***nr_gold_pdcch[NUMBER_OF_CONNECTED_eNB_MAX];
/// PUSCH DMRS sequence /// PUSCH DMRS sequence
uint32_t ****nr_gold_pusch_dmrs; uint32_t ****nr_gold_pusch_dmrs;
......
...@@ -104,6 +104,7 @@ ...@@ -104,6 +104,7 @@
#define NR_MAX_PDSCH_ENCODED_LENGTH NR_MAX_NB_RB*NR_SYMBOLS_PER_SLOT*NR_NB_SC_PER_RB*8*NR_MAX_NB_LAYERS // 8 is the maximum modulation order (it was 950984 before !!) #define NR_MAX_PDSCH_ENCODED_LENGTH NR_MAX_NB_RB*NR_SYMBOLS_PER_SLOT*NR_NB_SC_PER_RB*8*NR_MAX_NB_LAYERS // 8 is the maximum modulation order (it was 950984 before !!)
#define NR_MAX_PUSCH_ENCODED_LENGTH NR_MAX_PDSCH_ENCODED_LENGTH #define NR_MAX_PUSCH_ENCODED_LENGTH NR_MAX_PDSCH_ENCODED_LENGTH
#define NR_MAX_PDSCH_TBS 3824 #define NR_MAX_PDSCH_TBS 3824
#define NR_MAX_SIB_LENGTH 2976 // 3GPP TS 38.331 section 5.2.1 - The physical layer imposes a limit to the maximum size a SIB can take. The maximum SIB1 or SI message size is 2976 bits.
#define MAX_NUM_NR_DLSCH_SEGMENTS 34 #define MAX_NUM_NR_DLSCH_SEGMENTS 34
#define MAX_NR_DLSCH_PAYLOAD_BYTES (MAX_NUM_NR_DLSCH_SEGMENTS*1056) #define MAX_NR_DLSCH_PAYLOAD_BYTES (MAX_NUM_NR_DLSCH_SEGMENTS*1056)
......
...@@ -201,10 +201,10 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, ...@@ -201,10 +201,10 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,1);
LOG_D(PHY, "PDSCH generation started (%d) in frame %d.%d\n", gNB->num_pdsch_rnti[slot],frame,slot); LOG_D(PHY, "PDSCH generation started (%d) in frame %d.%d\n", gNB->num_pdsch_rnti[slot],frame,slot);
nr_generate_pdsch(gNB,frame, slot); nr_generate_pdsch(gNB,frame, slot);
if ((frame&127) == 0) dump_pdsch_stats(gNB);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0);
} }
if ((frame&127) == 0) dump_pdsch_stats(gNB);
//apply the OFDM symbol rotation here //apply the OFDM symbol rotation here
apply_nr_rotation(fp,(int16_t*) &gNB->common_vars.txdataF[0][txdataF_offset],slot,0,fp->Ncp==EXTENDED?12:14,fp->ofdm_symbol_size); apply_nr_rotation(fp,(int16_t*) &gNB->common_vars.txdataF[0][txdataF_offset],slot,0,fp->Ncp==EXTENDED?12:14,fp->ofdm_symbol_size);
......
...@@ -114,11 +114,13 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t ...@@ -114,11 +114,13 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, uint8_t
@param proc Pointer to proc information @param proc Pointer to proc information
@param gNB_id Local id of eNB on which to act @param gNB_id Local id of eNB on which to act
@param mode calibration/debug mode @param mode calibration/debug mode
@param dlsch_parallel use multithreaded dlsch processing
*/ */
int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
UE_nr_rxtx_proc_t *proc, UE_nr_rxtx_proc_t *proc,
uint8_t gNB_id, uint8_t gNB_id,
runmode_t mode); runmode_t mode,
uint8_t dlsch_parallel);
int phy_procedures_slot_parallelization_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,uint8_t do_pdcch_flag,runmode_t mode,relaying_type_t r_type); int phy_procedures_slot_parallelization_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,uint8_t do_pdcch_flag,runmode_t mode,relaying_type_t r_type);
......
...@@ -84,6 +84,11 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ ...@@ -84,6 +84,11 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
LOG_D(PHY,"FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH\n"); LOG_D(PHY,"FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH\n");
dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch_ra[0]; dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch_ra[0];
} }
else if (dl_config->dl_config_list[i].pdu_type == FAPI_NR_DL_CONFIG_TYPE_SI_DLSCH){
dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch_SI[0];
dlsch0->rnti_type = _SI_RNTI_;
dlsch0->harq_processes[dlsch0->current_harq_pid]->status = ACTIVE;
}
fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15; fapi_nr_dl_config_dlsch_pdu_rel15_t *dlsch_config_pdu = &dl_config->dl_config_list[i].dlsch_config_pdu.dlsch_config_rel15;
uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr; uint8_t current_harq_pid = dlsch_config_pdu->harq_process_nbr;
...@@ -115,6 +120,11 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){ ...@@ -115,6 +120,11 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
dlsch0_harq->Nl=1; dlsch0_harq->Nl=1;
dlsch0_harq->mcs_table=dlsch_config_pdu->mcs_table; dlsch0_harq->mcs_table=dlsch_config_pdu->mcs_table;
dlsch0_harq->harq_ack.rx_status = downlink_harq_process(dlsch0_harq, dlsch0->current_harq_pid, dlsch_config_pdu->ndi, dlsch0->rnti_type); dlsch0_harq->harq_ack.rx_status = downlink_harq_process(dlsch0_harq, dlsch0->current_harq_pid, dlsch_config_pdu->ndi, dlsch0->rnti_type);
if (dlsch0_harq->status != ACTIVE) {
// dlsch0_harq->status not ACTIVE may be due to false retransmission. Reset the
// following flag to skip PDSCH procedures in that case.
dlsch0->active = 0;
}
dlsch0_harq->harq_ack.vDAI_DL = dlsch_config_pdu->dai; dlsch0_harq->harq_ack.vDAI_DL = dlsch_config_pdu->dai;
/* PTRS */ /* PTRS */
dlsch0_harq->PTRSFreqDensity = dlsch_config_pdu->PTRSFreqDensity; dlsch0_harq->PTRSFreqDensity = dlsch_config_pdu->PTRSFreqDensity;
......
This diff is collapsed.
...@@ -447,7 +447,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ ...@@ -447,7 +447,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
return (FALSE); return (FALSE);
} }
int max_code_rate = 0; //int max_code_rate = 0;
//int Q_m = BITS_PER_SYMBOL_QPSK; /* default pucch modulation type is QPSK with 2 bits per symbol */ //int Q_m = BITS_PER_SYMBOL_QPSK; /* default pucch modulation type is QPSK with 2 bits per symbol */
int N_sc_ctrl_RB = 0; int N_sc_ctrl_RB = 0;
int O_CRC = 0; int O_CRC = 0;
...@@ -504,7 +504,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_ ...@@ -504,7 +504,7 @@ bool pucch_procedures_ue_nr(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_
if (format != pucch_format0_nr) { if (format != pucch_format0_nr) {
if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) { if (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1 != NULL) {
max_code_rate = code_rate_r_time_100[mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->maxCodeRate[0]]; /* it is code rate * 10 */ //max_code_rate = code_rate_r_time_100[mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->maxCodeRate[0]]; /* it is code rate * 10 */
if ((O_ACK != 0) && (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->simultaneousHARQ_ACK_CSI[0] == 0)) { if ((O_ACK != 0) && (mac->ULbwp[bwp_id-1]->bwp_Dedicated->pucch_Config->choice.setup->format1->choice.setup->simultaneousHARQ_ACK_CSI[0] == 0)) {
N_UCI = N_UCI - O_CSI; N_UCI = N_UCI - O_CSI;
...@@ -809,6 +809,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t ...@@ -809,6 +809,7 @@ uint8_t get_downlink_ack(PHY_VARS_NR_UE *ue, uint8_t gNB_id, UE_nr_rxtx_proc_t
number_harq_feedback++; number_harq_feedback++;
ack_data[code_word][dai_current - 1] = harq_status->ack; ack_data[code_word][dai_current - 1] = harq_status->ack;
dai[code_word][dai_current - 1] = dai_current; dai[code_word][dai_current - 1] = dai_current;
harq_status->slot_for_feedback_ack = NR_MAX_SLOTS_PER_FRAME;
} }
if (do_reset == TRUE) { if (do_reset == TRUE) {
init_downlink_harq_status(ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]); init_downlink_harq_status(ue->dlsch[thread_idx][gNB_id][code_word]->harq_processes[dl_harq_pid]);
......
...@@ -427,7 +427,7 @@ int main(int argc, char **argv) ...@@ -427,7 +427,7 @@ int main(int argc, char **argv)
UE->dlsch_ra[0] = new_nr_ue_dlsch(1, 1, Nsoft, 5, N_RB_DL, 0); UE->dlsch_ra[0] = new_nr_ue_dlsch(1, 1, Nsoft, 5, N_RB_DL, 0);
unsigned char harq_pid = 0; //dlsch->harq_ids[subframe]; unsigned char harq_pid = 0; //dlsch->harq_ids[subframe];
NR_gNB_DLSCH_t *dlsch = gNB->dlsch[0][0]; NR_gNB_DLSCH_t *dlsch = gNB->dlsch[0][0];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_processes[harq_pid]->pdsch_pdu.pdsch_pdu_rel15; nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &dlsch->harq_process.pdsch_pdu.pdsch_pdu_rel15;
//time_stats_t *rm_stats, *te_stats, *i_stats; //time_stats_t *rm_stats, *te_stats, *i_stats;
uint8_t is_crnti = 0, llr8_flag = 0; uint8_t is_crnti = 0, llr8_flag = 0;
unsigned int TBS = 8424; unsigned int TBS = 8424;
...@@ -519,7 +519,7 @@ int main(int argc, char **argv) ...@@ -519,7 +519,7 @@ int main(int argc, char **argv)
//if (i<16) //if (i<16)
// printf("encoder output f[%d] = %d\n",i,dlsch->harq_processes[0]->f[i]); // printf("encoder output f[%d] = %d\n",i,dlsch->harq_processes[0]->f[i]);
if (dlsch->harq_processes[0]->f[i] == 0) if (dlsch->harq_process.f[i] == 0)
modulated_input[i] = 1.0; ///sqrt(2); //QPSK modulated_input[i] = 1.0; ///sqrt(2); //QPSK
else else
modulated_input[i] = -1.0; ///sqrt(2); modulated_input[i] = -1.0; ///sqrt(2);
...@@ -547,7 +547,7 @@ int main(int argc, char **argv) ...@@ -547,7 +547,7 @@ int main(int argc, char **argv)
else else
channel_output_uncoded[i] = 0; channel_output_uncoded[i] = 0;
if (channel_output_uncoded[i] != dlsch->harq_processes[harq_pid]->f[i]) if (channel_output_uncoded[i] != dlsch->harq_process.f[i])
errors_bit_uncoded = errors_bit_uncoded + 1; errors_bit_uncoded = errors_bit_uncoded + 1;
} }
......
...@@ -146,6 +146,10 @@ int is_x2ap_enabled(void) ...@@ -146,6 +146,10 @@ int is_x2ap_enabled(void)
return 0; return 0;
} }
int8_t nr_rrc_ue_decode_NR_SIB1_Message(module_id_t module_id, uint8_t gNB_index, uint8_t *const bufferP, const uint8_t buffer_len) {
return 0;
}
// needed for some functions // needed for some functions
openair0_config_t openair0_cfg[MAX_CARDS]; openair0_config_t openair0_cfg[MAX_CARDS];
void update_ptrs_config(NR_CellGroupConfig_t *secondaryCellGroup, uint16_t *rbSize, uint8_t *mcsIndex,int8_t *ptrs_arg); void update_ptrs_config(NR_CellGroupConfig_t *secondaryCellGroup, uint16_t *rbSize, uint8_t *mcsIndex,int8_t *ptrs_arg);
...@@ -156,8 +160,7 @@ void update_dmrs_config(NR_CellGroupConfig_t *scg,PHY_VARS_NR_UE *ue, int8_t* dm ...@@ -156,8 +160,7 @@ void update_dmrs_config(NR_CellGroupConfig_t *scg,PHY_VARS_NR_UE *ue, int8_t* dm
int g_mcsIndex = -1, g_mcsTableIdx = 0, g_rbStart = -1, g_rbSize = -1; int g_mcsIndex = -1, g_mcsTableIdx = 0, g_rbStart = -1, g_rbSize = -1;
void nr_dlsim_preprocessor(module_id_t module_id, void nr_dlsim_preprocessor(module_id_t module_id,
frame_t frame, frame_t frame,
sub_frame_t slot, sub_frame_t slot) {
int num_slots_per_tdd) {
NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info; NR_UE_info_t *UE_info = &RC.nrmac[module_id]->UE_info;
AssertFatal(UE_info->num_UEs == 1, "can have only a single UE\n"); AssertFatal(UE_info->num_UEs == 1, "can have only a single UE\n");
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[0]; NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[0];
...@@ -173,15 +176,25 @@ void nr_dlsim_preprocessor(module_id_t module_id, ...@@ -173,15 +176,25 @@ void nr_dlsim_preprocessor(module_id_t module_id,
sched_ctrl->active_bwp, sched_ctrl->search_space, 1 /* dedicated */); sched_ctrl->active_bwp, sched_ctrl->search_space, 1 /* dedicated */);
sched_ctrl->cce_index = 0; sched_ctrl->cce_index = 0;
/* set "any" value for PUCCH (simulator evaluates PDSCH only) */
sched_ctrl->pucch_sched_idx = 0;
sched_ctrl->pucch_occ_idx = 0;
sched_ctrl->rbStart = g_rbStart; sched_ctrl->rbStart = g_rbStart;
sched_ctrl->rbSize = g_rbSize; sched_ctrl->rbSize = g_rbSize;
sched_ctrl->mcs = g_mcsIndex; sched_ctrl->mcs = g_mcsIndex;
sched_ctrl->time_domain_allocation = 2; sched_ctrl->time_domain_allocation = 2;
sched_ctrl->mcsTableIdx = g_mcsTableIdx; sched_ctrl->mcsTableIdx = g_mcsTableIdx;
/* the simulator assumes the HARQ PID is equal to the slot number */
sched_ctrl->dl_harq_pid = slot;
/* The scheduler uses lists to track whether a HARQ process is
* free/busy/awaiting retransmission, and updates the HARQ process states.
* However, in the simulation, we never get ack or nack for any HARQ process,
* thus the list and HARQ states don't match what the scheduler expects.
* Therefore, below lines just "repair" everything so that the scheduler
* won't remark that there is no HARQ feedback */
sched_ctrl->feedback_dl_harq.head = -1; // always overwrite feedback HARQ process
if (sched_ctrl->harq_processes[slot].round == 0) // depending on round set in simulation ...
add_front_nr_list(&sched_ctrl->available_dl_harq, slot); // ... make PID available
else
add_front_nr_list(&sched_ctrl->retrans_dl_harq, slot); // ... make PID retransmission
sched_ctrl->harq_processes[slot].is_waiting = false;
AssertFatal(sched_ctrl->rbStart >= 0, "invalid rbStart %d\n", sched_ctrl->rbStart); AssertFatal(sched_ctrl->rbStart >= 0, "invalid rbStart %d\n", sched_ctrl->rbStart);
AssertFatal(sched_ctrl->rbSize > 0, "invalid rbSize %d\n", sched_ctrl->rbSize); AssertFatal(sched_ctrl->rbSize > 0, "invalid rbSize %d\n", sched_ctrl->rbSize);
AssertFatal(sched_ctrl->mcs >= 0, "invalid sched_ctrl->mcs %d\n", sched_ctrl->mcs); AssertFatal(sched_ctrl->mcs >= 0, "invalid sched_ctrl->mcs %d\n", sched_ctrl->mcs);
...@@ -270,7 +283,7 @@ int main(int argc, char **argv) ...@@ -270,7 +283,7 @@ int main(int argc, char **argv)
uint16_t ptrsSymbPerSlot = 0; uint16_t ptrsSymbPerSlot = 0;
uint16_t rbSize = 106; uint16_t rbSize = 106;
uint8_t mcsIndex = 9; uint8_t mcsIndex = 9;
uint8_t dlsch_threads = 0;
if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0) { if ( load_configmodule(argc,argv,CONFIG_ENABLECMDLINEONLY) == 0) {
exit_fun("[NR_DLSIM] Error, configuration module init failed\n"); exit_fun("[NR_DLSIM] Error, configuration module init failed\n");
} }
...@@ -281,7 +294,7 @@ int main(int argc, char **argv) ...@@ -281,7 +294,7 @@ int main(int argc, char **argv)
FILE *scg_fd=NULL; FILE *scg_fd=NULL;
while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:e:m:w:T:U:q")) != -1) { while ((c = getopt (argc, argv, "f:hA:pf:g:i:j:n:s:S:t:x:y:z:M:N:F:GR:dPIL:Ea:b:d:e:m:w:T:U:q")) != -1) {
switch (c) { switch (c) {
case 'f': case 'f':
scg_fd = fopen(optarg,"r"); scg_fd = fopen(optarg,"r");
...@@ -448,7 +461,9 @@ int main(int argc, char **argv) ...@@ -448,7 +461,9 @@ int main(int argc, char **argv)
case 'b': case 'b':
g_rbSize = atoi(optarg); g_rbSize = atoi(optarg);
break; break;
case 'd':
dlsch_threads = atoi(optarg);
break;
case 'e': case 'e':
g_mcsIndex = atoi(optarg); g_mcsIndex = atoi(optarg);
break; break;
...@@ -519,6 +534,7 @@ int main(int argc, char **argv) ...@@ -519,6 +534,7 @@ int main(int argc, char **argv)
printf("-U Change DMRS Config, arguments list DMRS TYPE{0=A,1=B} DMRS AddPos{0:2}, e.g. -U 2 0 2 \n"); printf("-U Change DMRS Config, arguments list DMRS TYPE{0=A,1=B} DMRS AddPos{0:2}, e.g. -U 2 0 2 \n");
printf("-P Print DLSCH performances\n"); printf("-P Print DLSCH performances\n");
printf("-w Write txdata to binary file (one frame)\n"); printf("-w Write txdata to binary file (one frame)\n");
printf("-d number of dlsch threads, 0: no dlsch parallelization\n");
exit (-1); exit (-1);
break; break;
} }
...@@ -534,6 +550,7 @@ int main(int argc, char **argv) ...@@ -534,6 +550,7 @@ int main(int argc, char **argv)
if (snr1set==0) if (snr1set==0)
snr1 = snr0+10; snr1 = snr0+10;
init_dlsch_tpool(dlsch_threads);
RC.gNB = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *)); RC.gNB = (PHY_VARS_gNB**) malloc(sizeof(PHY_VARS_gNB *));
...@@ -637,6 +654,9 @@ int main(int argc, char **argv) ...@@ -637,6 +654,9 @@ int main(int argc, char **argv)
rrc_mac_config_req_gNB(0,0,1,pusch_tgt_snrx10,pucch_tgt_snrx10,NULL,1,secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity,secondaryCellGroup); rrc_mac_config_req_gNB(0,0,1,pusch_tgt_snrx10,pucch_tgt_snrx10,NULL,1,secondaryCellGroup->spCellConfig->reconfigurationWithSync->newUE_Identity,secondaryCellGroup);
phy_init_nr_gNB(gNB,0,0); phy_init_nr_gNB(gNB,0,0);
N_RB_DL = gNB->frame_parms.N_RB_DL; N_RB_DL = gNB->frame_parms.N_RB_DL;
NR_UE_info_t *UE_info = &RC.nrmac[0]->UE_info;
UE_info->num_UEs=1;
// stub to configure frame_parms // stub to configure frame_parms
// nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions); // nr_phy_config_request_sim(gNB,N_RB_DL,N_RB_DL,mu,Nid_cell,SSB_positions);
// call MAC to configure common parameters // call MAC to configure common parameters
...@@ -802,10 +822,10 @@ int main(int argc, char **argv) ...@@ -802,10 +822,10 @@ int main(int argc, char **argv)
scheduled_response.thread_id = UE_proc.thread_id; scheduled_response.thread_id = UE_proc.thread_id;
nr_ue_phy_config_request(&UE_mac->phy_config); nr_ue_phy_config_request(&UE_mac->phy_config);
NR_UE_info_t *UE_info = &RC.nrmac[0]->UE_info;
//NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels; //NR_COMMON_channels_t *cc = RC.nrmac[0]->common_channels;
snrRun = 0; snrRun = 0;
for (SNR = snr0; SNR < snr1; SNR += .2) { for (SNR = snr0; SNR < snr1; SNR += .2) {
varArray_t *table_tx=initVarArray(1000,sizeof(double)); varArray_t *table_tx=initVarArray(1000,sizeof(double));
...@@ -851,7 +871,7 @@ int main(int argc, char **argv) ...@@ -851,7 +871,7 @@ int main(int argc, char **argv)
NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid]; NR_DL_UE_HARQ_t *UE_harq_process = dlsch0->harq_processes[harq_pid];
NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0]; NR_gNB_DLSCH_t *gNB_dlsch = gNB->dlsch[0][0];
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->harq_processes[slot]->pdsch_pdu.pdsch_pdu_rel15; nfapi_nr_dl_tti_pdsch_pdu_rel15_t *rel15 = &gNB_dlsch->harq_process.pdsch_pdu.pdsch_pdu_rel15;
UE_harq_process->harq_ack.ack = 0; UE_harq_process->harq_ack.ack = 0;
round = 0; round = 0;
...@@ -867,15 +887,11 @@ int main(int argc, char **argv) ...@@ -867,15 +887,11 @@ int main(int argc, char **argv)
UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].round = round; UE_info->UE_sched_ctrl[0].harq_processes[harq_pid].round = round;
gNB->dlsch[0][0]->harq_processes[harq_pid]->round = round;
for (int i=0; i<MAX_NUM_CORESET; i++) for (int i=0; i<MAX_NUM_CORESET; i++)
gNB_mac->UE_info.num_pdcch_cand[0][i] = 0; gNB_mac->UE_info.num_pdcch_cand[0][i] = 0;
if (css_flag == 0) { if (css_flag == 0) {
const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160}; nr_schedule_ue_spec(0, frame, slot);
const NR_TDD_UL_DL_Pattern_t *tdd_pattern = &scc->tdd_UL_DL_ConfigurationCommon->pattern1;
const int num_slots_per_tdd = slots_per_frame[*scc->ssbSubcarrierSpacing] >> (7 - tdd_pattern->dl_UL_TransmissionPeriodicity);
nr_schedule_ue_spec(0, frame, slot, num_slots_per_tdd);
} else { } else {
nr_schedule_css_dlsch_phytest(0,frame,slot); nr_schedule_css_dlsch_phytest(0,frame,slot);
} }
...@@ -987,7 +1003,8 @@ int main(int argc, char **argv) ...@@ -987,7 +1003,8 @@ int main(int argc, char **argv)
phy_procedures_nrUE_RX(UE, phy_procedures_nrUE_RX(UE,
&UE_proc, &UE_proc,
0, 0,
normal_txrx); normal_txrx,
dlsch_threads);
//printf("dlsim round %d ends\n",round); //printf("dlsim round %d ends\n",round);
round++; round++;
...@@ -1019,8 +1036,8 @@ int main(int argc, char **argv) ...@@ -1019,8 +1036,8 @@ int main(int argc, char **argv)
for (i = 0; i < available_bits; i++) { for (i = 0; i < available_bits; i++) {
if(((gNB_dlsch->harq_processes[harq_pid]->f[i] == 0) && (UE_llr[i] <= 0)) || if(((gNB_dlsch->harq_process.f[i] == 0) && (UE_llr[i] <= 0)) ||
((gNB_dlsch->harq_processes[harq_pid]->f[i] == 1) && (UE_llr[i] >= 0))) ((gNB_dlsch->harq_process.f[i] == 1) && (UE_llr[i] >= 0)))
{ {
if(errors_scrambling == 0) { if(errors_scrambling == 0) {
LOG_D(PHY,"\n"); LOG_D(PHY,"\n");
...@@ -1033,7 +1050,7 @@ int main(int argc, char **argv) ...@@ -1033,7 +1050,7 @@ int main(int argc, char **argv)
for (i = 0; i < TBS; i++) { for (i = 0; i < TBS; i++) {
estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7); estimated_output_bit[i] = (UE_harq_process->b[i/8] & (1 << (i & 7))) >> (i & 7);
test_input_bit[i] = (gNB_dlsch->harq_processes[harq_pid]->b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments test_input_bit[i] = (gNB_dlsch->harq_process.b[i / 8] & (1 << (i & 7))) >> (i & 7); // Further correct for multiple segments
if (estimated_output_bit[i] != test_input_bit[i]) { if (estimated_output_bit[i] != test_input_bit[i]) {
if(errors_bit == 0) if(errors_bit == 0)
...@@ -1073,9 +1090,9 @@ int main(int argc, char **argv) ...@@ -1073,9 +1090,9 @@ int main(int argc, char **argv)
if (print_perf==1) { if (print_perf==1) {
printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))\n", printf("\ngNB TX function statistics (per %d us slot, NPRB %d, mcs %d, TBS %d, Kr %d (Zc %d))\n",
1000>>*scc->ssbSubcarrierSpacing, g_rbSize, g_mcsIndex, 1000>>*scc->ssbSubcarrierSpacing, g_rbSize, g_mcsIndex,
gNB->dlsch[0][0]->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3, gNB->dlsch[0][0]->harq_process.pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3,
gNB->dlsch[0][0]->harq_processes[0]->K, gNB->dlsch[0][0]->harq_process.K,
gNB->dlsch[0][0]->harq_processes[0]->K/((gNB->dlsch[0][0]->harq_processes[0]->pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3)>3824?22:10)); gNB->dlsch[0][0]->harq_process.K/((gNB->dlsch[0][0]->harq_process.pdsch_pdu.pdsch_pdu_rel15.TBSize[0]<<3)>3824?22:10));
printDistribution(&gNB->phy_proc_tx,table_tx,"PHY proc tx"); printDistribution(&gNB->phy_proc_tx,table_tx,"PHY proc tx");
printStatIndent2(&gNB->dlsch_encoding_stats,"DLSCH encoding time"); printStatIndent2(&gNB->dlsch_encoding_stats,"DLSCH encoding time");
printStatIndent3(&gNB->dlsch_segmentation_stats,"DLSCH segmentation time"); printStatIndent3(&gNB->dlsch_segmentation_stats,"DLSCH segmentation time");
......
...@@ -107,6 +107,10 @@ int is_x2ap_enabled(void) ...@@ -107,6 +107,10 @@ int is_x2ap_enabled(void)
return 0; return 0;
} }
int8_t nr_rrc_ue_decode_NR_SIB1_Message(module_id_t module_id, uint8_t gNB_index, uint8_t *const bufferP, const uint8_t buffer_len) {
return 0;
}
int main(int argc, char **argv){ int main(int argc, char **argv){
char c; char c;
......
...@@ -126,6 +126,10 @@ int is_x2ap_enabled(void) ...@@ -126,6 +126,10 @@ int is_x2ap_enabled(void)
return 0; return 0;
} }
int8_t nr_rrc_ue_decode_NR_SIB1_Message(module_id_t module_id, uint8_t gNB_index, uint8_t *const bufferP, const uint8_t buffer_len) {
return 0;
}
// needed for some functions // needed for some functions
uint16_t n_rnti = 0x1234; uint16_t n_rnti = 0x1234;
openair0_config_t openair0_cfg[MAX_CARDS]; openair0_config_t openair0_cfg[MAX_CARDS];
......
...@@ -399,8 +399,8 @@ typedef struct NbIoTRrcConfigurationReq_s { ...@@ -399,8 +399,8 @@ typedef struct NbIoTRrcConfigurationReq_s {
// gNB: GNB_APP -> RRC messages // gNB: GNB_APP -> RRC messages
typedef struct NRRrcConfigurationReq_s { typedef struct NRRrcConfigurationReq_s {
uint32_t cell_identity; uint64_t cell_identity;
uint16_t tac; uint32_t tac;
uint16_t mcc[PLMN_LIST_MAX_SIZE]; uint16_t mcc[PLMN_LIST_MAX_SIZE];
uint16_t mnc[PLMN_LIST_MAX_SIZE]; uint16_t mnc[PLMN_LIST_MAX_SIZE];
uint8_t mnc_digit_length[PLMN_LIST_MAX_SIZE]; uint8_t mnc_digit_length[PLMN_LIST_MAX_SIZE];
......
...@@ -39,6 +39,7 @@ ...@@ -39,6 +39,7 @@
/* cell configuration section name */ /* cell configuration section name */
#define GNB_CONFIG_STRING_GNB_LIST "gNBs" #define GNB_CONFIG_STRING_GNB_LIST "gNBs"
#define GNB_CONFIG_STRING_PDCCH_CONFIGSIB1 "pdcch_ConfigSIB1"
#define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON "servingCellConfigCommon" #define GNB_CONFIG_STRING_SERVINGCELLCONFIGCOMMON "servingCellConfigCommon"
#define GNB_CONFIG_STRING_PHYSCELLID "physCellId" #define GNB_CONFIG_STRING_PHYSCELLID "physCellId"
#define GNB_CONFIG_STRING_NTIMINGADVANCEOFFSET "n_TimingAdvanceOffset" #define GNB_CONFIG_STRING_NTIMINGADVANCEOFFSET "n_TimingAdvanceOffset"
...@@ -210,6 +211,21 @@ ...@@ -210,6 +211,21 @@
#define CARRIERBANDWIDTH_OKVALUES {11,18,24,25,31,32,38,51,52,65,66,78,79,93,106,107,121,132,133,135,160,162,189,216,217,245,264,270,273} #define CARRIERBANDWIDTH_OKVALUES {11,18,24,25,31,32,38,51,52,65,66,78,79,93,106,107,121,132,133,135,160,162,189,216,217,245,264,270,273}
/*--------------------------------------------------------------------------------------------------------------------*/
/* pdcch_ConfigSIB1 parameters */
/*--------------------------------------------------------------------------------------------------------------------*/
#define CONTROL_RESOURCE_SET_ZERO "controlResourceSetZero"
#define SEARCH_SPACE_ZERO "searchSpaceZero"
#define PDCCH_CONFIGSIB1PARAMS_DESC(pdcch_ConfigSIB1) { \
{CONTROL_RESOURCE_SET_ZERO, NULL, 0, i64ptr:&pdcch_ConfigSIB1->controlResourceSetZero, defintval:0, TYPE_INT64, 0}, \
{SEARCH_SPACE_ZERO, NULL, 0, i64ptr:&pdcch_ConfigSIB1->searchSpaceZero, defintval:0, TYPE_INT64, 0} \
}
#define CONTROL_RESOURCE_SET_ZERO_IDX 0
#define SEARCH_SPACE_ZERO_IDX 1
/*--------------------------------------------------------------------------------------------------------------------*/
/*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------*/
/* Serving Cell Config Common configuration parameters */ /* Serving Cell Config Common configuration parameters */
/* optname helpstr paramflags XXXptr defXXXval type numelt */ /* optname helpstr paramflags XXXptr defXXXval type numelt */
......
...@@ -574,6 +574,17 @@ void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc) { ...@@ -574,6 +574,17 @@ void RCconfig_NRRRC(MessageDef *msg_p, uint32_t i, gNB_RRC_INST *rrc) {
gnb_id = *(GNBParamList.paramarray[i][GNB_GNB_ID_IDX].uptr); gnb_id = *(GNBParamList.paramarray[i][GNB_GNB_ID_IDX].uptr);
} }
// pdcch_ConfigSIB1
rrc->carrier.pdcch_ConfigSIB1 = calloc(1,sizeof(NR_PDCCH_ConfigSIB1_t));
paramdef_t pdcch_ConfigSIB1[] = PDCCH_CONFIGSIB1PARAMS_DESC(rrc->carrier.pdcch_ConfigSIB1);
paramlist_def_t pdcch_ConfigSIB1ParamList = {GNB_CONFIG_STRING_PDCCH_CONFIGSIB1, NULL, 0};
sprintf(aprefix, "%s.[%i]", GNB_CONFIG_STRING_GNB_LIST, 0);
config_getlist(&pdcch_ConfigSIB1ParamList, NULL, 0, aprefix);
if (pdcch_ConfigSIB1ParamList.numelt > 0) {
sprintf(aprefix, "%s.[%i].%s.[%i]", GNB_CONFIG_STRING_GNB_LIST,0,GNB_CONFIG_STRING_PDCCH_CONFIGSIB1, 0);
config_get(pdcch_ConfigSIB1,sizeof(pdcch_ConfigSIB1)/sizeof(paramdef_t),aprefix);
}
sprintf(aprefix, "%s.[%i]", GNB_CONFIG_STRING_GNB_LIST, 0); sprintf(aprefix, "%s.[%i]", GNB_CONFIG_STRING_GNB_LIST, 0);
config_getlist(&SCCsParamList, NULL, 0, aprefix); config_getlist(&SCCsParamList, NULL, 0, aprefix);
......
...@@ -79,7 +79,6 @@ typedef enum { ...@@ -79,7 +79,6 @@ typedef enum {
#define GNB_CONFIG_STRING_ASN1_VERBOSITY_ANNOYING "annoying" #define GNB_CONFIG_STRING_ASN1_VERBOSITY_ANNOYING "annoying"
#define GNB_CONFIG_STRING_ASN1_VERBOSITY_INFO "info" #define GNB_CONFIG_STRING_ASN1_VERBOSITY_INFO "info"
/* global parameters, not under a specific section */ /* global parameters, not under a specific section */
#define GNB_CONFIG_STRING_ASN1_VERBOSITY "Asn1_verbosity" #define GNB_CONFIG_STRING_ASN1_VERBOSITY "Asn1_verbosity"
#define GNB_CONFIG_STRING_ACTIVE_GNBS "Active_gNBs" #define GNB_CONFIG_STRING_ACTIVE_GNBS "Active_gNBs"
......
...@@ -102,22 +102,22 @@ typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED; ...@@ -102,22 +102,22 @@ typedef NR_BSR_SHORT NR_BSR_SHORT_TRUNCATED;
// Long BSR for all logical channel group ID // Long BSR for all logical channel group ID
typedef struct { typedef struct {
uint8_t Buffer_size7: 8; uint8_t LcgID0: 1; // octet 1 [0]
uint8_t Buffer_size6: 8; uint8_t LcgID1: 1; // octet 1 [1]
uint8_t Buffer_size5: 8; uint8_t LcgID2: 1; // octet 1 [2]
uint8_t Buffer_size4: 8; uint8_t LcgID3: 1; // octet 1 [3]
uint8_t Buffer_size3: 8; uint8_t LcgID4: 1; // octet 1 [4]
uint8_t Buffer_size2: 8; uint8_t LcgID5: 1; // octet 1 [5]
uint8_t Buffer_size1: 8; uint8_t LcgID6: 1; // octet 1 [6]
uint8_t Buffer_size0: 8; uint8_t LcgID7: 1; // octet 1 [7]
uint8_t LcgID0: 1; uint8_t Buffer_size0: 8; // octet 2 [7:0]
uint8_t LcgID1: 1; uint8_t Buffer_size1: 8; // octet 3 [7:0]
uint8_t LcgID2: 1; uint8_t Buffer_size2: 8; // octet 4 [7:0]
uint8_t LcgID3: 1; uint8_t Buffer_size3: 8; // octet 5 [7:0]
uint8_t LcgID4: 1; uint8_t Buffer_size4: 8; // octet 6 [7:0]
uint8_t LcgID5: 1; uint8_t Buffer_size5: 8; // octet 7 [7:0]
uint8_t LcgID6: 1; uint8_t Buffer_size6: 8; // octet 8 [7:0]
uint8_t LcgID7: 1; uint8_t Buffer_size7: 8; // octet 9 [7:0]
} __attribute__ ((__packed__)) NR_BSR_LONG; } __attribute__ ((__packed__)) NR_BSR_LONG;
typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED; typedef NR_BSR_LONG NR_BSR_LONG_TRUNCATED;
......
...@@ -32,9 +32,24 @@ ...@@ -32,9 +32,24 @@
#ifndef __LAYER2_NR_MAC_COMMON_H__ #ifndef __LAYER2_NR_MAC_COMMON_H__
#define __LAYER2_NR_MAC_COMMON_H__ #define __LAYER2_NR_MAC_COMMON_H__
#include "NR_MIB.h"
#include "NR_PDSCH-Config.h" #include "NR_PDSCH-Config.h"
#include "NR_CellGroupConfig.h" #include "NR_CellGroupConfig.h"
#include "nr_mac.h" #include "nr_mac.h"
#include "openair1/PHY/impl_defs_nr.h"
#define TABLE_38213_13_1_NUM_INDEXES 15
#define TABLE_38213_13_2_NUM_INDEXES 14
#define TABLE_38213_13_3_NUM_INDEXES 9
#define TABLE_38213_13_4_NUM_INDEXES 16
#define TABLE_38213_13_5_NUM_INDEXES 9
#define TABLE_38213_13_6_NUM_INDEXES 10
#define TABLE_38213_13_7_NUM_INDEXES 12
#define TABLE_38213_13_8_NUM_INDEXES 8
#define TABLE_38213_13_9_NUM_INDEXES 4
#define TABLE_38213_13_10_NUM_INDEXES 8
#define TABLE_38213_13_11_NUM_INDEXES 16
#define TABLE_38213_13_12_NUM_INDEXES 14
// =============================================== // ===============================================
...@@ -99,6 +114,52 @@ typedef enum { ...@@ -99,6 +114,52 @@ typedef enum {
NR_RNTI_MCS_C, NR_RNTI_MCS_C,
} nr_rnti_type_t; } nr_rnti_type_t;
typedef enum subcarrier_spacing_e {
scs_15kHz = 0x1,
scs_30kHz = 0x2,
scs_60kHz = 0x4,
scs_120kHz = 0x8,
scs_240kHz = 0x16
} subcarrier_spacing_t;
typedef enum channel_bandwidth_e {
bw_5MHz = 0x1,
bw_10MHz = 0x2,
bw_20MHz = 0x4,
bw_40MHz = 0x8,
bw_80MHz = 0x16,
bw_100MHz = 0x32
} channel_bandwidth_t;
typedef enum nr_ssb_and_cset_mux_pattern_type_e {
NR_SSB_AND_CSET_MUX_PATTERN_TYPE1=1,
NR_SSB_AND_CSET_MUX_PATTERN_TYPE2,
NR_SSB_AND_CSET_MUX_PATTERN_TYPE3
} nr_ssb_and_cset_mux_pattern_type_t;
typedef enum {
SFN_C_MOD_2_EQ_0,
SFN_C_MOD_2_EQ_1,
SFN_C_IMPOSSIBLE
} SFN_C_TYPE;
typedef struct Type0_PDCCH_CSS_config_s {
int32_t num_rbs;
int32_t num_symbols;
int32_t rb_offset; // Offset from SSB RB0
uint32_t type0_pdcch_ss_mux_pattern;
uint16_t frame;
SFN_C_TYPE sfn_c;
uint32_t n_c;
uint32_t n_0;
uint32_t number_of_search_space_per_slot;
uint32_t first_symbol_index;
uint32_t search_space_duration;
uint32_t ssb_length;
uint32_t ssb_index;
uint32_t cset_start_rb;
} NR_Type0_PDCCH_CSS_config_t;
uint16_t config_bandwidth(int mu, int nb_rb, int nr_band); uint16_t config_bandwidth(int mu, int nb_rb, int nr_band);
void get_frame_type(uint16_t nr_bandP, uint8_t scs_index, lte_frame_type_t *current_type); void get_frame_type(uint16_t nr_bandP, uint8_t scs_index, lte_frame_type_t *current_type);
...@@ -115,14 +176,18 @@ int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); ...@@ -115,14 +176,18 @@ int is_nr_DL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP); int is_nr_UL_slot(NR_ServingCellConfigCommon_t *scc,slot_t slotP);
uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc, uint16_t nr_dci_size(const NR_ServingCellConfigCommon_t *scc,
NR_CellGroupConfig_t *secondaryCellGroup, const NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu_rel15_t *dci_pdu, dci_pdu_rel15_t *dci_pdu,
nr_dci_format_t format, nr_dci_format_t format,
nr_rnti_type_t rnti_type, nr_rnti_type_t rnti_type,
uint16_t N_RB, uint16_t N_RB,
int bwp_id); int bwp_id);
void find_aggregation_candidates(uint8_t *aggregation_level,
uint8_t *nr_of_candidates,
NR_SearchSpace_t *ss);
void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss, void find_monitoring_periodicity_offset_common(NR_SearchSpace_t *ss,
uint16_t *slot_period, uint16_t *slot_period,
uint16_t *offset); uint16_t *offset);
...@@ -184,6 +249,13 @@ int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmr ...@@ -184,6 +249,13 @@ int32_t get_l_prime(uint8_t duration_in_symbols, uint8_t mapping_type, pusch_dmr
uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table); uint8_t get_L_ptrs(uint8_t mcs1, uint8_t mcs2, uint8_t mcs3, uint8_t I_mcs, uint8_t mcs_table);
uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB); uint8_t get_K_ptrs(uint16_t nrb0, uint16_t nrb1, uint16_t N_RB);
int get_type0_PDCCH_CSS_config_parameters(NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config,
NR_MIB_t *mib,
uint8_t extra_bits,
uint32_t ssb_length,
uint32_t ssb_index,
uint32_t ssb_offset_point_a);
int16_t get_N_RA_RB (int delta_f_RA_PRACH,int delta_f_PUSCH); int16_t get_N_RA_RB (int delta_f_RA_PRACH,int delta_f_PUSCH);
bool set_dl_ptrs_values(NR_PTRS_DownlinkConfig_t *ptrs_config, bool set_dl_ptrs_values(NR_PTRS_DownlinkConfig_t *ptrs_config,
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -58,6 +58,19 @@ int8_t nr_ue_decode_mib( ...@@ -58,6 +58,19 @@ int8_t nr_ue_decode_mib(
void *pduP, void *pduP,
uint16_t cell_id ); uint16_t cell_id );
/**\brief decode sib1 pdu in NR_UE, from if_module dl_ind
\param module_id module id
\param cc_id component carrier id
\param gNB_index gNB index
\param sibs_mask sibs mask
\param pduP pointer to pdu
\param pdu_length length of pdu */
int8_t nr_ue_decode_sib1(module_id_t module_id,
int cc_id,
unsigned int gNB_index,
uint32_t sibs_mask,
uint8_t *pduP,
uint32_t pdu_len);
/**\brief primitive from RRC layer to MAC layer for configuration L1/L2, now supported 4 rrc messages: MIB, cell_group_config for MAC/PHY, spcell_config(serving cell config) /**\brief primitive from RRC layer to MAC layer for configuration L1/L2, now supported 4 rrc messages: MIB, cell_group_config for MAC/PHY, spcell_config(serving cell config)
\param module_id module id \param module_id module id
...@@ -125,8 +138,6 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr ...@@ -125,8 +138,6 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
int nr_ue_process_dci_indication_pdu(module_id_t module_id, int cc_id, int gNB_index, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci); int nr_ue_process_dci_indication_pdu(module_id_t module_id, int cc_id, int gNB_index, frame_t frame, int slot, fapi_nr_dci_indication_pdu_t *dci);
uint32_t get_ssb_frame(uint32_t test); uint32_t get_ssb_frame(uint32_t test);
uint32_t get_ssb_slot(uint32_t ssb_index);
uint32_t mr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe); uint32_t mr_ue_get_SR(module_id_t module_idP, int CC_id, frame_t frameP, uint8_t eNB_id, uint16_t rnti, sub_frame_t subframe);
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment