Commit f45e8bbe authored by Robert Schmidt's avatar Robert Schmidt

UL_tti_req_ahead: Create PUSCH PDU directly within nr_fill_nfapi_ul_pdu()

Use a "future" UL_tti_req structure to save in between scheduling and
reception slots. Should also work for FDD.
parent ee9268fe
dev Fix_SA_SIB1 NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_initsync_fixes NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_PUCCH_MultiUE NR_RA_cleanup NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_UE_CONFIG_REQ_FIXES NR_UE_SA NR_UE_dlsch_bugfix NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_Wireshark NR_beam_simulation NR_cleanup_PUCCH_resources NR_multiplexing_HARQ_CSI_PUCCH NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 PBCHNRTCFIX RFquality Saankhya_NRPRACH_HighSpeed add-dmrs-test benetel_config_file_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes bsr-fix bugfix-free-ra-process bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge ci-new-docker-pipeline ci-reduce-nb-vms ci-test ci_benetel_test ci_phytest ci_quectel_support ci_test_nsa_fix_quectel_nic ci_test_ra_fr2 ci_vm_resource_fix cleanup_softmodem_main detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-v3 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop_stable disable_CSI_measrep docker-improvements-2021-april docker-no-cache-option enhance-rfsim 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......@@ -322,6 +322,13 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if (scc != NULL ) {
AssertFatal((scc->ssb_PositionsInBurst->present > 0) && (scc->ssb_PositionsInBurst->present < 4), "SSB Bitmap type %d is not valid\n",scc->ssb_PositionsInBurst->present);
/* dimension UL_tti_req_ahead for number of slots in frame */
const uint8_t slots_per_frame[5] = {10, 20, 40, 80, 160};
const int n = slots_per_frame[*scc->ssbSubcarrierSpacing];
RC.nrmac[Mod_idP]->UL_tti_req_ahead[0] = calloc(n, sizeof(nfapi_nr_ul_tti_request_t));
AssertFatal(RC.nrmac[Mod_idP]->UL_tti_req_ahead[0],
"could not allocate memory for RC.nrmac[]->UL_tti_req_ahead[]\n");
LOG_I(MAC,"Configuring common parameters from NR ServingCellConfig\n");
config_common(Mod_idP,
......
......@@ -285,26 +285,34 @@ void schedule_nr_SRS(module_id_t module_idP, frame_t frameP, sub_frame_t subfram
*/
void nr_schedule_pusch(int Mod_idP,
int UE_id,
int num_slots_per_tdd,
int ul_slots,
frame_t frameP,
sub_frame_t slotP) {
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
int k = slotP + ul_slots - num_slots_per_tdd;
NR_sched_pusch *pusch = &UE_info->UE_sched_ctrl[UE_id].sched_pusch[k];
if ((pusch->active == true) && (frameP == pusch->frame) && (slotP == pusch->slot)) {
UL_tti_req->SFN = pusch->frame;
UL_tti_req->Slot = pusch->slot;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pusch_pdu = pusch->pusch_pdu;
UL_tti_req->n_pdus+=1;
memset((void *) &UE_info->UE_sched_ctrl[UE_id].sched_pusch[k],
0, sizeof(NR_sched_pusch));
void nr_schedule_pusch(int mod_id, frame_t frame, sub_frame_t slot) {
nfapi_nr_ul_tti_request_t *ul_tti_req = &RC.nrmac[mod_id]->UL_tti_req[0];
nfapi_nr_ul_tti_request_t *future_ul_tti_req =
&RC.nrmac[mod_id]->UL_tti_req_ahead[0][slot];
if (future_ul_tti_req->Slot == slot
&& future_ul_tti_req->SFN == frame
&& future_ul_tti_req->n_pdus > 0) {
LOG_D(MAC, "%4d.%2d copy %d PDUs from future_ul_tti_req\n", frame, slot, future_ul_tti_req->n_pdus);
/* the future_UL_tti_req_has data for the current frame/slot pair, copy
* everything into the "real" UL_tti_req */
ul_tti_req->SFN = future_ul_tti_req->SFN;
ul_tti_req->Slot = future_ul_tti_req->Slot;
ul_tti_req->n_pdus = future_ul_tti_req->n_pdus;
ul_tti_req->rach_present = future_ul_tti_req->rach_present;
ul_tti_req->n_ulsch = future_ul_tti_req->n_ulsch;
ul_tti_req->n_ulcch = future_ul_tti_req->n_ulcch;
ul_tti_req->n_group = future_ul_tti_req->n_group;
memcpy(ul_tti_req->pdus_list,
future_ul_tti_req->pdus_list,
ul_tti_req->n_pdus * sizeof(nfapi_nr_ul_tti_request_number_of_pdus_t));
memcpy(ul_tti_req->groups_list,
future_ul_tti_req->groups_list,
ul_tti_req->n_group * sizeof(nfapi_nr_ul_tti_request_number_of_groups_t));
future_ul_tti_req->n_pdus = 0;
future_ul_tti_req->n_ulsch = 0;
future_ul_tti_req->n_ulcch = 0;
future_ul_tti_req->n_group = 0;
}
}
......@@ -433,9 +441,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// inside
if (UE_info->active[UE_id] && slot < 10) {
nr_schedule_ulsch(module_idP, frame, slot, num_slots_per_tdd, nr_ulmix_slots, ulsch_in_slot_bitmap);
nr_schedule_pusch(module_idP, UE_id, num_slots_per_tdd, nr_ulmix_slots, frame, slot);
}
nr_schedule_pusch(module_idP, frame, slot);
if (UE_info->active[UE_id]
&& (is_xlsch_in_slot(dlsch_in_slot_bitmap, slot % num_slots_per_tdd))
......
......@@ -499,9 +499,10 @@ void nr_schedule_ulsch(module_id_t module_id,
* period, slot 8 (for K2=2, this is at slot 6 in the gNB; because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */
const int slot_idx = (slot + K2) % num_slots_per_tdd;
if (is_xlsch_in_slot(ulsch_in_slot_bitmap, slot_idx)
&& (!get_softmodem_params()->phy_test || slot_idx == 8)) {
const int sched_frame = frame + (slot + K2 >= num_slots_per_tdd);
const int sched_slot = (slot + K2) % num_slots_per_tdd;
if (is_xlsch_in_slot(ulsch_in_slot_bitmap, sched_slot)
&& (!get_softmodem_params()->phy_test || sched_slot == 8)) {
const int target_ss = NR_SearchSpace__searchSpaceType_PR_ue_Specific;
NR_SearchSpace_t *ss = get_searchspace(bwp, target_ss);
......@@ -536,15 +537,20 @@ void nr_schedule_ulsch(module_id_t module_id,
uint16_t rnti = UE_info->rnti[UE_id];
int first_ul_slot = num_slots_per_tdd - ul_slots;
NR_sched_pusch *pusch_sched = &UE_info->UE_sched_ctrl[UE_id].sched_pusch[slot+K2-first_ul_slot];
pusch_sched->frame = frame;
pusch_sched->slot = slot + K2;
pusch_sched->active = true;
LOG_D(MAC, "Scheduling UE specific PUSCH\n");
//UL_tti_req = &nr_mac->UL_tti_req[CC_id];
/* PUSCH in a later slot, but corresponding DCI now! */
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][sched_slot];
future_ul_tti_req->SFN = sched_frame;
future_ul_tti_req->Slot = sched_slot;
nfapi_nr_ul_dci_request_t *ul_dci_req = &RC.nrmac[module_id]->UL_dci_req[0];
ul_dci_req->SFN = frame;
ul_dci_req->Slot = slot;
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUSCH_PDU_TYPE;
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pusch_pdu_t);
nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu;
memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t));
future_ul_tti_req->n_pdus += 1;
LOG_D(MAC, "%4d.%2d Scheduling UE specific PUSCH\n", frame, slot);
int dci_formats[2];
if (ss->searchSpaceType->choice.ue_Specific->dci_Formats)
......@@ -554,8 +560,6 @@ void nr_schedule_ulsch(module_id_t module_id,
int rnti_types[2] = { NR_RNTI_C, 0 };
nfapi_nr_pusch_pdu_t *pusch_pdu = &pusch_sched->pusch_pdu;
memset(pusch_pdu,0,sizeof(nfapi_nr_pusch_pdu_t));
//Resource Allocation in time domain
const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength;
int StartSymbolIndex, NrOfSymbols;
......@@ -709,7 +713,7 @@ void nr_schedule_ulsch(module_id_t module_id,
pusch_pdu->pusch_data.rv_index = nr_rv_round_map[cur_harq->round];
cur_harq->state = ACTIVE_SCHED;
cur_harq->last_tx_slot = pusch_sched->slot;
cur_harq->last_tx_slot = sched_slot;
uint8_t num_dmrs_symb = 0;
for(int i = pusch_pdu->start_symbol_index; i < pusch_pdu->start_symbol_index + pusch_pdu->nr_of_symbols; i++)
......
......@@ -178,12 +178,7 @@ void config_uldci(NR_BWP_Uplink_t *ubwp,
int time_domain_assignment, uint8_t tpc,
int n_ubwp, int bwp_id);
void nr_schedule_pusch(int Mod_idP,
int UE_id,
int num_slots_per_tdd,
int ul_slots,
frame_t frameP,
sub_frame_t slotP);
void nr_schedule_pusch(int Mod_idP, frame_t frameP, sub_frame_t slotP);
void nr_schedule_pucch(int Mod_idP,
int UE_id,
......
......@@ -469,6 +469,9 @@ typedef struct gNB_MAC_INST_s {
nfapi_nr_dl_tti_request_t DL_req[NFAPI_CC_MAX];
/// NFAPI UL TTI Request Structure (this is from the new SCF specs)
nfapi_nr_ul_tti_request_t UL_tti_req[NFAPI_CC_MAX];
/// NFAPI UL TTI Request Structure for future TTIs, dynamically allocated
/// because length depends on number of slots
nfapi_nr_ul_tti_request_t *UL_tti_req_ahead[NFAPI_CC_MAX];
/// NFAPI HI/DCI0 Config Request Structure
nfapi_nr_ul_dci_request_t UL_dci_req[NFAPI_CC_MAX];
/// NFAPI DL PDU structure
......
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