The system is: Linux - 3.17.0-031700-lowlatency - x86_64
Compiling the C compiler identification source file "CMakeCCompilerId.c" succeeded.
Compiler: /usr/bin/cc
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Id flags:
The output was:
0
Compilation of the C compiler identification source "CMakeCCompilerId.c" produced "a.out"
The C compiler identification is GNU, found in "/home/papillon/openairinterface5g/targets/ARCH/LMSSDR/USERSPACE/LIB/Si5351C/build/CMakeFiles/2.8.12.2/CompilerIdC/a.out"
Compiling the CXX compiler identification source file "CMakeCXXCompilerId.cpp" succeeded.
Compiler: /usr/bin/c++
Build flags:
Id flags:
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Compilation of the CXX compiler identification source "CMakeCXXCompilerId.cpp" produced "a.out"
The CXX compiler identification is GNU, found in "/home/papillon/openairinterface5g/targets/ARCH/LMSSDR/USERSPACE/LIB/Si5351C/build/CMakeFiles/2.8.12.2/CompilerIdCXX/a.out"
Determining if the C compiler works passed with the following output:
conststructLMS7ParameterLML2_FIDM={0x0023,5,5,0,"LML2_FIDM","Frame start ID selection for Port 2 when LML_MODE2 = 0"};
conststructLMS7ParameterLML2_TXNRXIQ={0x0023,4,4,1,"LML2_TXNRXIQ","TXIQ/RXIQ mode selection for Port 2 when LML_MODE2 = 0"};
conststructLMS7ParameterLML2_MODE={0x0023,3,3,1,"LML2_MODE","Mode of LimeLight Port 2"};
conststructLMS7ParameterLML1_FIDM={0x0023,2,2,0,"LML1_FIDM","Frame start ID selection for Port 1 when LML_MODE1 = 0"};
conststructLMS7ParameterLML1_TXNRXIQ={0x0023,1,1,0,"LML1_TXNRXIQ","TXIQ/RXIQ mode selection for Port 1 when LML_MODE1 = 0"};
conststructLMS7ParameterLML1_MODE={0x0023,0,0,1,"LML1_MODE","Mode of LimeLight Port 1"};
conststructLMS7ParameterLML1_S3S={0x0024,15,14,3,"LML1_S3S","Sample source in position 3, when Port 1 is RF2BB"};
conststructLMS7ParameterLML1_S2S={0x0024,13,12,2,"LML1_S2S","Sample source in position 2, when Port 1 is RF2BB"};
conststructLMS7ParameterLML1_S1S={0x0024,11,10,1,"LML1_S1S","Sample source in position 1, when Port 1 is RF2BB"};
conststructLMS7ParameterLML1_S0S={0x0024,9,8,0,"LML1_S0S","Sample source in position 0, when Port 1 is RF2BB"};
conststructLMS7ParameterLML1_BQP={0x0024,7,6,3,"LML1_BQP","BQ sample position in frame, when Port 1 is BB2RF"};
conststructLMS7ParameterLML1_BIP={0x0024,5,4,2,"LML1_BIP","BI sample position in frame, when Port 1 is BB2RF"};
conststructLMS7ParameterLML1_AQP={0x0024,3,2,1,"LML1_AQP","AQ sample position in frame, when Port 1 is BB2RF"};
conststructLMS7ParameterLML1_AIP={0x0024,1,0,0,"LML1_AIP","AI sample position in frame, when Port 1 is BB2RF"};
conststructLMS7ParameterLML1_BB2RF_PST={0x0025,15,8,1,"LML1_BB2RF_PST","Number of clock cycles to wait before data drive stop after burst stop is detected in JESD207 mode on Port 1 and Port 1 BB2RF"};
conststructLMS7ParameterLML1_BB2RF_PRE={0x0025,7,0,1,"LML1_BB2RF_PRE","Number of clock cycles to wait before data drive start after burst start is detected in JESD207 mode on Port 1 and Port 1 BB2RF"};
conststructLMS7ParameterLML1_RF2BB_PST={0x0026,15,8,1,"LML1_RF2BB_PST","Number of clock cycles to wait before data capture stop after burst stop is detected in JESD207 mode on Port 1 and Port 1 is RF2BB"};
conststructLMS7ParameterLML1_RF2BB_PRE={0x0026,7,0,1,"LML1_RF2BB_PRE","Number of clock cycles to wait before data capture start after burst start is detected in JESD207 mode on Port 1 and Port 1 RF2BB"};
conststructLMS7ParameterLML2_S3S={0x0027,15,14,3,"LML2_S3S","Sample source in position 3, when Port 2 is RF2BB"};
conststructLMS7ParameterLML2_S2S={0x0027,13,12,2,"LML2_S2S","Sample source in position 2, when Port 2 is RF2BB"};
conststructLMS7ParameterLML2_S1S={0x0027,11,10,1,"LML2_S1S","Sample source in position 1, when Port 2 is RF2BB"};
conststructLMS7ParameterLML2_S0S={0x0027,9,8,0,"LML2_S0S","Sample source in position 0, when Port 2 is RF2BB"};
conststructLMS7ParameterLML2_BQP={0x0027,7,6,3,"LML2_BQP","BQ sample position in frame, when Port 2 is BB2RF"};
conststructLMS7ParameterLML2_BIP={0x0027,5,4,2,"LML2_BIP","BI sample position in frame, when Port 2 is BB2RF"};
conststructLMS7ParameterLML2_AQP={0x0027,3,2,1,"LML2_AQP","AQ sample position in frame, when Port 2 is BB2RF"};
conststructLMS7ParameterLML2_AIP={0x0027,1,0,0,"LML2_AIP","AI sample position in frame, when Port 2 is BB2RF"};
conststructLMS7ParameterLML2_BB2RF_PST={0x0028,15,8,1,"LML2_BB2RF_PST","Number of clock cycles to wait before data drive stop after burst stop is detected in JESD207 mode on Port 2 and Port 2 BB2RF"};
conststructLMS7ParameterLML2_BB2RF_PRE={0x0028,7,0,1,"LML2_BB2RF_PRE","Number of clock cycles to wait before data drive start after burst start is detected in JESD207 mode on Port 2 and Port 2 BB2RF"};
conststructLMS7ParameterLML2_RF2BB_PST={0x0029,15,8,1,"LML2_RF2BB_PST","Number of clock cycles to wait before data capture stop after burst stop is detected in JESD207 mode on Port 2 and Port 2 RF2BB"};
conststructLMS7ParameterLML2_RF2BB_PRE={0x0029,7,0,1,"LML2_RF2BB_PRE","Number of clock cycles to wait before data capture start after burst start is detected in JESD207 mode on Port 2 and Port 2 RF2BB"};
conststructLMS7ParameterTXTSPCLKA_DIV={0x002C,15,8,255,"TXTSPCLKA_DIV","TxTSP clock divider, used to produce MCLK(1/2). Clock division ratio is 2(TXTSPCLKA_DIV + 1)"};
conststructLMS7ParameterRXTSPCLKA_DIV={0x002C,7,0,255,"RXTSPCLKA_DIV","RxTSP clock divider, used to produce MCLK(1/2). Clock division ratio is 2(RXTSPCLKA_DIV + 1)"};
conststructLMS7ParameterMIMO_SISO={0x002E,15,15,0,"MIMO_SISO","MIMO channel B enable control"};
conststructLMS7ParameterISEL_DAC_AFE={0x0082,15,13,4,"ISEL_DAC_AFE","Controls the peak current of the DAC output current"};
conststructLMS7ParameterMODE_INTERLEAVE_AFE={0x0082,12,12,0,"MODE_INTERLEAVE_AFE","time interleaves the two ADCs into one ADC"};
conststructLMS7ParameterMUX_AFE_1={0x0082,11,10,0,"MUX_AFE_1","Controls the MUX at the input of the ADC channel 1"};
conststructLMS7ParameterMUX_AFE_2={0x0082,9,8,0,"MUX_AFE_2","Controls the MUX at the input of the ADC channel 2"};
conststructLMS7ParameterPD_AFE={0x0082,5,5,0,"PD_AFE","Power down control for the AFE current mirror in BIAS_TOP"};
conststructLMS7ParameterPD_RX_AFE1={0x0082,4,4,0,"PD_RX_AFE1","Power down control for the ADC of channel 1"};
conststructLMS7ParameterPD_RX_AFE2={0x0082,3,3,1,"PD_RX_AFE2","Power down control for the ADC of channel 2"};
conststructLMS7ParameterPD_TX_AFE1={0x0082,2,2,0,"PD_TX_AFE1","Power down control for the DAC of channel 1"};
conststructLMS7ParameterPD_TX_AFE2={0x0082,1,1,1,"PD_TX_AFE2","Power down control for the DAC of channel 2"};
conststructLMS7ParameterEN_G_AFE={0x0082,0,0,1,"EN_G_AFE","Enable control for all the AFE power downs"};
conststructLMS7ParameterMUX_BIAS_OUT={0x0084,12,11,0,"MUX_BIAS_OUT","Test mode of the BIAS_TOP"};
conststructLMS7ParameterRP_CALIB_BIAS={0x0084,10,6,16,"RP_CALIB_BIAS","Calibration code for rppolywo. This code is set by the calibration algorithm: BIAS_RPPOLY_calibration"};
conststructLMS7ParameterPD_FRP_BIAS={0x0084,4,4,0,"PD_FRP_BIAS","Power down signal for Fix/RP block"};
conststructLMS7ParameterPD_F_BIAS={0x0084,3,3,0,"PD_F_BIAS","Power down signal for Fix"};
conststructLMS7ParameterPD_PTRP_BIAS={0x0084,2,2,0,"PD_PTRP_BIAS","Power down signal for PTAT/RP block"};
conststructLMS7ParameterPD_PT_BIAS={0x0084,1,1,0,"PD_PT_BIAS","Power down signal for PTAT block"};
conststructLMS7ParameterPD_BIAS_MASTER={0x0084,0,0,0,"PD_BIAS_MASTER","Enable signal for central bias block"};
conststructLMS7ParameterSLFB_XBUF_RX={0x0085,8,8,0,"SLFB_XBUF_RX","Self biasing digital contol SLFB_XBUF_RX"};
conststructLMS7ParameterSLFB_XBUF_TX={0x0085,7,7,0,"SLFB_XBUF_TX","Self biasing digital contol SLFB_XBUF_TX"};
conststructLMS7ParameterBYP_XBUF_RX={0x0085,6,6,0,"BYP_XBUF_RX","Shorts the Input 3.3V buffer in XBUF"};
conststructLMS7ParameterBYP_XBUF_TX={0x0085,5,5,0,"BYP_XBUF_TX","Shorts the Input 3.3V buffer in XBUF"};
conststructLMS7ParameterEN_OUT2_XBUF_TX={0x0085,4,4,0,"EN_OUT2_XBUF_TX","Enables the 2nd output of TX XBUF. This 2nd buffer goes to XBUF_RX. This should be active when only 1 XBUF is to be used"};
conststructLMS7ParameterEN_TBUFIN_XBUF_RX={0x0085,3,3,0,"EN_TBUFIN_XBUF_RX","Disables the input from the external XOSC and buffers the 2nd input signal (from TX XBUF 2nd output) to the RX. This should be active when only 1 XBUF is to be used"};
conststructLMS7ParameterPD_XBUF_RX={0x0085,2,2,0,"PD_XBUF_RX","Power down signal PD_XBUF_RX"};
conststructLMS7ParameterPD_XBUF_TX={0x0085,1,1,0,"PD_XBUF_TX","Power down signal PD_XBUF_TX"};
conststructLMS7ParameterEN_G_XBUF={0x0085,0,0,1,"EN_G_XBUF","Enable control for all the XBUF power downs"};
conststructLMS7ParameterSPDUP_VCO_CGEN={0x0086,15,15,0,"SPDUP_VCO_CGEN","Bypasses the noise filter resistor for fast setlling time. It should be connected to a 1us pulse"};
conststructLMS7ParameterRESET_N_CGEN={0x0086,14,14,1,"RESET_N_CGEN","A pulse should be used in the start-up to reset ( 1-normal operation)"};
conststructLMS7ParameterEN_ADCCLKH_CLKGN={0x0086,11,11,1,"EN_ADCCLKH_CLKGN","Selects if F_CLKH or F_CLKL is connected to FCLK_ADC"};
conststructLMS7ParameterEN_COARSE_CKLGEN={0x0086,10,10,0,"EN_COARSE_CKLGEN","Enable signal for coarse tuning block"};
conststructLMS7ParameterEN_INTONLY_SDM_CGEN={0x0086,9,9,0,"EN_INTONLY_SDM_CGEN","Enables INTEGER-N mode of the SX "};
conststructLMS7ParameterEN_SDM_CLK_CGEN={0x0086,8,8,1,"EN_SDM_CLK_CGEN","Enables/Disables SDM clock. In INT-N mode or for noise testing, SDM clock can be disabled"};
conststructLMS7ParameterPD_CP_CGEN={0x0086,6,6,0,"PD_CP_CGEN","Power down for Charge Pump"};
conststructLMS7ParameterPD_FDIV_FB_CGEN={0x0086,5,5,0,"PD_FDIV_FB_CGEN","Power down for feedback frequency divider"};
conststructLMS7ParameterPD_FDIV_O_CGEN={0x0086,4,4,0,"PD_FDIV_O_CGEN","Power down for forward frequency divider of the CGEN block"};
conststructLMS7ParameterPD_SDM_CGEN={0x0086,3,3,0,"PD_SDM_CGEN","Power down for SDM"};
conststructLMS7ParameterPD_VCO_CGEN={0x0086,2,2,0,"PD_VCO_CGEN","Power down for VCO"};
conststructLMS7ParameterPD_VCO_COMP_CGEN={0x0086,1,1,0,"PD_VCO_COMP_CGEN","Power down for VCO comparator"};
conststructLMS7ParameterEN_G_CGEN={0x0086,0,0,1,"EN_G_CGEN","Enable control for all the CGEN power downs"};
conststructLMS7ParameterREV_SDMCLK_CGEN={0x0089,15,15,0,"REV_SDMCLK_CGEN","Reverses the SDM clock"};
conststructLMS7ParameterSEL_SDMCLK_CGEN={0x0089,14,14,0,"SEL_SDMCLK_CGEN","Selects between the feedback divider output and Fref for SDM"};
conststructLMS7ParameterSX_DITHER_EN_CGEN={0x0089,13,13,0,"SX_DITHER_EN_CGEN","Enabled dithering in SDM"};
conststructLMS7ParameterCLKH_OV_CLKL_CGEN={0x0089,12,11,0,"CLKH_OV_CLKL_CGEN","FCLKL here is ADC clock. FCLKH is the clock to the DAC and if no division is added to the ADC as well"};
conststructLMS7ParameterREV_CLKADC_CGEN={0x008A,13,13,0,"REV_CLKADC_CGEN","Inverts the clock F_CLKL"};
conststructLMS7ParameterREVPH_PFD_CGEN={0x008A,12,12,0,"REVPH_PFD_CGEN","Reverse the pulses of PFD. It can be used to reverse the polarity of the PLL loop (positive feedback to negative feedback)"};
conststructLMS7ParameterIOFFSET_CP_CGEN={0x008A,11,6,20,"IOFFSET_CP_CGEN","Scales the offset current of the charge pump, 0-->63. This current is used in Fran-N mode to create an offset in the CP response and avoide the non-linear section"};
conststructLMS7ParameterIPULSE_CP_CGEN={0x008A,5,0,20,"IPULSE_CP_CGEN","Scales the pulse current of the charge pump"};
conststructLMS7ParameterICT_VCO_CGEN={0x008B,13,9,16,"ICT_VCO_CGEN","Scales the VCO bias current from 0 to 2.5xInom"};
conststructLMS7ParameterCP2_CGEN={0x008C,11,8,6,"CP2_CGEN","Controls the value of CP2 (cap from CP output to GND) in the PLL filter"};
conststructLMS7ParameterCP3_CGEN={0x008C,7,4,7,"CP3_CGEN","Controls the value of CP3 (cap from VCO Vtune input to GND) in the PLL filter"};
conststructLMS7ParameterCZ_CGEN={0x008C,3,0,11,"CZ_CGEN","Controls the value of CZ (Zero capacitor) in the PLL filter"};
conststructLMS7ParameterEN_LDO_DIG={0x0092,15,15,0,"EN_LDO_DIG","Enables the LDO"};
conststructLMS7ParameterEN_LDO_DIGGN={0x0092,14,14,0,"EN_LDO_DIGGN","Enables the LDO"};
conststructLMS7ParameterEN_LDO_DIGSXR={0x0092,13,13,0,"EN_LDO_DIGSXR","Enables the LDO"};
conststructLMS7ParameterEN_LDO_DIGSXT={0x0092,12,12,0,"EN_LDO_DIGSXT","Enables the LDO"};
conststructLMS7ParameterEN_LDO_DIVGN={0x0092,11,11,0,"EN_LDO_DIVGN","Enables the LDO"};
conststructLMS7ParameterEN_LDO_DIVSXR={0x0092,10,10,0,"EN_LDO_DIVSXR","Enables the LDO"};
conststructLMS7ParameterEN_LDO_DIVSXT={0x0092,9,9,0,"EN_LDO_DIVSXT","Enables the LDO"};
conststructLMS7ParameterEN_LDO_LNA12={0x0092,8,8,0,"EN_LDO_LNA12","Enables the LDO"};
conststructLMS7ParameterEN_LDO_LNA14={0x0092,7,7,0,"EN_LDO_LNA14","Enables the LDO"};
conststructLMS7ParameterEN_LDO_MXRFE={0x0092,6,6,0,"EN_LDO_MXRFE","Enables the LDO"};
conststructLMS7ParameterEN_LDO_RBB={0x0092,5,5,0,"EN_LDO_RBB","Enables the LDO"};
conststructLMS7ParameterEN_LDO_RXBUF={0x0092,4,4,0,"EN_LDO_RXBUF","Enables the LDO"};
conststructLMS7ParameterEN_LDO_TBB={0x0092,3,3,0,"EN_LDO_TBB","Enables the LDO"};
conststructLMS7ParameterEN_LDO_TIA12={0x0092,2,2,0,"EN_LDO_TIA12","Enables the LDO"};
conststructLMS7ParameterEN_LDO_TIA14={0x0092,1,1,0,"EN_LDO_TIA14","Enables the LDO"};
conststructLMS7ParameterEN_G_LDO={0x0092,0,0,1,"EN_G_LDO","Enable control for all the LDO power downs"};
conststructLMS7ParameterEN_LOADIMP_LDO_TLOB={0x0093,15,15,0,"EN_LOADIMP_LDO_TLOB","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_TPAD={0x0093,14,14,0,"EN_LOADIMP_LDO_TPAD","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_TXBUF={0x0093,13,13,0,"EN_LOADIMP_LDO_TXBUF","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_VCOGN={0x0093,12,12,0,"EN_LOADIMP_LDO_VCOGN","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_VCOSXR={0x0093,11,11,0,"EN_LOADIMP_LDO_VCOSXR","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_VCOSXT={0x0093,10,10,0,"EN_LOADIMP_LDO_VCOSXT","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LDO_AFE={0x0093,9,9,0,"EN_LDO_AFE","Enables the LDO"};
conststructLMS7ParameterEN_LDO_CPGN={0x0093,8,8,0,"EN_LDO_CPGN","Enables the LDO"};
conststructLMS7ParameterEN_LDO_CPSXR={0x0093,7,7,0,"EN_LDO_CPSXR","Enables the LDO"};
conststructLMS7ParameterEN_LDO_TLOB={0x0093,6,6,0,"EN_LDO_TLOB","Enables the LDO"};
conststructLMS7ParameterEN_LDO_TPAD={0x0093,5,5,0,"EN_LDO_TPAD","Enables the LDO"};
conststructLMS7ParameterEN_LDO_TXBUF={0x0093,4,4,0,"EN_LDO_TXBUF","Enables the LDO"};
conststructLMS7ParameterEN_LDO_VCOGN={0x0093,3,3,0,"EN_LDO_VCOGN","Enables the LDO"};
conststructLMS7ParameterEN_LDO_VCOSXR={0x0093,2,2,0,"EN_LDO_VCOSXR","Enables the LDO"};
conststructLMS7ParameterEN_LDO_VCOSXT={0x0093,1,1,0,"EN_LDO_VCOSXT","Enables the LDO"};
conststructLMS7ParameterEN_LDO_CPSXT={0x0093,0,0,0,"EN_LDO_CPSXT","Enables the LDO"};
conststructLMS7ParameterEN_LOADIMP_LDO_CPSXT={0x0094,15,15,0,"EN_LOADIMP_LDO_CPSXT","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIG={0x0094,14,14,0,"EN_LOADIMP_LDO_DIG","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIGGN={0x0094,13,13,0,"EN_LOADIMP_LDO_DIGGN","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIGSXR={0x0094,12,12,0,"EN_LOADIMP_LDO_DIGSXR","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIGSXT={0x0094,11,11,0,"EN_LOADIMP_LDO_DIGSXT","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIVGN={0x0094,10,10,0,"EN_LOADIMP_LDO_DIVGN","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIVSXR={0x0094,9,9,0,"EN_LOADIMP_LDO_DIVSXR","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIVSXT={0x0094,8,8,0,"EN_LOADIMP_LDO_DIVSXT","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_LNA12={0x0094,7,7,0,"EN_LOADIMP_LDO_LNA12","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_LNA14={0x0094,6,6,0,"EN_LOADIMP_LDO_LNA14","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_MXRFE={0x0094,5,5,0,"EN_LOADIMP_LDO_MXRFE","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_RBB={0x0094,4,4,0,"EN_LOADIMP_LDO_RBB","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_RXBUF={0x0094,3,3,0,"EN_LOADIMP_LDO_RXBUF","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_TBB={0x0094,2,2,0,"EN_LOADIMP_LDO_TBB","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_TIA12={0x0094,1,1,0,"EN_LOADIMP_LDO_TIA12","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_TIA14={0x0094,0,0,0,"EN_LOADIMP_LDO_TIA14","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterBYP_LDO_TBB={0x0095,15,15,0,"BYP_LDO_TBB","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_TIA12={0x0095,14,14,0,"BYP_LDO_TIA12","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_TIA14={0x0095,13,13,0,"BYP_LDO_TIA14","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_TLOB={0x0095,12,12,0,"BYP_LDO_TLOB","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_TPAD={0x0095,11,11,0,"BYP_LDO_TPAD","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_TXBUF={0x0095,10,10,0,"BYP_LDO_TXBUF","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_VCOGN={0x0095,9,9,0,"BYP_LDO_VCOGN","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_VCOSXR={0x0095,8,8,0,"BYP_LDO_VCOSXR","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_VCOSXT={0x0095,7,7,0,"BYP_LDO_VCOSXT","Bypass signal for the LDO"};
conststructLMS7ParameterEN_LOADIMP_LDO_AFE={0x0095,2,2,0,"EN_LOADIMP_LDO_AFE","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_CPGN={0x0095,1,1,0,"EN_LOADIMP_LDO_CPGN","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_CPSXR={0x0095,0,0,0,"EN_LOADIMP_LDO_CPSXR","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterBYP_LDO_AFE={0x0096,15,15,0,"BYP_LDO_AFE","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_CPGN={0x0096,14,14,0,"BYP_LDO_CPGN","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_CPSXR={0x0096,13,13,0,"BYP_LDO_CPSXR","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_CPSXT={0x0096,12,12,0,"BYP_LDO_CPSXT","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIG={0x0096,11,11,0,"BYP_LDO_DIG","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIGGN={0x0096,10,10,0,"BYP_LDO_DIGGN","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIGSXR={0x0096,9,9,0,"BYP_LDO_DIGSXR","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIGSXT={0x0096,8,8,0,"BYP_LDO_DIGSXT","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIVGN={0x0096,7,7,0,"BYP_LDO_DIVGN","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIVSXR={0x0096,6,6,0,"BYP_LDO_DIVSXR","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIVSXT={0x0096,5,5,0,"BYP_LDO_DIVSXT","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_LNA12={0x0096,4,4,0,"BYP_LDO_LNA12","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_LNA14={0x0096,3,3,0,"BYP_LDO_LNA14","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_MXRFE={0x0096,2,2,0,"BYP_LDO_MXRFE","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_RBB={0x0096,1,1,0,"BYP_LDO_RBB","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_RXBUF={0x0096,0,0,0,"BYP_LDO_RXBUF","Bypass signal for the LDO"};
conststructLMS7ParameterSPDUP_LDO_DIVSXR={0x0097,15,15,0,"SPDUP_LDO_DIVSXR","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIVSXT={0x0097,14,14,0,"SPDUP_LDO_DIVSXT","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_LNA12={0x0097,13,13,0,"SPDUP_LDO_LNA12","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_LNA14={0x0097,12,12,0,"SPDUP_LDO_LNA14","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_MXRFE={0x0097,11,11,0,"SPDUP_LDO_MXRFE","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_RBB={0x0097,10,10,0,"SPDUP_LDO_RBB","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_RXBUF={0x0097,9,9,0,"SPDUP_LDO_RXBUF","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_TBB={0x0097,8,8,0,"SPDUP_LDO_TBB","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_TIA12={0x0097,7,7,0,"SPDUP_LDO_TIA12","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_TIA14={0x0097,6,6,0,"SPDUP_LDO_TIA14","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_TLOB={0x0097,5,5,0,"SPDUP_LDO_TLOB","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_TPAD={0x0097,4,4,0,"SPDUP_LDO_TPAD","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_TXBUF={0x0097,3,3,0,"SPDUP_LDO_TXBUF","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_VCOGN={0x0097,2,2,0,"SPDUP_LDO_VCOGN","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_VCOSXR={0x0097,1,1,0,"SPDUP_LDO_VCOSXR","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_VCOSXT={0x0097,0,0,0,"SPDUP_LDO_VCOSXT","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_AFE={0x0098,8,8,0,"SPDUP_LDO_AFE","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_CPGN={0x0098,7,7,0,"SPDUP_LDO_CPGN","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_CPSXR={0x0098,6,6,0,"SPDUP_LDO_CPSXR","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_CPSXT={0x0098,5,5,0,"SPDUP_LDO_CPSXT","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIG={0x0098,4,4,0,"SPDUP_LDO_DIG","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIGGN={0x0098,3,3,0,"SPDUP_LDO_DIGGN","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIGSXR={0x0098,2,2,0,"SPDUP_LDO_DIGSXR","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIGSXT={0x0098,1,1,0,"SPDUP_LDO_DIGSXT","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIVGN={0x0098,0,0,0,"SPDUP_LDO_DIVGN","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterRDIV_VCOSXR={0x0099,15,8,101,"RDIV_VCOSXR","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_VCOSXT={0x0099,7,0,101,"RDIV_VCOSXT","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_TXBUF={0x009A,15,8,101,"RDIV_TXBUF","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_VCOGN={0x009A,7,0,140,"RDIV_VCOGN","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_TLOB={0x009B,15,8,101,"RDIV_TLOB","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_TPAD={0x009B,7,0,101,"RDIV_TPAD","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_TIA12={0x009C,15,8,101,"RDIV_TIA12","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_TIA14={0x009C,7,0,140,"RDIV_TIA14","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_RXBUF={0x009D,15,8,101,"RDIV_RXBUF","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_TBB={0x009D,7,0,101,"RDIV_TBB","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_MXRFE={0x009E,15,8,101,"RDIV_MXRFE","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_RBB={0x009E,7,0,140,"RDIV_RBB","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_LNA12={0x009F,15,8,101,"RDIV_LNA12","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_LNA14={0x009F,7,0,140,"RDIV_LNA14","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIVSXR={0x00A0,15,8,101,"RDIV_DIVSXR","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIVSXT={0x00A0,7,0,101,"RDIV_DIVSXT","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIGSXT={0x00A1,15,8,101,"RDIV_DIGSXT","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIVGN={0x00A1,7,0,101,"RDIV_DIVGN","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIGGN={0x00A2,15,8,101,"RDIV_DIGGN","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIGSXR={0x00A2,7,0,101,"RDIV_DIGSXR","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_CPSXT={0x00A3,15,8,101,"RDIV_CPSXT","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIG={0x00A3,7,0,101,"RDIV_DIG","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_CPGN={0x00A4,15,8,101,"RDIV_CPGN","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_CPSXR={0x00A4,7,0,101,"RDIV_CPSXR","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_SPIBUF={0x00A5,15,8,101,"RDIV_SPIBUF","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_AFE={0x00A5,7,0,101,"RDIV_AFE","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterSPDUP_LDO_SPIBUF={0x00A6,12,12,0,"SPDUP_LDO_SPIBUF","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIGIp2={0x00A6,11,11,0,"SPDUP_LDO_DIGIp2","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterSPDUP_LDO_DIGIp1={0x00A6,10,10,0,"SPDUP_LDO_DIGIp1","Short the noise filter resistor to speed up the settling time"};
conststructLMS7ParameterBYP_LDO_SPIBUF={0x00A6,9,9,0,"BYP_LDO_SPIBUF","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIGIp2={0x00A6,8,8,0,"BYP_LDO_DIGIp2","Bypass signal for the LDO"};
conststructLMS7ParameterBYP_LDO_DIGIp1={0x00A6,7,7,0,"BYP_LDO_DIGIp1","Bypass signal for the LDO"};
conststructLMS7ParameterEN_LOADIMP_LDO_SPIBUF={0x00A6,6,6,0,"EN_LOADIMP_LDO_SPIBUF","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIGIp2={0x00A6,5,5,0,"EN_LOADIMP_LDO_DIGIp2","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterEN_LOADIMP_LDO_DIGIp1={0x00A6,4,4,0,"EN_LOADIMP_LDO_DIGIp1","Enables the load dependent bias to optimize the load regulation"};
conststructLMS7ParameterPD_LDO_SPIBUF={0x00A6,3,3,1,"PD_LDO_SPIBUF","Enables the LDO"};
conststructLMS7ParameterPD_LDO_DIGIp2={0x00A6,2,2,1,"PD_LDO_DIGIp2","Enables the LDO"};
conststructLMS7ParameterPD_LDO_DIGIp1={0x00A6,1,1,1,"PD_LDO_DIGIp1","Enables the LDO"};
conststructLMS7ParameterEN_G_LDOP={0x00A6,0,0,1,"EN_G_LDOP","Enable control for all the LDO power downs"};
conststructLMS7ParameterRDIV_DIGIp2={0x00A7,15,8,101,"RDIV_DIGIp2","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterRDIV_DIGIp1={0x00A7,7,0,101,"RDIV_DIGIp1","Controls the output voltage of the LDO by setting the resistive voltage divider ratio"};
conststructLMS7ParameterCDS_TXBTSP={0x00AE,15,14,0,"CDS_TXBTSP","TX TSP B clock delay"};
conststructLMS7ParameterCDS_TXATSP={0x00AE,13,12,0,"CDS_TXATSP","TX TSP A clock delay"};
conststructLMS7ParameterCDS_RXBTSP={0x00AE,11,10,0,"CDS_RXBTSP","RX TSP B clock delay"};
conststructLMS7ParameterCDS_RXATSP={0x00AE,9,8,0,"CDS_RXATSP","RX TSP A clock delay"};
conststructLMS7ParameterCDS_TXBLML={0x00AE,7,6,0,"CDS_TXBLML","TX LML B clock delay"};
conststructLMS7ParameterCDS_TXALML={0x00AE,5,4,0,"CDS_TXALML","TX LML A clock delay"};
conststructLMS7ParameterCDS_RXBLML={0x00AE,3,2,0,"CDS_RXBLML","RX LML B clock delay"};
conststructLMS7ParameterCDS_RXALML={0x00AE,1,0,0,"CDS_RXALML","RX LML A clock delay"};
conststructLMS7ParameterEN_LOWBWLOMX_TMX_TRF={0x0100,15,15,0,"EN_LOWBWLOMX_TMX_TRF","Controls the high pass pole frequency of the RC biasing the gate of the mixer switches"};
conststructLMS7ParameterEN_NEXTTX_TRF={0x0100,14,14,0,"EN_NEXTTX_TRF","Enables the daisy change LO buffer going from TRF_1 to TRF2"};
conststructLMS7ParameterEN_AMPHF_PDET_TRF={0x0100,13,12,3,"EN_AMPHF_PDET_TRF","Enables the TXPAD power detector preamplifier"};
conststructLMS7ParameterLOADR_PDET_TRF={0x0100,11,10,1,"LOADR_PDET_TRF","Controls the resistive load of the Power detector"};
conststructLMS7ParameterPD_PDET_TRF={0x0100,3,3,1,"PD_PDET_TRF","Powerdown signal for Power Detector"};
conststructLMS7ParameterPD_TLOBUF_TRF={0x0100,2,2,0,"PD_TLOBUF_TRF","Powerdown signal for TX LO buffer"};
conststructLMS7ParameterPD_TXPAD_TRF={0x0100,1,1,0,"PD_TXPAD_TRF","Powerdown signal for TXPAD"};
conststructLMS7ParameterEN_G_TRF={0x0100,0,0,1,"EN_G_TRF","Enable control for all the TRF_1 power downs"};
conststructLMS7ParameterF_TXPAD_TRF={0x0101,15,13,3,"F_TXPAD_TRF","Controls the switched capacitor at the TXPAD output. Is used for fine tuning of the TXPAD output"};
conststructLMS7ParameterL_LOOPB_TXPAD_TRF={0x0101,12,11,3,"L_LOOPB_TXPAD_TRF","Controls the loss of the of the loopback path at the TX side"};
conststructLMS7ParameterLOSS_LIN_TXPAD_TRF={0x0101,10,6,0,"LOSS_LIN_TXPAD_TRF","Controls the gain of the linearizing part of of the TXPAD"};
conststructLMS7ParameterLOSS_MAIN_TXPAD_TRF={0x0101,5,1,0,"LOSS_MAIN_TXPAD_TRF","Controls the gain output power of the TXPAD"};
conststructLMS7ParameterEN_LOOPB_TXPAD_TRF={0x0101,0,0,0,"EN_LOOPB_TXPAD_TRF","Enables the TXPAD loopback path"};
conststructLMS7ParameterGCAS_GNDREF_TXPAD_TRF={0x0102,15,15,0,"GCAS_GNDREF_TXPAD_TRF","Controls if the TXPAD cascode transistor gate bias is referred to VDD or GND"};
conststructLMS7ParameterICT_LIN_TXPAD_TRF={0x0102,14,10,12,"ICT_LIN_TXPAD_TRF","Control the bias current of the linearization section of the TXPAD"};
conststructLMS7ParameterICT_MAIN_TXPAD_TRF={0x0102,9,5,12,"ICT_MAIN_TXPAD_TRF","Control the bias current of the main gm section of the TXPAD"};
conststructLMS7ParameterVGCAS_TXPAD_TRF={0x0102,4,0,0,"VGCAS_TXPAD_TRF","Controls the bias voltage at the gate of TXPAD cascade"};
conststructLMS7ParameterLOOPB_TBB={0x0105,14,12,0,"LOOPB_TBB","This controls which signal is connected to the loopback output pins. Note: when both the lowpass ladder and real pole are powered down, the output of the active highband biquad is routed to the loopb output"};
conststructLMS7ParameterPD_LPFH_TBB={0x0105,4,4,0,"PD_LPFH_TBB","This selectively powers down the LPFH_TBB biquad"};
conststructLMS7ParameterPD_LPFIAMP_TBB={0x0105,3,3,0,"PD_LPFIAMP_TBB","selectively powers down the LPFIAMP_TBB front-end current amp of the transmitter baseband"};
conststructLMS7ParameterPD_LPFLAD_TBB={0x0105,2,2,1,"PD_LPFLAD_TBB","This selectively powers down the LPFLAD_TBB low pass ladder filter of the transmitter baseband"};
conststructLMS7ParameterPD_LPFS5_TBB={0x0105,1,1,1,"PD_LPFS5_TBB","This selectively powers down the LPFS5_TBB low pass real-pole filter of the transmitter baseband"};
conststructLMS7ParameterEN_G_TBB={0x0105,0,0,1,"EN_G_TBB","Enable control for all the TBB_TOP power downs"};
conststructLMS7ParameterICT_LPFS5_F_TBB={0x0106,14,10,12,"ICT_LPFS5_F_TBB","This controls the operational amplifier's output stage bias current of the low band real pole filter of the transmitter's baseband"};
conststructLMS7ParameterICT_LPFS5_PT_TBB={0x0106,9,5,12,"ICT_LPFS5_PT_TBB","This controls the operational amplifier's input stage bias current of the low band real pole filter of the transmitter's baseband"};
conststructLMS7ParameterICT_LPF_H_PT_TBB={0x0106,4,0,12,"ICT_LPF_H_PT_TBB","This controls the operational amplifiers input stage bias reference current of the high band low pass filter of the transmitter's baseband "};
conststructLMS7ParameterICT_LPFH_F_TBB={0x0107,14,10,12,"ICT_LPFH_F_TBB","controls the operational amplifiers output stage bias reference current of the high band low pass filter of the transmitter's baseband (LPFH_TBB)"};
conststructLMS7ParameterICT_LPFLAD_F_TBB={0x0107,9,5,12,"ICT_LPFLAD_F_TBB","This controls the operational amplfiers' output stages bias referene current of the low band ladder filter of the transmisster's baseband"};
conststructLMS7ParameterICT_LPFLAD_PT_TBB={0x0107,4,0,12,"ICT_LPFLAD_PT_TBB","This controls the operational amplifers' input stages bias reference current of the low band ladder filter of the transmitter's baseband"};
conststructLMS7ParameterCG_IAMP_TBB={0x0108,15,10,37,"CG_IAMP_TBB","This controls the frontend gain of the TBB. For a given gain value, this control value varies with the set TX mode. After resistance calibration, the following table gives the nominal values for each frequency setting. However, this table is to be updated and corrected after calibration"};
conststructLMS7ParameterICT_IAMP_FRP_TBB={0x0108,9,5,1,"ICT_IAMP_FRP_TBB","This controls the reference bias current of the IAMP main bias current sources"};
conststructLMS7ParameterICT_IAMP_GG_FRP_TBB={0x0108,4,0,6,"ICT_IAMP_GG_FRP_TBB","This controls the reference bias current of the IAMP's cascode transistors gate voltages that set the IAMP's input voltage level. The IAMP's input is connected to the DAC output"};
conststructLMS7ParameterRCAL_LPFH_TBB={0x0109,15,8,97,"RCAL_LPFH_TBB","This controls the value of the equivalent resistance of the resistor banks of the biquad filter stage (of the high band section) of the transmitter baseband(TBB)"};
conststructLMS7ParameterRCAL_LPFLAD_TBB={0x0109,7,0,193,"RCAL_LPFLAD_TBB","This controls the value of the equivalent resistance of the resistor banks of the low pass filter ladder (of the low band section) of the transmitter baseband(TBB)"};
conststructLMS7ParameterTSTIN_TBB={0x010A,15,14,0,"TSTIN_TBB","This control selects where the input test signal (vinp/n_aux_bbq/i) is routed to as well as disabling the route."};
conststructLMS7ParameterBYPLADDER_TBB={0x010A,13,13,0,"BYPLADDER_TBB","This signal bypasses the LPF ladder of TBB and directly connects the output of current amplifier to the null port of the real pole stage of TBB low pass filter"};
conststructLMS7ParameterCCAL_LPFLAD_TBB={0x010A,12,8,16,"CCAL_LPFLAD_TBB","A common control signal for all the capacitor banks of TBB filters (including the ladder, real pole, and the high band biquad). It is the calibrated value of the banks control that sets the value of the banks' equivalent capacitor to their respective nominal values"};
conststructLMS7ParameterRCAL_LPFS5_TBB={0x010A,7,0,76,"RCAL_LPFS5_TBB","This controls the value of the equivalent resistance of the resistor banks of the real pole filter stage (of the low band section) of the transmitter baseband (TBB). Following is a nominal values table that are corrected for any process variation after calibration"};
conststructLMS7ParameterPD_LNA_RFE={0x010C,7,7,1,"PD_LNA_RFE","Power control signal for LNA_RFE"};
conststructLMS7ParameterPD_RLOOPB_1_RFE={0x010C,6,6,1,"PD_RLOOPB_1_RFE","Power control signal for RXFE loopback 1"};
conststructLMS7ParameterPD_RLOOPB_2_RFE={0x010C,5,5,1,"PD_RLOOPB_2_RFE","Power control signal for RXFE loopback 2"};
conststructLMS7ParameterPD_MXLOBUF_RFE={0x010C,4,4,1,"PD_MXLOBUF_RFE","Power control signal for RXFE mixer lo buffer"};
conststructLMS7ParameterPD_QGEN_RFE={0x010C,3,3,1,"PD_QGEN_RFE","Power control signal for RXFE Quadrature LO generator"};
conststructLMS7ParameterPD_RSSI_RFE={0x010C,2,2,1,"PD_RSSI_RFE","Power control signal for RXFE RSSI"};
conststructLMS7ParameterPD_TIA_RFE={0x010C,1,1,0,"PD_TIA_RFE","Power control signal for RXFE TIA"};
conststructLMS7ParameterEN_G_RFE={0x010C,0,0,1,"EN_G_RFE","Enable control for all the RFE_1 power downs"};
conststructLMS7ParameterSEL_PATH_RFE={0x010D,8,7,1,"SEL_PATH_RFE","Selects the active path of the RXFE"};
conststructLMS7ParameterEN_DCOFF_RXFE_RFE={0x010D,6,6,0,"EN_DCOFF_RXFE_RFE","Enables the DCOFFSET block for the RXFE"};
conststructLMS7ParameterEN_INSHSW_LB1_RFE={0x010D,4,4,1,"EN_INSHSW_LB1_RFE","Enables the input shorting switch at the input of the loopback 1 (in parallel with LNAL mixer)"};
conststructLMS7ParameterEN_INSHSW_LB2_RFE={0x010D,3,3,1,"EN_INSHSW_LB2_RFE","Enables the input shorting switch at the input of the loopback 2 (in parallel with LNAW mixer)"};
conststructLMS7ParameterEN_INSHSW_L_RFE={0x010D,2,2,1,"EN_INSHSW_L_RFE","Enables the input shorting switch at the input of the LNAL"};
conststructLMS7ParameterEN_INSHSW_W_RFE={0x010D,1,1,1,"EN_INSHSW_W_RFE","Enables the input shorting switch at the input of the LNAW"};
conststructLMS7ParameterEN_NEXTRX_RFE={0x010D,0,0,0,"EN_NEXTRX_RFE","Enables the daisy chain LO buffer going from RXFE1 to RXFE2"};
conststructLMS7ParameterDCOFFI_RFE={0x010E,13,7,64,"DCOFFI_RFE","Controls DC offset at the output of the TIA by injecting current to the input of the TIA (I side)"};
conststructLMS7ParameterDCOFFQ_RFE={0x010E,6,0,64,"DCOFFQ_RFE","Controls DC offset at the output of the TIA by injecting current to the input of the TIA (Q side)"};
conststructLMS7ParameterICT_LOOPB_RFE={0x010F,14,10,12,"ICT_LOOPB_RFE","Controls the reference current of the RXFE loopback amplifier"};
conststructLMS7ParameterICT_TIAMAIN_RFE={0x010F,9,5,2,"ICT_TIAMAIN_RFE","Controls the reference current of the RXFE TIA first stage"};
conststructLMS7ParameterICT_TIAOUT_RFE={0x010F,4,0,2,"ICT_TIAOUT_RFE","Controls the reference current of the RXFE TIA 2nd stage"};
conststructLMS7ParameterICT_LNACMO_RFE={0x0110,14,10,2,"ICT_LNACMO_RFE","Controls the current generating LNA output common mode voltage"};
conststructLMS7ParameterICT_LNA_RFE={0x0110,9,5,31,"ICT_LNA_RFE","Controls the current of the LNA core"};
conststructLMS7ParameterICT_LODC_RFE={0x0110,4,0,20,"ICT_LODC_RFE","Controls the DC of the mixer LO signal at the gate of the mixer switches"};
conststructLMS7ParameterCAP_RXMXO_RFE={0x0111,9,5,4,"CAP_RXMXO_RFE","Control the decoupling cap at the output of the RX Mixer"};
conststructLMS7ParameterCGSIN_LNA_RFE={0x0111,4,0,3,"CGSIN_LNA_RFE","Controls the cap parallel with the LNA input input NMOS CGS to control the Q of the maching circuit and provides trade off between gain/NF and IIP. The higher the frequency, the lower CGSIN_LNA_RFE should be. Also, the higher CGSIN, the lower the Q, The lower the gain, the higher the NF, and the higher the IIP3"};
conststructLMS7ParameterCCOMP_TIA_RFE={0x0112,15,12,12,"CCOMP_TIA_RFE","Compensation capacitor for TIA"};
conststructLMS7ParameterCFB_TIA_RFE={0x0112,11,0,230,"CFB_TIA_RFE","Feeback capacitor for TIA. Controls the 3dB BW of the TIA. Should be set with calibration through digital baseband"};
conststructLMS7ParameterG_LNA_RFE={0x0113,9,6,15,"G_LNA_RFE","Controls the gain of the LNA"};
conststructLMS7ParameterPD_LPFH_RBB={0x0115,3,3,1,"PD_LPFH_RBB","Power down of the LPFH block"};
conststructLMS7ParameterPD_LPFL_RBB={0x0115,2,2,0,"PD_LPFL_RBB","Power down of the LPFL block"};
conststructLMS7ParameterPD_PGA_RBB={0x0115,1,1,0,"PD_PGA_RBB","Power down of the PGA block"};
conststructLMS7ParameterEN_G_RBB={0x0115,0,0,1,"EN_G_RBB","Enable control for all the RBB_1 power downs"};
conststructLMS7ParameterR_CTL_LPF_RBB={0x0116,15,11,16,"R_CTL_LPF_RBB","Controls the absolute value of the resistance of the RC time constant of the RBB_LPF blocks (both Low and High)"};
conststructLMS7ParameterRCC_CTL_LPFH_RBB={0x0116,10,8,1,"RCC_CTL_LPFH_RBB","Controls the stability passive compensation of the LPFH_RBB operational amplifier"};
conststructLMS7ParameterC_CTL_LPFH_RBB={0x0116,7,0,128,"C_CTL_LPFH_RBB","Controls the capacitance value of the RC time constant of RBB_LPFH and it varies with the respective rxMode from 37MHz to 108MHz"};
conststructLMS7ParameterRCC_CTL_LPFL_RBB={0x0117,13,11,5,"RCC_CTL_LPFL_RBB","Controls the stability passive compensation of the LPFL_RBB operational amplifier"};
conststructLMS7ParameterC_CTL_LPFL_RBB={0x0117,10,0,12,"C_CTL_LPFL_RBB","Controls the capacitance value of the RC time constant of RBB_LPFH and it varies with the respective rxMode from 1.4MHz to 20MHz."};
conststructLMS7ParameterINPUT_CTL_PGA_RBB={0x0118,15,13,0,"INPUT_CTL_PGA_RBB","There are a total of four different differential inputs to the PGA. Only one of them is active at a time"};
conststructLMS7ParameterICT_LPF_IN_RBB={0x0118,9,5,12,"ICT_LPF_IN_RBB","Controls the reference bias current of the input stage of the operational amplifier used in RBB_LPF blocks (Low or High). "};
conststructLMS7ParameterICT_LPF_OUT_RBB={0x0118,4,0,12,"ICT_LPF_OUT_RBB","The reference bias current of the output stage of the operational amplifier used in RBB_LPF blocks (low or High)"};
conststructLMS7ParameterOSW_PGA_RBB={0x0119,15,15,0,"OSW_PGA_RBB","There are two instances of the PGA circuit in the design. The output of the RBB_LPF blocks are connected the input of these PGA blocks (common). The output of one of them is connected to two pads pgaoutn and pgaoutp and the output of the other PGA is connected directly to the ADC input"};
conststructLMS7ParameterICT_PGA_OUT_RBB={0x0119,14,10,6,"ICT_PGA_OUT_RBB","Controls the output stage reference bias current of the operational amplifier used in the PGA circuit"};
conststructLMS7ParameterICT_PGA_IN_RBB={0x0119,9,5,6,"ICT_PGA_IN_RBB","Controls the input stage reference bias current of the operational amplifier used in the PGA circuit"};
conststructLMS7ParameterG_PGA_RBB={0x0119,4,0,11,"G_PGA_RBB","This is the gain of the PGA"};
conststructLMS7ParameterRCC_CTL_PGA_RBB={0x011A,13,9,23,"RCC_CTL_PGA_RBB","Controls the stability passive compensation of the PGA_RBB operational amplifier"};
conststructLMS7ParameterC_CTL_PGA_RBB={0x011A,6,0,2,"C_CTL_PGA_RBB","Control the value of the feedback capacitor of the PGA that is used to help against the parasitic cap at the virtual node for stability"};
conststructLMS7ParameterRESET_N={0x011C,15,15,1,"RESET_N","Resets SX. A pulse should be used in the start-up to reset"};
conststructLMS7ParameterSPDUP_VCO={0x011C,14,14,0,"SPDUP_VCO","Bypasses the noise filter resistor for fast settling time. It should be connected to a 1uS pulse"};
conststructLMS7ParameterBYPLDO_VCO={0x011C,13,13,1,"BYPLDO_VCO","Controls the bypass signal for the SX LDO"};
conststructLMS7ParameterEN_COARSEPLL={0x011C,12,12,0,"EN_COARSEPLL","Enable signal for coarse tuning block"};
conststructLMS7ParameterCURLIM_VCO={0x011C,11,11,1,"CURLIM_VCO","Enables the output current limitation in the VCO regulator"};
conststructLMS7ParameterEN_INTONLY_SDM={0x011C,9,9,0,"EN_INTONLY_SDM","Enables INTEGER-N mode of the SX "};
conststructLMS7ParameterEN_SDM_CLK={0x011C,8,8,1,"EN_SDM_CLK","Enables/Disables SDM clock. In INT-N mode or for noise testing, SDM clock can be disabled"};
conststructLMS7ParameterPD_FBDIV={0x011C,7,7,0,"PD_FBDIV","Power down the feedback divider block"};
conststructLMS7ParameterPD_LOCH_T2RBUF={0x011C,6,6,1,"PD_LOCH_T2RBUF","Power down for LO buffer from SXT to SXR. To be active only in the TDD mode"};
conststructLMS7ParameterPD_CP={0x011C,5,5,0,"PD_CP","Power down for Charge Pump"};
conststructLMS7ParameterPD_FDIV={0x011C,4,4,0,"PD_FDIV","Power down for feedback frequency and forward dividers"};
conststructLMS7ParameterPD_SDM={0x011C,3,3,0,"PD_SDM","Power down for SDM"};
conststructLMS7ParameterPD_VCO_COMP={0x011C,2,2,0,"PD_VCO_COMP","Power down for VCO comparator"};
conststructLMS7ParameterPD_VCO={0x011C,1,1,1,"PD_VCO","Power down for VCO"};
conststructLMS7ParameterEN_G={0x011C,0,0,1,"EN_G","Enable control for all the SXT power downs"};
conststructLMS7ParameterPW_DIV2_LOCH={0x011F,14,12,3,"PW_DIV2_LOCH","trims the duty cycle of DIV2 LOCH. Only works when forward divider is dividing by at least 2 (excluding quadrature block division). If in bypass mode, this does not work"};
conststructLMS7ParameterPW_DIV4_LOCH={0x011F,11,9,3,"PW_DIV4_LOCH","trims the duty cycle of DIV4 LOCH. Only works when forward divider is dividing by at least 4 (excluding quadrature block division). If in bypass mode, this does not work"};
conststructLMS7ParameterDIV_LOCH={0x011F,8,6,1,"DIV_LOCH","Controls the division ratio in the LOCH_DIV"};
"Controls the test mode of PLLs. TST signal lines are shared between all PLLs (CGEN, RX and TX). Only one TST signal of any PLL should be active at a given time.\n\
0 - TST disabled; RSSI analog outputs enabled if RSSI blocks active and when all PLL test signals are off(default)\n\
conststructLMS7ParameterICT_VCO={0x0120,7,0,255,"ICT_VCO","Scales the VCO bias current from 0 to 2.5xInom"};
conststructLMS7ParameterRSEL_LDO_VCO={0x0121,15,11,6,"RSEL_LDO_VCO","Set the reference voltage that supplies bias voltage of switch-cap array and varactor"};
conststructLMS7ParameterCSW_VCO={0x0121,10,3,128,"CSW_VCO","Coarse control of VCO frequency, 0 for lowest frequency and 255 for highest. This control is set by SX_SWC_calibration"};
conststructLMS7ParameterSEL_VCO={0x0121,2,1,2,"SEL_VCO","Selects the active VCO. It is set by SX_SWC_calibration"};
conststructLMS7ParameterREVPH_PFD={0x0122,12,12,0,"REVPH_PFD","Reverse the pulses of PFD. It can be used to reverse the polarity of the PLL loop (positive feedback to negative feedback)"};
conststructLMS7ParameterIOFFSET_CP={0x0122,11,6,12,"IOFFSET_CP","Scales the offset current of the charge pump, 0-->63. This current is used in Fran-N mode to create an offset in the CP response and avoid the non-linear section"};
conststructLMS7ParameterIPULSE_CP={0x0122,5,0,63,"IPULSE_CP","Scales the pulse current of the charge pump"};
conststructLMS7ParameterTSGSWAPIQ_TXTSP={0x0200,4,4,0,"TSGSWAPIQ_TXTSP","Swap signals at test signal generator's output"};
conststructLMS7ParameterTSGMODE_TXTSP={0x0200,3,3,0,"TSGMODE_TXTSP","Test signal generator mode"};
conststructLMS7ParameterINSEL_TXTSP={0x0200,2,2,0,"INSEL_TXTSP","Input source of TxTSP"};
conststructLMS7ParameterBSTART_TXTSP={0x0200,1,1,0,"BSTART_TXTSP","Starts delta sigma built in self test. Keep it at 1 one at least three clock cycles"};
conststructLMS7ParameterTSGSWAPIQ_RXTSP={0x0400,4,4,0,"TSGSWAPIQ_RXTSP","Swap signals at test signal generator's output"};
conststructLMS7ParameterTSGMODE_RXTSP={0x0400,3,3,0,"TSGMODE_RXTSP","Test signal generator mode"};
conststructLMS7ParameterINSEL_RXTSP={0x0400,2,2,0,"INSEL_RXTSP","Input source of RxTSP"};
conststructLMS7ParameterBSTART_RXTSP={0x0400,1,1,0,"BSTART_RXTSP","Starts delta sigma built in self test. Keep it at 1 one at least three clock cycles"};
conststructLMS7ParameterDCCORR_AVG_RXTSP={0x0404,2,0,0,"DCCORR_AVG_RXTSP","Number of samples to average for Automatic DC corrector. Number of samples to average is 2DCCORR_AVG + 12"};
conststructLMS7ParameterGFIR1_L_RXTSP={0x0405,10,8,0,"GFIR1_L_RXTSP","Parameter l of GFIR1 (l = roundUp(CoeffN/5)-1). Unsigned integer"};
conststructLMS7ParameterGFIR1_N_RXTSP={0x0405,7,0,0,"GFIR1_N_RXTSP","Clock division ratio of GFIR1 is GFIR1_N + 1. Unsigned integer"};
conststructLMS7ParameterGFIR2_L_RXTSP={0x0406,10,8,0,"GFIR2_L_RXTSP","Parameter l of GFIR2 (l = roundUp(CoeffN/5)-1). Unsigned integer"};
conststructLMS7ParameterGFIR2_N_RXTSP={0x0406,7,0,0,"GFIR2_N_RXTSP","Clock division ratio of GFIR2 is GFIR2_N + 1. Unsigned integer"};
conststructLMS7ParameterGFIR3_L_RXTSP={0x0407,10,8,0,"GFIR3_L_RXTSP","Parameter l of GFIR3 (l = roundUp(CoeffN/5)-1). Unsigned integer"};
conststructLMS7ParameterGFIR3_N_RXTSP={0x0407,7,0,0,"GFIR3_N_RXTSP","Clock division ratio of GFIR3 is GFIR3_N + 1. Unsigned integer"};
@param buffer destination array for interleaved values (IQIQIQ...), must be big enough to store requested number of samples, each value amplitude will be from -2048 to 2047
@param samplesCount number of samples to read, 1 sample = 2 bytes I + 2 bytes Q
@param antenna_id source channel
@param timestamp returns timestamp of the first sample in the buffer (used only in synchronized operating mode)
@param timeout_ms time amount in milliseconds to try reading samples