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wangjie
OpenXG-RAN
Commits
aadc2825
Commit
aadc2825
authored
6 years ago
by
Thomas Schlichter
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[ulschsim] Initial version (copy of dlschsim)
parent
94cca321
dev
1
128-ues
256_QAM_demod
445-LDPC-implementation-on-GPU
459-pusch-based-ta-updates
464-ru_beamforming_in_gpu
464-ru_beamforming_in_gpu-CPUsubfunction
472-add-pusch-dmrs-modes
481-ldpc-decoder-on-gpu
512-dataplane-bug-in-l2nfapi_nos1
5g_fapi_scf
FR2_NSA
Fix_SA_SIB1
LTE_TRX_on_single_port
NCTU_CS_ISIP
NCTU_CS_ISIP_CPU
NCTU_CS_ISIP_GPU
NCTU_OpinConnect_Beamforming_ISIP
NCTU_OpinConnect_LDPC
NR-PHY-MAC-IF-multi-UE
NRPRACH_highSpeed_saankhya
NRUE_usedlschparallel
NR_10MHz
NR_2port_CSIRS
NR_CSIRS_tomerge
NR_CSI_reporting
NR_DCI_01
NR_DLUL_PF
NR_DLUL_PF_4UL
NR_DLUL_PF_rebased
NR_DL_MIMO
NR_DL_sched_fixes
NR_DL_scheduler
NR_F1C_F1U_extensions
NR_FAPI_beamindex_SSB_RO
NR_FAPI_beamindex_SSB_RO_SEMPROJ
NR_FDD_FIX
NR_FR2_RA
NR_FR2_RRC_SSB
NR_FR2_initsync_fixes
NR_MAC_CE_GlobalEdge
NR_MAC_Multi_Rach_GlobalEdge
NR_MAC_Multi_Rach_GlobalEdge-old
NR_MAC_SSB
NR_MAC_SSB_RO_GlobalEdge
NR_MAC_SSB_RO_UE_IDCC
NR_MAC_SSB_RO_merge
NR_MAC_TCI_UCI_GlobalEdge
NR_MCS_BLER
NR_NGAP
NR_PDCP_noS1
NR_PUCCH_MultiUE
NR_RA_cleanup
NR_RA_updates
NR_RRCConfiguragion_FR2
NR_RRCConfiguration
NR_RRCConfiguration_FR2
NR_RRCConfiguration_S1U
NR_RRCConfiguration_merge_develop
NR_RRCConfiguration_sync_source
NR_RRCConfiguration_trx_thread
NR_RRCReconfiguration_BWP
NR_RRC_CP_bugfix
NR_RRC_PDCP
NR_RRC_PRACH_procedures
NR_RRC_PRACH_procedures_todevelop
NR_RRC_PUSCH
NR_RRC_TA
NR_RRC_X2AP_AMBR_Change_Global_edge
NR_RRC_X2AP_RemoveHardcodings_GlobalEdge
NR_RRC_config_simplified
NR_RRC_harq
NR_RRC_harq_b
NR_RRC_harq_hacks
NR_RRC_harq_newdcipdu
NR_SA_F1AP_5GRECORDS
NR_SA_F1AP_5GRECORDS-USIM
NR_SA_F1AP_5GRECORDS-wf-0623
NR_SA_F1AP_5GRECORDS_lts
NR_SA_F1AP_RFSIMULATOR
NR_SA_F1AP_RFSIMULATOR2
NR_SA_F1AP_RFSIMULATOR2_SRB
NR_SA_F1AP_RFSIMULATOR3
NR_SA_F1AP_RFSIMULATOR3_tmp
NR_SA_F1AP_RFSIMULATOR3_wf
NR_SA_F1AP_RFSIMULATOR_w5GCN
NR_SA_F1AP_dev
NR_SA_NGAP_RRC
NR_SA_NGAP_RRC_wk42
NR_SA_itti_sim_wk48
NR_SA_itti_sim_wk48_hs
NR_SA_itti_sim_wk48_hs1
NR_SA_w5GCN_new_gtpu
NR_SCHED
NR_SCHED_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ
NR_SCHED_PDCCH_PUCCH_HARQ_rebased
NR_SCHED_fixes
NR_SRB_Config
NR_TRX_on_single_port
NR_TRX_on_single_port2
NR_UE_CONFIG_REQ_FIXES
NR_UE_MAC_scheduler
NR_UE_PUCCH_bugfixes
NR_UE_RA_fixes
NR_UE_SA
NR_UE_SSB_meas
NR_UE_UL_DCI_improvements
NR_UE_dlsch_bugfix
NR_UE_enable_parallelization
NR_UE_rework_test
NR_UE_reworking_UCI_procedures
NR_UE_stability_fixes
NR_UL_FAPI_programming
NR_UL_SCFDMA_100MHz
NR_UL_scheduler
NR_UL_scheduler_rebased
NR_UL_scheduling
NR_Wireshark
NR_beam_simulation
NR_beamforming_test
NR_cleanup_PUCCH_resources
NR_gNB_SCF_Indication
NR_gNB_initial_MIB_fix
NR_ipaccess_testing
NR_mac_uci_functions_rework
NR_msg2_phytest
NR_multiplexing_HARQ_CSI_PUCCH
NR_new_ul_antennaports
NR_phytest_bugfixes
NR_reworking_UL_antennaports
NR_scheduling_CSIRS
NR_scheduling_request
NR_scheduling_request2
NR_scheduling_request3
NR_test_S1U_RRC_PRACH_procedures
NR_ue_dlsch_dmrs_cdm
OpInConnect_ISIP
PBCHNRTCFIX
PUSCH_TA_update
RA_CI_test
RFquality
Saankhya_NRPRACH_HighSpeed
Test_SA_5GREC
UE_DL_DCI_hotfix
add-dmrs-test
add-ru-docker-image
addoptions_nr_USRPdevice
avxllr
bandwidth-testing
bch-fixes-bitmap
benetel_5g_prach_fix
benetel_config_file_fix
benetel_dpdk20
benetel_driver_uldl_pf_merge
benetel_driver_update
benetel_fixes
benetel_phase_rotation
benetel_phase_rotation_old
bsr-fix
bugfix-free-ra-process
bugfix-minor-remove-wrong-log
bugfix-nr-bands
bugfix-nr-ldpc-post-processing
bugfix-nr-ldpc-size-typo
bugfix-nr-pdcp-sn-size
bugfix-nr-rate-matching-assertion
bugfix-nr-t-reordering
bugfix-x2-SgNBAdditionRequest
bugfix_gnb_rt_stats_html
bupt-sa-merge
cce_indexing_fix
cce_indexing_fix2
ci-add-sabox-support
ci-deploy-asterix
ci-deploy-docker-compose
ci-fix-module-ul-iperf
ci-new-docker-pipeline
ci-rd-july-improvements
ci-reduce-nb-vms
ci-test
ci-ul-iperf-from-trf-container
ci_benetel_longrun_limits
ci_benetel_test
ci_fix_iperf_for_module
ci_hotfix_module_ue_ip_address
ci_improve_module_ctl
ci_nsa_2x2_implem
ci_nsa_benetel
ci_nsa_fixes
ci_nsa_pipes_improve
ci_nsa_test_integration_2021_wk19
ci_nsa_traces
ci_nsa_uplink
ci_phytest
ci_quectel_support
ci_sa_rfsim_test
ci_solve_ul_for_module
ci_test_5GREC
ci_test_nsa_2x2
ci_test_nsa_fix_quectel_nic
ci_test_nsa_on_develop
ci_test_ra_fr2
ci_testinfra_as_code
ci_update_build_nasmesh
ci_vm_resource_fix
clean-5G-scope-round2
cleanup_softmodem_main
code-cleanup-20210716
constant_power
debug-UL-5GRECORDS
debug_UL_signal
debug_branch_init_sync
detached-w16-test
develop
develop-CBRA-v3
develop-CCE
develop-NR_SA_F1AP_5GRECORDS
develop-NR_SA_F1AP_5GRECORDS-abs
develop-NR_SA_F1AP_5GRECORDS-hs
develop-NR_SA_F1AP_5GRECORDS-hs1
develop-NR_SA_F1AP_5GRECORDS-lts
develop-NR_SA_F1AP_5GRECORDS-lts-wf
develop-NR_SA_F1AP_5GRECORDS-v3
develop-NR_SA_F1AP_5GRECORDS_100M
develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA
develop-NR_SA_F1AP_5GRECORDS_lfq_0607
develop-NSA_SA_fixes
develop-SA-CBRA
develop-SA-CBRA-CUDU
develop-SA-CBRA-Msg5
develop-SA-CBRA-lts
develop-SA-CBRA-ulsch-lts
develop-SA-RA
develop-SnT
develop-aw2sori
develop-ci
develop-nr
develop-nr-fr2
develop-nr-fr2-rework
develop-nr_cppcheck
develop-oriecpriupdates
develop-sib1
develop-sib1-local
develop-sib1-lts
develop-sib1-update
develop-sib1-update-test1
develop-sib1-update-ue
develop-wf-du
develop_fpga_ldpc
develop_inria_ci_deployment
develop_inria_ci_deployment_gp
develop_integration_2020_w15
develop_integration_2020_w19
develop_integration_w08
develop_stable
dfts_alternatives
disable_CSI_measrep
dlsch-all-dlslots
dlsch_encode_mthread
dlsch_parallel
docker-improvements-2021-april
docker-no-cache-option
docupdate_tools
dongzhanyi-zte-develop
dongzhanyi-zte-develop1
dongzhanyi-zte-develop2
dreibh/apt-auth-fix
dreibh/device-load-fix
dreibh/device-load-fix-develop-branch
dual-connectivity
edrx
enhance-rfsim
episys-merge
episys/nsa_baseline
episys/nsa_development
extend_sharedlibusage
extend_sharedlibusage2
fapi_for_dmrs_and_ptrs
feature-4g-sched
feature-nr-4g-nfapi-modifications
feature-support-clang-format
feature/make-s1-mme-port-configurable
feature/make-s1-mme-port-configurable-with-astyle-fixes
fedora-gen-kernel-fix
fembms-enb-ue
fft_bench_hotfix
finalize-oaicn-integration
firas
fix-check
fix-ci-tun
fix-clock-source
fix-compile
fix-itti-segv
fix-l2-sim
fix-limeSDR-compile
fix-lte-ue-modem-in-docker-container
fix-nr-pdcp-timer
fix-nr-rlc-range-nack
fix-physim-deploy
fix-physim-run-script-on-cluster
fix-quectel
fix-realtime
fix-retransmission-rbg
fix-softmodem-restart
fix-warnings
fix-x2-without-gnb
fix_NR_DLUL_PF
fix_NR_DLUL_PF_benchmark
fix_coreset_dmrs_idx
fix_do_ra_data
fix_nr_ulsim
fix_pdsch_low_prb
fix_rb_corruption
fix_reestablishment
fix_rfsim_mimo
fix_rrc_x2_ticking
fixes-CE-RLC-PDU-size
fixes-mac-sched-nfapi
fixes-mac-sched-tun
fixes-tun
fixgtpu
flexran-apps
flexran-improvements
flexran-repair-mme-mgmt
flexran-rtc-repo-is-public
fr2-hw-test
fujitsu_lte_contribution
fujitsu_lte_contribution-128
gNB-nrUE-USRP
generate_push_ptrs
git-dashboard
gnb-freerun-txru
gnb-n300-fixes
gnb-only-test
gnb-realtime-hotfix
gnb-realtime-quickfix
gnb-threadpool
hack-bch-no-sched-sf-0
hack-exit-gnb-when-no-enb-nsa
harq-hotfix
hotfix-minor-remove-nr-rlc-cppcheck-error
hotfix-nr-rlc-tick
hotfix-ocp-executable
hotfix-ue-musim-compilation
hotfix_usrp_lib
improve_build_nr_lte_merge
improve_nr_modulation
improve_ue_stability
integ-w13-test-rt-issue
integration-develop-nr-2019w45
integration_2020_wk15
integration_2020_wk40
integration_2020_wk41
integration_2020_wk42_2
integration_2020_wk45
integration_2020_wk45_2
integration_2020_wk46
integration_2020_wk46_2
integration_2020_wk47
integration_2020_wk48
integration_2020_wk48_2
integration_2020_wk49
integration_2020_wk50
integration_2020_wk50_1
integration_2020_wk51
integration_2020_wk51_2
integration_2021_wk02
integration_2021_wk02_wMR988
integration_2021_wk04
integration_2021_wk05
integration_2021_wk06
integration_2021_wk06_MR978
integration_2021_wk06_b
integration_2021_wk06_c
integration_2021_wk08
integration_2021_wk08_2
integration_2021_wk08_MR963
integration_2021_wk09
integration_2021_wk09_b
integration_2021_wk10
integration_2021_wk10_b
integration_2021_wk11
integration_2021_wk12
integration_2021_wk12_b
integration_2021_wk13_a
integration_2021_wk13_b
integration_2021_wk13_b_fix_tdas
integration_2021_wk13_b_fixed
integration_2021_wk13_c
integration_2021_wk14_a
integration_2021_wk15_a
integration_2021_wk16
integration_2021_wk17_a
integration_2021_wk17_b
integration_2021_wk18_a
integration_2021_wk18_b
integration_2021_wk19
integration_2021_wk20_a
integration_2021_wk22
integration_2021_wk23
integration_2021_wk27
integration_2021_wk28
integration_2021_wk30
integration_2021_wk30_b
integration_w5GC_CBRA_test
inter-RRU-final
inter-RRU-nr
inter-RRU-oairu
inter-rru-UE
interoperability-test
isip_nr
itti-enhancement
l2-fixes
ldpc-dec-layering
ldpc-decoder-codegen
ldpc-decoder-codegen2
ldpc-decoder-improvements
ldpc-offload
ldpc_offload_t1
ldpc_short_codeword_fixes
load_gnb
lte-ulsch-bugfix
lte_uplink_improvement
mac-fixes-wk45_2
mbms-fix-develop-nr
merging-2019-w51-to-develop-nr
migrate-cpp-check-container
migrate-vm-pipeline-to-bionic
minor-fix-doc-basic-sim
mosaic5g-oai-ran
mosaic5g-oai-sim
msg4_phy_0303_lfq
multiple_ssb_sib1_bugfix
nasmesh_kernel_5.8
new-gtpu
new_rlc_2020
nfapi-bugfix
nfapi_nr_arch_mod
nfapi_nr_develop
nfapi_nr_develop_new
ngap-dlul
ngap-support
ngap-w48-merge2
ngap-wf
ngap-wf-1120
ngap-wf-1120-srb
ngap-wf-1120-srb-gtp
ngap-wf-1120-srb-gtp-hs
ngap-wf-1120-srb-gtp-hs1
ngap-wf-1120-srb-gtp-hs2
ngap-wf-1120-srb-gtp-yhz
ngap-wf-1203-yunsdr
ngap-wf-liuyu
ngap_lfq_1120
ngap_merge
noCore
nr-bsr-fix
nr-coreset-bug-fix
nr-dl-mimo-2layer
nr-dlsch-multi-thread
nr-dlsch-thread
nr-dmrs-fixes
nr-dual-connectivity
nr-interdigital-test
nr-ip-uplink-noS1
nr-mac-pdu-wireshark
nr-mac-remove-ue-list
nr-pdcp
nr-pdcp-benchmarking
nr-pdcp-improvements
nr-pdcp-nea2-security
nr-pdcp-nia2-integrity
nr-pdcp-small-bugfixes
nr-pdcp-srb-integrity
nr-pdsch-extraction-bugfix
nr-physim-update
nr-ra-fix
nr-rlc-am-bugfix-w44
nr-rlc-bugfix-w44
nr-ssb-measurements
nr-stats-print
nr-timing-measurement
nr-timing-measurement-merge
nr-ue-buffer-status
nr-uldci
nrPBCHTCFix
nrPbchTcFix
nrUE
nrUE-hs
nrUE-upper-layer
nr_beamforming
nr_bsr
nr_csi_newbranch
nr_demo_wsa2019
nr_dl_dmrs_type2
nr_dl_pf
nr_dl_pf2
nr_dl_ul_ptrs
nr_dlsch_parallel_measurements
nr_dlsim_plot
nr_fapi_for_push_tmp
nr_fdd_if_fix
nr_fix_easycppcheck
nr_flexible_NRBDL
nr_improve_build_procedures
nr_improve_chanest
nr_increase_tp
nr_pdcch_testing
nr_polar_decoder_improvement
nr_power_measurement_fixes
nr_prach
nr_prach_fr2
nr_pucch
nr_pucch2
nr_segmentation_fixes
nr_sim_fix
nr_tdd_configuration
nr_ue_msg3
nr_ue_pdcp_fix
nr_ue_remove_high_speed_flag
nr_ue_tti_cleanup
nr_ul_pf
nr_ul_scfdma
nr_vcd
nrue-multi-thread
nrue_msg2_reception
nsa-ue
nsa_remove_band_hardcodings
oai-sim
oai-ubuntu-docker
oai-ubuntu-docker-for-lmssdr
oairu
oairu-dockerfile-support
oc-docker-october-improvements
openxg/develop
pdcp-benchmark
pdsch-ch-est
phy-asan-fixes
physim-build-deploy
physim-deploy-handle-error-cases
polar8
prb_based_dl_channel_estimation
ptrs_rrc_config
pusch-mthread-scaling-fix
pusch-retrans-fix-ue
ra-dl-ul
recursive-cmake
reduce_memory_footprint
remove-ci-workaround
remove_nos1_hack_pdcp
remove_x2_gnb_hardcoding
repair-TA
revert-f5c94279
revert_memcpy
rh-ci-add-ue-parallelization
rh_ci_add_runtime_stats
rh_ci_add_uldlharq_stats
rh_ci_fix_autoterminate
rh_ci_fr1_update
rh_ci_gsheet_rt_monitoring
rh_ci_nsa2jenkins
rh_ci_nsa_test_n310
rh_ci_oc
rh_ci_phy_test_improve
rh_ci_py
rh_ci_ra_fr2
rh_ci_rfsim_ra
rh_ci_test_benetel
rh_ci_test_nsa
rh_ci_test_nsa_wk16
rh_ci_test_nsa_wk17_b
rh_ci_test_nsa_wk17b
rh_ci_test_rfsim_sa
rh_ci_ue_parallel
rh_doc_update_3
rh_fr1_newjenkins
rh_fr1_update
rh_gnb_compile_fix
rh_wk50_debug
rlc-v2-bugfix-status-reporting
rlc-v2-tick
rlc_v2_coverity_fixes
rohan_ulsim2RxFix
rrc-enb-phy-testmode
ru-parallel-beamforming
runel
runel-reverse-test
s1-subnormal_rewrite
s1_subnormal
s1_subnormal-robert
s1ap-bugfix-rab_setup
sa-demo
sa-demo-hs
sa-merge-rrc-srb
sa-msg4
sa-msg4-rrc
sa-msg4-rrc-yihz
sa-msg4-rrc-yihz-hs
sa_rrc_yihz
sanitize-address
sanitize-v1
sanitize-v1-tmp
sarma_pvnp_oai
scs_60_iisc
sim-channels
small-bugfixes-w40
small-config-change
small_nr_bugfixes
smallcleanup
softmodem_cleanup
split73
t-gnb-tracer
test-5GREC
test-nsa-benetel
test-panos
test-x310-perf
test_nsa_gtpu_fix
test_rt-fix_phy-test
testing_2symb_pdcch
testing_with_external_txdata
thread-pool
tools_5Gadapt
tp-ota-test
trx_thread_param
trx_write_thread
ue-csi
ue-dci-false-detection
ue-fixes
ue-fixes-ota
ue-pdsch-pusch-parallel
ue-race-fix
ue-updates-runel-test
ue_adjust_gain
ue_beam_selection
ue_dlsch-multi-threading
ue_dlsch_decoding_ldpc_offload
ue_nfapi_mch
uhd_priority_set_cleanup
ul-freq-iq-samps-to-file
ul_dl_dci_same_slot
ul_harq
ulsch_decode_mthread
ulsim_changes
update-to-2019-march-june-release
usrp_fix_adc_shift_and_pps_sync
usrp_gpio_test
usrp_stop_cleanly
usrp_x400
wf-sa-rrc
wf_testc
wireshark-T-hack-ueid
wireshark-log-scheduling-requests
wk11-with-phytest
x2-endc-processing
x2_handle_sctp_shutdown
xiangwab
xiangwan
xw2
yihongzheng_srb
zzs
2021.wk14_a
2021.wk13_d
2021.wk13_c
2021.w30
2021.w29
2021.w28
2021.w27
2021.w26
2021.w25
2021.w24
2021.w23
2021.w22
2021.w20
2021.w19
2021.w18_b
2021.w18_a
2021.w17_b
2021.w16
2021.w15
2021.w14
2021.w13_a
2021.w12
2021.w11
2021.w10
2021.w09
2021.w08
2021.w06
2021.w05
2021.w04
2021.w02
2020.w51_2
2020.w51
2020.w50
2020.w49
2020.w48_2
2020.w48
2020.w47
2020.w46_2
2020.w46
2020.w45_2
2020.w45
2020.w44
2020.w42_2
2020.w42
2020.w41
2020.w39
2020.w38
2020.w37
2020.w36
2020.w34
2020.w33
2020.w31
2020.w30
2020.w29
2020.w28
2020.w26
2020.w25
2020.w24
2020.w23
2020.w22
2020.w19
2020.w17
2020.w16
2020.w15
2020.w11
2020.w09
2020.w06
2020.w05
2020.w04
2020.w03
nr-ip-over-lte
nr-ip-over-lte-v.1.5
nr-ip-over-lte-v.1.4
nr-ip-over-lte-v.1.3
nr-ip-over-lte-v.1.2
nr-ip-over-lte-v.1.1
nr-ip-over-lte-v.1.0
develop-nr-2020w03
develop-nr-2020w02
develop-nr-2019w51
develop-nr-2019w50
develop-nr-2019w48
develop-nr-2019w47
develop-nr-2019w45
develop-nr-2019w43
develop-nr-2019w42
develop-nr-2019w40
develop-nr-2019w28
develop-nr-2019w23
benetel_phase_rotation
benetel_gnb_rel_2.0
benetel_gnb_rel_1.0
benetel_enb_rel_2.0
benetel_enb_rel_1.0
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cmake_targets/CMakeLists.txt
cmake_targets/CMakeLists.txt
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cmake_targets/build_oai
cmake_targets/build_oai
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openair1/SIMULATION/NR_PHY/ulschsim.c
openair1/SIMULATION/NR_PHY/ulschsim.c
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cmake_targets/CMakeLists.txt
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aadc2825
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@@ -2557,6 +2557,9 @@ add_executable(nr_dlsim
${
T_SOURCE
}
)
target_link_libraries
(
nr_dlsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB SCHED_NR_UE_LIB MAC_NR MAC_UE_NR RRC_LIB NR_RRC_LIB CONFIG_LIB L2_NR -Wl,--end-group m pthread
${
ATLAS_LIBRARIES
}
${
T_LIB
}
dl
)
add_executable
(
nr_ulschsim
${
OPENAIR1_DIR
}
/SIMULATION/NR_PHY/ulschsim.c
${
T_SOURCE
}
)
target_link_libraries
(
nr_ulschsim -Wl,--start-group UTIL SIMU PHY_COMMON PHY_NR PHY_NR_UE SCHED_NR_LIB CONFIG_LIB -Wl,--end-group m pthread
${
ATLAS_LIBRARIES
}
${
T_LIB
}
dl
)
foreach
(
myExe dlsim dlsim_tm7 ulsim pbchsim scansim mbmssim pdcchsim pucchsim prachsim syncsim
)
...
...
This diff is collapsed.
Click to expand it.
cmake_targets/build_oai
View file @
aadc2825
...
...
@@ -691,7 +691,7 @@ function main() {
echo_info
"Compiling unitary tests simulators"
# TODO: fix: dlsim_tm4 pucchsim prachsim pdcchsim pbchsim mbmssim
#simlist="dlsim_tm4 dlsim ulsim pucchsim prachsim pdcchsim pbchsim mbmssim"
simlist
=
"dlsim ulsim polartest ldpctest nr_pbchsim nr_dlschsim nr_dlsim"
simlist
=
"dlsim ulsim polartest ldpctest nr_pbchsim nr_dlschsim nr_dlsim
nr_ulschsim
"
for
f
in
$simlist
;
do
compilations
\
phy_simulators
$f
\
...
...
This diff is collapsed.
Click to expand it.
openair1/SIMULATION/NR_PHY/ulschsim.c
0 → 100644
View file @
aadc2825
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.1 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
#include <string.h>
#include <math.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <sys/mman.h>
#include "common/config/config_userapi.h"
#include "common/utils/LOG/log.h"
#include "common/ran_context.h"
#include "SIMULATION/TOOLS/sim.h"
#include "SIMULATION/RF/rf.h"
#include "PHY/types.h"
#include "PHY/defs_nr_common.h"
#include "PHY/defs_nr_UE.h"
#include "PHY/defs_gNB.h"
#include "PHY/INIT/phy_init.h"
#include "PHY/NR_REFSIG/refsig_defs_ue.h"
#include "PHY/NR_REFSIG/nr_mod_table.h"
#include "PHY/MODULATION/modulation_eNB.h"
#include "PHY/MODULATION/modulation_UE.h"
#include "PHY/NR_TRANSPORT/nr_transport.h"
#include "PHY/NR_TRANSPORT/nr_dlsch.h"
#include "PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h"
#include "SCHED_NR/sched_nr.h"
//#include "PHY/MODULATION/modulation_common.h"
//#include "common/config/config_load_configmodule.h"
//#include "UTIL/LISTS/list.h"
//#include "common/ran_context.h"
//#define DEBUG_DLSCHSIM
PHY_VARS_gNB
*
gNB
;
PHY_VARS_NR_UE
*
UE
;
RAN_CONTEXT_t
RC
;
double
cpuf
;
// dummy functions
int
nfapi_mode
=
0
;
int
oai_nfapi_hi_dci0_req
(
nfapi_hi_dci0_request_t
*
hi_dci0_req
)
{
return
(
0
);
}
int
oai_nfapi_tx_req
(
nfapi_tx_request_t
*
tx_req
)
{
return
(
0
);
}
int
oai_nfapi_dl_config_req
(
nfapi_dl_config_request_t
*
dl_config_req
)
{
return
(
0
);
}
int
oai_nfapi_ul_config_req
(
nfapi_ul_config_request_t
*
ul_config_req
)
{
return
(
0
);
}
int
oai_nfapi_nr_dl_config_req
(
nfapi_nr_dl_config_request_t
*
dl_config_req
)
{
return
(
0
);
}
uint32_t
from_nrarfcn
(
int
nr_bandP
,
uint32_t
dl_earfcn
)
{
return
(
0
);
}
int32_t
get_uldl_offset
(
int
eutra_bandP
)
{
return
(
0
);
}
NR_IF_Module_t
*
NR_IF_Module_init
(
int
Mod_id
)
{
return
(
NULL
);
}
void
exit_function
(
const
char
*
file
,
const
char
*
function
,
const
int
line
,
const
char
*
s
)
{
const
char
*
msg
=
s
==
NULL
?
"no comment"
:
s
;
printf
(
"Exiting at: %s:%d %s(), %s
\n
"
,
file
,
line
,
function
,
msg
);
exit
(
-
1
);
}
// needed for some functions
PHY_VARS_NR_UE
*
PHY_vars_UE_g
[
1
][
1
]
=
{
{
NULL
}
};
uint16_t
n_rnti
=
0x1234
;
char
quantize
(
double
D
,
double
x
,
unsigned
char
B
)
{
double
qxd
;
short
maxlev
;
qxd
=
floor
(
x
/
D
);
maxlev
=
1
<<
(
B
-
1
);
//(char)(pow(2,B-1));
//printf("x=%f,qxd=%f,maxlev=%d\n",x,qxd, maxlev);
if
(
qxd
<=
-
maxlev
)
qxd
=
-
maxlev
;
else
if
(
qxd
>=
maxlev
)
qxd
=
maxlev
-
1
;
return
((
char
)
qxd
);
}
int
main
(
int
argc
,
char
**
argv
)
{
char
c
;
int
i
;
//,j,l,aa;
double
SNR
,
SNR_lin
,
snr0
=
-
2
.
0
,
snr1
=
2
.
0
;
double
snr_step
=
0
.
1
;
uint8_t
snr1set
=
0
;
int
**
txdata
;
double
**
s_re
,
**
s_im
,
**
r_re
,
**
r_im
;
// int sync_pos, sync_pos_slot;
// FILE *rx_frame_file;
FILE
*
output_fd
=
NULL
;
uint8_t
write_output_file
=
0
;
// int subframe_offset;
// char fname[40], vname[40];
int
trial
,
n_trials
=
1
,
n_errors
=
0
,
n_false_positive
=
0
;
uint8_t
transmission_mode
=
1
,
n_tx
=
1
,
n_rx
=
1
;
uint16_t
Nid_cell
=
0
;
channel_desc_t
*
gNB2UE
;
uint8_t
extended_prefix_flag
=
0
;
int8_t
interf1
=
-
21
,
interf2
=
-
21
;
FILE
*
input_fd
=
NULL
,
*
pbch_file_fd
=
NULL
;
//char input_val_str[50],input_val_str2[50];
//uint16_t NB_RB=25;
SCM_t
channel_model
=
AWGN
;
//Rayleigh1_anticorr;
uint16_t
N_RB_DL
=
106
,
mu
=
1
;
unsigned
char
frame_type
=
0
;
unsigned
char
pbch_phase
=
0
;
int
frame
=
0
,
subframe
=
0
;
int
frame_length_complex_samples
;
//int frame_length_complex_samples_no_prefix;
NR_DL_FRAME_PARMS
*
frame_parms
;
//nfapi_nr_config_request_t *gNB_config;
uint8_t
Kmimo
=
0
;
uint32_t
Nsoft
=
0
;
double
sigma
;
unsigned
char
qbits
=
8
;
int
ret
;
//int run_initial_sync=0;
int
loglvl
=
OAILOG_WARNING
;
float
target_error_rate
=
0
.
01
;
uint16_t
nb_symb_sch
=
12
;
uint16_t
nb_rb
=
50
;
uint8_t
Imcs
=
9
;
cpuf
=
get_cpu_freq_GHz
();
if
(
load_configmodule
(
argc
,
argv
)
==
0
)
{
exit_fun
(
"[SOFTMODEM] Error, configuration module init failed
\n
"
);
}
//logInit();
randominit
(
0
);
while
((
c
=
getopt
(
argc
,
argv
,
"df:hpg:i:j:n:l:m:r:s:S:y:z:N:F:R:P:"
))
!=
-
1
)
{
switch
(
c
)
{
case
'f'
:
write_output_file
=
1
;
output_fd
=
fopen
(
optarg
,
"w"
);
if
(
output_fd
==
NULL
)
{
printf
(
"Error opening %s
\n
"
,
optarg
);
exit
(
-
1
);
}
break
;
case
'd'
:
frame_type
=
1
;
break
;
case
'g'
:
switch
((
char
)
*
optarg
)
{
case
'A'
:
channel_model
=
SCM_A
;
break
;
case
'B'
:
channel_model
=
SCM_B
;
break
;
case
'C'
:
channel_model
=
SCM_C
;
break
;
case
'D'
:
channel_model
=
SCM_D
;
break
;
case
'E'
:
channel_model
=
EPA
;
break
;
case
'F'
:
channel_model
=
EVA
;
break
;
case
'G'
:
channel_model
=
ETU
;
break
;
default:
msg
(
"Unsupported channel model!
\n
"
);
exit
(
-
1
);
}
break
;
case
'i'
:
interf1
=
atoi
(
optarg
);
break
;
case
'j'
:
interf2
=
atoi
(
optarg
);
break
;
case
'n'
:
n_trials
=
atoi
(
optarg
);
break
;
case
's'
:
snr0
=
atof
(
optarg
);
msg
(
"Setting SNR0 to %f
\n
"
,
snr0
);
break
;
case
'S'
:
snr1
=
atof
(
optarg
);
snr1set
=
1
;
msg
(
"Setting SNR1 to %f
\n
"
,
snr1
);
break
;
case
'p'
:
extended_prefix_flag
=
1
;
break
;
/*
case 'r':
ricean_factor = pow(10,-.1*atof(optarg));
if (ricean_factor>1) {
printf("Ricean factor must be between 0 and 1\n");
exit(-1);
}
break;
*/
case
'y'
:
n_tx
=
atoi
(
optarg
);
if
((
n_tx
==
0
)
||
(
n_tx
>
2
))
{
msg
(
"Unsupported number of tx antennas %d
\n
"
,
n_tx
);
exit
(
-
1
);
}
break
;
case
'z'
:
n_rx
=
atoi
(
optarg
);
if
((
n_rx
==
0
)
||
(
n_rx
>
2
))
{
msg
(
"Unsupported number of rx antennas %d
\n
"
,
n_rx
);
exit
(
-
1
);
}
break
;
case
'N'
:
Nid_cell
=
atoi
(
optarg
);
break
;
case
'R'
:
N_RB_DL
=
atoi
(
optarg
);
break
;
case
'F'
:
input_fd
=
fopen
(
optarg
,
"r"
);
if
(
input_fd
==
NULL
)
{
printf
(
"Problem with filename %s
\n
"
,
optarg
);
exit
(
-
1
);
}
break
;
case
'P'
:
pbch_phase
=
atoi
(
optarg
);
if
(
pbch_phase
>
3
)
printf
(
"Illegal PBCH phase (0-3) got %d
\n
"
,
pbch_phase
);
break
;
case
'm'
:
Imcs
=
atoi
(
optarg
);
break
;
case
'l'
:
nb_symb_sch
=
atoi
(
optarg
);
break
;
case
'r'
:
nb_rb
=
atoi
(
optarg
);
break
;
case
'x'
:
transmission_mode
=
atoi
(
optarg
);
break
;
default:
case
'h'
:
printf
(
"%s -h(elp) -p(extended_prefix) -N cell_id -f output_filename -F input_filename -g channel_model -n n_frames -t Delayspread -s snr0 -S snr1 -x transmission_mode -y TXant -z RXant -i Intefrence0 -j Interference1 -A interpolation_file -C(alibration offset dB) -N CellId
\n
"
,
argv
[
0
]);
printf
(
"-h This message
\n
"
);
printf
(
"-p Use extended prefix mode
\n
"
);
printf
(
"-d Use TDD
\n
"
);
printf
(
"-n Number of frames to simulate
\n
"
);
printf
(
"-s Starting SNR, runs from SNR0 to SNR0 + 5 dB. If n_frames is 1 then just SNR is simulated
\n
"
);
printf
(
"-S Ending SNR, runs from SNR0 to SNR1
\n
"
);
printf
(
"-t Delay spread for multipath channel
\n
"
);
printf
(
"-g [A,B,C,D,E,F,G] Use 3GPP SCM (A,B,C,D) or 36-101 (E-EPA,F-EVA,G-ETU) models (ignores delay spread and Ricean factor)
\n
"
);
printf
(
"-x Transmission mode (1,2,6 for the moment)
\n
"
);
printf
(
"-y Number of TX antennas used in eNB
\n
"
);
printf
(
"-z Number of RX antennas used in UE
\n
"
);
printf
(
"-i Relative strength of first intefering eNB (in dB) - cell_id mod 3 = 1
\n
"
);
printf
(
"-j Relative strength of second intefering eNB (in dB) - cell_id mod 3 = 2
\n
"
);
printf
(
"-N Nid_cell
\n
"
);
printf
(
"-R N_RB_DL
\n
"
);
printf
(
"-O oversampling factor (1,2,4,8,16)
\n
"
);
printf
(
"-A Interpolation_filname Run with Abstraction to generate Scatter plot using interpolation polynomial in file
\n
"
);
// printf("-C Generate Calibration information for Abstraction (effective SNR adjustment to remove Pe bias w.r.t. AWGN)\n");
printf
(
"-f Output filename (.txt format) for Pe/SNR results
\n
"
);
printf
(
"-F Input filename (.txt format) for RX conformance testing
\n
"
);
exit
(
-
1
);
break
;
}
}
logInit
();
set_glog
(
loglvl
);
T_stdout
=
1
;
if
(
snr1set
==
0
)
snr1
=
snr0
+
10
;
gNB2UE
=
new_channel_desc_scm
(
n_tx
,
n_rx
,
channel_model
,
61.44e6
,
//N_RB2sampling_rate(N_RB_DL),
40e6
,
//N_RB2channel_bandwidth(N_RB_DL),
0
,
0
,
0
);
if
(
gNB2UE
==
NULL
)
{
msg
(
"Problem generating channel model. Exiting.
\n
"
);
exit
(
-
1
);
}
RC
.
gNB
=
(
PHY_VARS_gNB
**
*
)
malloc
(
sizeof
(
PHY_VARS_gNB
**
));
RC
.
gNB
[
0
]
=
(
PHY_VARS_gNB
**
)
malloc
(
sizeof
(
PHY_VARS_gNB
*
));
RC
.
gNB
[
0
][
0
]
=
malloc
(
sizeof
(
PHY_VARS_gNB
));
gNB
=
RC
.
gNB
[
0
][
0
];
//gNB_config = &gNB->gNB_config;
frame_parms
=
&
gNB
->
frame_parms
;
//to be initialized I suppose (maybe not necessary for PBCH)
frame_parms
->
nb_antennas_tx
=
n_tx
;
frame_parms
->
nb_antennas_rx
=
n_rx
;
frame_parms
->
N_RB_DL
=
N_RB_DL
;
frame_parms
->
Ncp
=
extended_prefix_flag
?
EXTENDED
:
NORMAL
;
crcTableInit
();
nr_phy_config_request_sim
(
gNB
,
N_RB_DL
,
N_RB_DL
,
mu
,
Nid_cell
);
phy_init_nr_gNB
(
gNB
,
0
,
0
);
//init_eNB_afterRU();
frame_length_complex_samples
=
frame_parms
->
samples_per_subframe
;
//frame_length_complex_samples_no_prefix = frame_parms->samples_per_subframe_wCP;
s_re
=
malloc
(
2
*
sizeof
(
double
*
));
s_im
=
malloc
(
2
*
sizeof
(
double
*
));
r_re
=
malloc
(
2
*
sizeof
(
double
*
));
r_im
=
malloc
(
2
*
sizeof
(
double
*
));
txdata
=
malloc
(
2
*
sizeof
(
int
*
));
for
(
i
=
0
;
i
<
2
;
i
++
)
{
s_re
[
i
]
=
malloc
(
frame_length_complex_samples
*
sizeof
(
double
));
bzero
(
s_re
[
i
],
frame_length_complex_samples
*
sizeof
(
double
));
s_im
[
i
]
=
malloc
(
frame_length_complex_samples
*
sizeof
(
double
));
bzero
(
s_im
[
i
],
frame_length_complex_samples
*
sizeof
(
double
));
r_re
[
i
]
=
malloc
(
frame_length_complex_samples
*
sizeof
(
double
));
bzero
(
r_re
[
i
],
frame_length_complex_samples
*
sizeof
(
double
));
r_im
[
i
]
=
malloc
(
frame_length_complex_samples
*
sizeof
(
double
));
bzero
(
r_im
[
i
],
frame_length_complex_samples
*
sizeof
(
double
));
txdata
[
i
]
=
malloc
(
frame_length_complex_samples
*
sizeof
(
int
));
bzero
(
r_re
[
i
],
frame_length_complex_samples
*
sizeof
(
int
));
}
if
(
pbch_file_fd
!=
NULL
)
{
load_pbch_desc
(
pbch_file_fd
);
}
/* for (int k=0; k<2; k++) {
// Create transport channel structures for 2 transport blocks (MIMO)
for (i=0; i<2; i++) {
gNB->dlsch[k][i] = new_gNB_dlsch(Kmimo,8,Nsoft,0,frame_parms,gNB_config);
if (!gNB->dlsch[k][i]) {
printf("Can't get eNB dlsch structures\n");
exit(-1);
}
gNB->dlsch[k][i]->Nsoft = 10;
gNB->dlsch[k][i]->rnti = n_rnti+k;
}
}*/
//configure UE
UE
=
malloc
(
sizeof
(
PHY_VARS_NR_UE
));
memcpy
(
&
UE
->
frame_parms
,
frame_parms
,
sizeof
(
NR_DL_FRAME_PARMS
));
//phy_init_nr_top(frame_parms);
if
(
init_nr_ue_signal
(
UE
,
1
,
0
)
!=
0
)
{
printf
(
"Error at UE NR initialisation
\n
"
);
exit
(
-
1
);
}
//nr_init_frame_parms_ue(&UE->frame_parms);
//init_nr_ue_transport(UE, 0);
for
(
int
sf
=
0
;
sf
<
2
;
sf
++
)
{
for
(
i
=
0
;
i
<
2
;
i
++
)
{
UE
->
dlsch
[
sf
][
0
][
i
]
=
new_nr_ue_dlsch
(
Kmimo
,
8
,
Nsoft
,
5
,
N_RB_DL
,
0
);
if
(
!
UE
->
dlsch
[
sf
][
0
][
i
])
{
printf
(
"Can't get ue dlsch structures
\n
"
);
exit
(
-
1
);
}
UE
->
dlsch
[
sf
][
0
][
i
]
->
rnti
=
n_rnti
;
}
}
UE
->
dlsch_SI
[
0
]
=
new_nr_ue_dlsch
(
1
,
1
,
Nsoft
,
5
,
N_RB_DL
,
0
);
UE
->
dlsch_ra
[
0
]
=
new_nr_ue_dlsch
(
1
,
1
,
Nsoft
,
5
,
N_RB_DL
,
0
);
unsigned
char
harq_pid
=
0
;
//dlsch->harq_ids[subframe];
NR_gNB_DLSCH_t
*
dlsch
=
gNB
->
dlsch
[
0
][
0
];
nfapi_nr_dl_config_dlsch_pdu_rel15_t
*
rel15
=
&
dlsch
->
harq_processes
[
harq_pid
]
->
dlsch_pdu
.
dlsch_pdu_rel15
;
//time_stats_t *rm_stats, *te_stats, *i_stats;
uint8_t
is_crnti
=
0
,
llr8_flag
=
0
;
unsigned
int
TBS
=
8424
;
unsigned
int
available_bits
;
uint8_t
nb_re_dmrs
=
6
;
uint16_t
length_dmrs
=
1
;
unsigned
char
mod_order
;
uint8_t
Nl
=
1
;
uint8_t
rvidx
=
0
;
dlsch
->
rnti
=
1
;
/*dlsch->harq_processes[0]->mcs = Imcs;
dlsch->harq_processes[0]->rvidx = rvidx;*/
//printf("dlschsim harqid %d nb_rb %d, mscs %d\n",dlsch->harq_ids[subframe],
// dlsch->harq_processes[0]->nb_rb,dlsch->harq_processes[0]->mcs,dlsch->harq_processes[0]->Nl);
mod_order
=
nr_get_Qm
(
Imcs
,
1
);
available_bits
=
nr_get_G
(
nb_rb
,
nb_symb_sch
,
nb_re_dmrs
,
length_dmrs
,
mod_order
,
1
);
TBS
=
nr_compute_tbs
(
Imcs
,
nb_rb
,
nb_symb_sch
,
nb_re_dmrs
,
length_dmrs
,
Nl
);
printf
(
"available bits %d TBS %d mod_order %d
\n
"
,
available_bits
,
TBS
,
mod_order
);
//dlsch->harq_ids[subframe]= 0;
rel15
->
n_prb
=
nb_rb
;
rel15
->
nb_symbols
=
nb_symb_sch
;
rel15
->
modulation_order
=
mod_order
;
rel15
->
nb_layers
=
Nl
;
rel15
->
nb_re_dmrs
=
nb_re_dmrs
;
rel15
->
transport_block_size
=
TBS
;
double
*
modulated_input
=
malloc16
(
sizeof
(
double
)
*
16
*
68
*
384
);
short
*
channel_output_fixed
=
malloc16
(
sizeof
(
short
)
*
16
*
68
*
384
);
short
*
channel_output_uncoded
=
malloc16
(
sizeof
(
unsigned
short
)
*
16
*
68
*
384
);
double
errors_bit_uncoded
=
0
;
unsigned
char
*
estimated_output
;
unsigned
char
*
estimated_output_bit
;
unsigned
char
*
test_input_bit
;
unsigned
int
errors_bit
=
0
;
test_input_bit
=
(
unsigned
char
*
)
malloc16
(
sizeof
(
unsigned
char
)
*
16
*
68
*
384
);
estimated_output
=
(
unsigned
char
*
)
malloc16
(
sizeof
(
unsigned
char
)
*
16
*
68
*
384
);
estimated_output_bit
=
(
unsigned
char
*
)
malloc16
(
sizeof
(
unsigned
char
)
*
16
*
68
*
384
);
NR_UE_DLSCH_t
*
dlsch0_ue
=
UE
->
dlsch
[
0
][
0
][
0
];
NR_DL_UE_HARQ_t
*
harq_process
=
dlsch0_ue
->
harq_processes
[
harq_pid
];
harq_process
->
mcs
=
Imcs
;
harq_process
->
Nl
=
Nl
;
harq_process
->
nb_rb
=
nb_rb
;
harq_process
->
Qm
=
mod_order
;
harq_process
->
rvidx
=
rvidx
;
printf
(
"harq process ue mcs = %d Qm = %d, symb %d
\n
"
,
harq_process
->
mcs
,
harq_process
->
Qm
,
nb_symb_sch
);
unsigned
char
*
test_input
;
test_input
=
(
unsigned
char
*
)
malloc16
(
sizeof
(
unsigned
char
)
*
TBS
/
8
);
for
(
i
=
0
;
i
<
TBS
/
8
;
i
++
)
test_input
[
i
]
=
(
unsigned
char
)
rand
();
estimated_output
=
harq_process
->
b
;
#ifdef DEBUG_DLSCHSIM
for
(
i
=
0
;
i
<
TBS
/
8
;
i
++
)
printf
(
"test_input[i]=%d
\n
"
,
test_input
[
i
]);
#endif
/*for (int i=0; i<TBS/8; i++)
printf("test input[%d]=%d \n",i,test_input[i]);*/
//printf("crc32: [0]->0x%08x\n",crc24c(test_input, 32));
// generate signal
if
(
input_fd
==
NULL
)
{
nr_dlsch_encoding
(
test_input
,
subframe
,
dlsch
,
frame_parms
);
}
for
(
SNR
=
snr0
;
SNR
<
snr1
;
SNR
+=
snr_step
)
{
n_errors
=
0
;
n_false_positive
=
0
;
for
(
trial
=
0
;
trial
<
n_trials
;
trial
++
)
{
errors_bit_uncoded
=
0
;
for
(
i
=
0
;
i
<
available_bits
;
i
++
)
{
#ifdef DEBUG_CODER
if
((
i
&
0xf
)
==
0
)
printf
(
"
\n
e %d..%d: "
,
i
,
i
+
15
);
#endif
//if (i<16)
// printf("encoder output f[%d] = %d\n",i,dlsch->harq_processes[0]->f[i]);
if
(
dlsch
->
harq_processes
[
0
]
->
f
[
i
]
==
0
)
modulated_input
[
i
]
=
1
.
0
;
///sqrt(2); //QPSK
else
modulated_input
[
i
]
=
-
1
.
0
;
///sqrt(2);
//if (i<16) printf("modulated_input[%d] = %d\n",i,modulated_input[i]);
//SNR =10;
SNR_lin
=
pow
(
10
,
SNR
/
10
.
0
);
sigma
=
1
.
0
/
sqrt
(
2
*
SNR_lin
);
channel_output_fixed
[
i
]
=
(
short
)
quantize
(
sigma
/
4
.
0
/
4
.
0
,
modulated_input
[
i
]
+
sigma
*
gaussdouble
(
0
.
0
,
1
.
0
),
qbits
);
//channel_output_fixed[i] = (char)quantize8bit(sigma/4.0,(2.0*modulated_input[i]) - 1.0 + sigma*gaussdouble(0.0,1.0));
//printf("llr[%d]=%d\n",i,channel_output_fixed[i]);
//printf("channel_output_fixed[%d]: %d\n",i,channel_output_fixed[i]);
//channel_output_fixed[i] = (char)quantize(1,channel_output_fixed[i],qbits);
//if (i<16) printf("channel_output_fixed[%d] = %d\n",i,channel_output_fixed[i]);
//Uncoded BER
if
(
channel_output_fixed
[
i
]
<
0
)
channel_output_uncoded
[
i
]
=
1
;
//QPSK demod
else
channel_output_uncoded
[
i
]
=
0
;
if
(
channel_output_uncoded
[
i
]
!=
dlsch
->
harq_processes
[
harq_pid
]
->
f
[
i
])
errors_bit_uncoded
=
errors_bit_uncoded
+
1
;
}
//if (errors_bit_uncoded>10)
//printf("errors bits uncoded %f\n", errors_bit_uncoded);
#ifdef DEBUG_CODER
printf
(
"
\n
"
);
exit
(
-
1
);
#endif
ret
=
nr_dlsch_decoding
(
UE
,
channel_output_fixed
,
&
UE
->
frame_parms
,
dlsch0_ue
,
dlsch0_ue
->
harq_processes
[
0
],
frame
,
nb_symb_sch
,
subframe
,
harq_pid
,
is_crnti
,
llr8_flag
);
if
(
ret
>
dlsch0_ue
->
max_ldpc_iterations
)
n_errors
++
;
//count errors
errors_bit
=
0
;
for
(
i
=
0
;
i
<
TBS
;
i
++
)
{
estimated_output_bit
[
i
]
=
(
dlsch0_ue
->
harq_processes
[
0
]
->
b
[
i
/
8
]
&
(
1
<<
(
i
&
7
)))
>>
(
i
&
7
);
test_input_bit
[
i
]
=
(
test_input
[
i
/
8
]
&
(
1
<<
(
i
&
7
)))
>>
(
i
&
7
);
// Further correct for multiple segments
if
(
estimated_output_bit
[
i
]
!=
test_input_bit
[
i
])
{
errors_bit
++
;
//printf("estimated bits error occurs @%d ",i);
}
}
if
(
errors_bit
>
0
)
{
n_false_positive
++
;
if
(
n_trials
==
1
)
printf
(
"errors_bit %d (trial %d)
\n
"
,
errors_bit
,
trial
);
}
}
printf
(
"SNR %f, BLER %f (false positive %f)
\n
"
,
SNR
,
(
float
)
n_errors
/
(
float
)
n_trials
,
(
float
)
n_false_positive
/
(
float
)
n_trials
);
if
((
float
)
n_errors
/
(
float
)
n_trials
<
target_error_rate
)
{
printf
(
"PDSCH test OK
\n
"
);
break
;
}
}
/*LOG_M("txsigF0.m","txsF0", gNB->common_vars.txdataF[0],frame_length_complex_samples_no_prefix,1,1);
if (gNB->frame_parms.nb_antennas_tx>1)
LOG_M("txsigF1.m","txsF1", gNB->common_vars.txdataF[1],frame_length_complex_samples_no_prefix,1,1);*/
//TODO: loop over slots
/*for (aa=0; aa<gNB->frame_parms.nb_antennas_tx; aa++) {
if (gNB_config->subframe_config.dl_cyclic_prefix_type.value == 1) {
PHY_ofdm_mod(gNB->common_vars.txdataF[aa],
txdata[aa],
frame_parms->ofdm_symbol_size,
12,
frame_parms->nb_prefix_samples,
CYCLIC_PREFIX);
} else {
nr_normal_prefix_mod(gNB->common_vars.txdataF[aa],
txdata[aa],
14,
frame_parms);
}
}
LOG_M("txsig0.m","txs0", txdata[0],frame_length_complex_samples,1,1);
if (gNB->frame_parms.nb_antennas_tx>1)
LOG_M("txsig1.m","txs1", txdata[1],frame_length_complex_samples,1,1);
for (i=0; i<frame_length_complex_samples; i++) {
for (aa=0; aa<frame_parms->nb_antennas_tx; aa++) {
r_re[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)]);
r_im[aa][i] = ((double)(((short *)txdata[aa]))[(i<<1)+1]);
}
}*/
for
(
i
=
0
;
i
<
2
;
i
++
)
{
printf
(
"gNB %d
\n
"
,
i
);
free_gNB_dlsch
(
gNB
->
dlsch
[
0
][
i
]);
printf
(
"UE %d
\n
"
,
i
);
free_nr_ue_dlsch
(
UE
->
dlsch
[
0
][
0
][
i
]);
}
for
(
i
=
0
;
i
<
2
;
i
++
)
{
free
(
s_re
[
i
]);
free
(
s_im
[
i
]);
free
(
r_re
[
i
]);
free
(
r_im
[
i
]);
free
(
txdata
[
i
]);
}
free
(
s_re
);
free
(
s_im
);
free
(
r_re
);
free
(
r_im
);
free
(
txdata
);
if
(
output_fd
)
fclose
(
output_fd
);
if
(
input_fd
)
fclose
(
input_fd
);
return
(
n_errors
);
}
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