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wangjie
OpenXG-RAN
Commits
ab3794e6
Commit
ab3794e6
authored
4 years ago
by
rmagueta
Browse files
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Plain Diff
Improvements in RA-Msg2
parent
bb0507a8
xw2
512-dataplane-bug-in-l2nfapi_nos1
FR2_NSA
Fix_SA_SIB1
NRUE_usedlschparallel
NR_2port_CSIRS
NR_CSIRS_tomerge
NR_F1C_F1U_extensions
NR_FR2_initsync_fixes
NR_RRCReconfiguration_BWP
NR_SA_F1AP_5GRECORDS
NR_SA_F1AP_5GRECORDS-USIM
NR_SA_F1AP_5GRECORDS-wf-0623
NR_SA_F1AP_5GRECORDS_lts
NR_UE_CONFIG_REQ_FIXES
NR_UE_PUCCH_bugfixes
NR_UE_SA
NR_UE_SSB_meas
NR_UE_rework_test
NR_UE_reworking_UCI_procedures
NR_cleanup_PUCCH_resources
NR_gNB_initial_MIB_fix
NR_multiplexing_HARQ_CSI_PUCCH
NR_new_ul_antennaports
NR_phytest_bugfixes
NR_reworking_UL_antennaports
NR_scheduling_CSIRS
NR_scheduling_request
RFquality
Test_SA_5GREC
add-ru-docker-image
avxllr
bandwidth-testing
benetel_config_file_fix
benetel_dpdk20
bugfix-nr-t-reordering
bugfix_gnb_rt_stats_html
ci-add-sabox-support
ci-fix-module-ul-iperf
ci_benetel_longrun_limits
ci_fix_iperf_for_module
ci_hotfix_module_ue_ip_address
ci_improve_module_ctl
ci_nsa_2x2_implem
ci_nsa_benetel
ci_nsa_fixes
ci_nsa_pipes_improve
ci_nsa_test_integration_2021_wk19
ci_nsa_traces
ci_nsa_uplink
ci_quectel_support
ci_sa_rfsim_test
ci_solve_ul_for_module
ci_test_5GREC
ci_test_nsa_2x2
ci_test_nsa_fix_quectel_nic
ci_test_nsa_on_develop
ci_testinfra_as_code
ci_update_build_nasmesh
code-cleanup-20210716
debug-UL-5GRECORDS
debug_UL_signal
detached-w16-test
develop
develop-CBRA-v3
develop-CCE
develop-NR_SA_F1AP_5GRECORDS
develop-NR_SA_F1AP_5GRECORDS-abs
develop-NR_SA_F1AP_5GRECORDS-hs
develop-NR_SA_F1AP_5GRECORDS-hs1
develop-NR_SA_F1AP_5GRECORDS-lts
develop-NR_SA_F1AP_5GRECORDS-lts-wf
develop-NR_SA_F1AP_5GRECORDS-v3
develop-NR_SA_F1AP_5GRECORDS_100M
develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA
develop-NR_SA_F1AP_5GRECORDS_lfq_0607
develop-NSA_SA_fixes
develop-SA-CBRA
develop-SA-CBRA-CUDU
develop-SA-CBRA-Msg5
develop-SA-CBRA-ulsch-lts
develop-aw2sori
develop-wf-du
develop_fpga_ldpc
docker-improvements-2021-april
dongzhanyi-zte-develop1
episys-merge
fedora-gen-kernel-fix
fix-check
fix-compile
fix-lte-ue-modem-in-docker-container
fix-physim-deploy
fix-physim-run-script-on-cluster
fix-realtime
fix-retransmission-rbg
fix_coreset_dmrs_idx
fix_nr_ulsim
fixgtpu
flexran-rtc-repo-is-public
gnb-realtime-hotfix
hack-bch-no-sched-sf-0
hack-exit-gnb-when-no-enb-nsa
integration_2020_wk15
integration_2021_wk13_b
integration_2021_wk13_b_fix_tdas
integration_2021_wk13_b_fixed
integration_2021_wk16
integration_2021_wk17_a
integration_2021_wk17_b
integration_2021_wk18_a
integration_2021_wk18_b
integration_2021_wk19
integration_2021_wk20_a
integration_2021_wk22
integration_2021_wk23
integration_2021_wk27
integration_2021_wk28
integration_2021_wk30
integration_2021_wk30_b
integration_w5GC_CBRA_test
ldpc_offload_t1
migrate-vm-pipeline-to-bionic
multiple_ssb_sib1_bugfix
nfapi_nr_arch_mod
nr-dl-mimo-2layer
nr-dmrs-fixes
nr-pdcp-benchmarking
nr-pdcp-small-bugfixes
nr-pdcp-srb-integrity
nr_improve_chanest
nr_ue_remove_high_speed_flag
oairu
phy-asan-fixes
physim-build-deploy
physim-deploy-handle-error-cases
prb_based_dl_channel_estimation
rh_ci_add_runtime_stats
rh_ci_add_uldlharq_stats
rh_ci_gsheet_rt_monitoring
rh_ci_nsa_test_n310
rh_ci_phy_test_improve
rh_ci_test_benetel
rh_ci_test_nsa
rh_ci_test_nsa_wk16
rh_ci_test_nsa_wk17_b
rh_ci_test_nsa_wk17b
rh_ci_test_rfsim_sa
scs_60_iisc
test-5GREC
test-nsa-benetel
test_nsa_gtpu_fix
test_rt-fix_phy-test
usrp_stop_cleanly
wf_testc
x2_handle_sctp_shutdown
2021.w30
2021.w29
2021.w28
2021.w27
2021.w26
2021.w25
2021.w24
2021.w23
2021.w22
2021.w20
2021.w19
2021.w18_b
2021.w18_a
2021.w17_b
2021.w16
2021.w15
benetel_gnb_rel_2.0
benetel_enb_rel_2.0
No related merge requests found
Changes
2
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Showing
2 changed files
with
60 additions
and
70 deletions
+60
-70
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+3
-3
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+57
-67
No files found.
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @
ab3794e6
...
@@ -654,8 +654,11 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
...
@@ -654,8 +654,11 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
}
else
{
}
else
{
if
(
ra
->
RA_window_cnt
>=
0
&&
rnti
==
ra
->
ra_rnti
){
if
(
ra
->
RA_window_cnt
>=
0
&&
rnti
==
ra
->
ra_rnti
){
dl_config
->
dl_config_list
[
dl_config
->
number_pdus
].
pdu_type
=
FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH
;
dl_config
->
dl_config_list
[
dl_config
->
number_pdus
].
pdu_type
=
FAPI_NR_DL_CONFIG_TYPE_RA_DLSCH
;
pdsch_config
->
dmrs_DownlinkForPDSCH_MappingTypeA
->
choice
.
setup
->
dmrs_AdditionalPosition
=
NULL
;
}
else
{
}
else
{
dl_config
->
dl_config_list
[
dl_config
->
number_pdus
].
pdu_type
=
FAPI_NR_DL_CONFIG_TYPE_DLSCH
;
dl_config
->
dl_config_list
[
dl_config
->
number_pdus
].
pdu_type
=
FAPI_NR_DL_CONFIG_TYPE_DLSCH
;
if
(
pdsch_config
->
dmrs_DownlinkForPDSCH_MappingTypeA
->
choice
.
setup
->
dmrs_AdditionalPosition
==
NULL
)
pdsch_config
->
dmrs_DownlinkForPDSCH_MappingTypeA
->
choice
.
setup
->
dmrs_AdditionalPosition
=
calloc
(
1
,
sizeof
(
*
pdsch_config
->
dmrs_DownlinkForPDSCH_MappingTypeA
->
choice
.
setup
->
dmrs_AdditionalPosition
));
}
}
if
(
(
ra
->
RA_window_cnt
>=
0
&&
rnti
==
ra
->
ra_rnti
)
||
(
rnti
==
ra
->
t_crnti
)
)
{
if
(
(
ra
->
RA_window_cnt
>=
0
&&
rnti
==
ra
->
ra_rnti
)
||
(
rnti
==
ra
->
t_crnti
)
)
{
...
@@ -667,9 +670,6 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
...
@@ -667,9 +670,6 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
dlsch_config_pdu_1_0
->
SubcarrierSpacing
=
mac
->
DLbwp
[
0
]
->
bwp_Common
->
genericParameters
.
subcarrierSpacing
;
dlsch_config_pdu_1_0
->
SubcarrierSpacing
=
mac
->
DLbwp
[
0
]
->
bwp_Common
->
genericParameters
.
subcarrierSpacing
;
}
}
if
(
pdsch_config
->
dmrs_DownlinkForPDSCH_MappingTypeA
->
choice
.
setup
->
dmrs_AdditionalPosition
==
NULL
)
pdsch_config
->
dmrs_DownlinkForPDSCH_MappingTypeA
->
choice
.
setup
->
dmrs_AdditionalPosition
=
calloc
(
1
,
sizeof
(
*
pdsch_config
->
dmrs_DownlinkForPDSCH_MappingTypeA
->
choice
.
setup
->
dmrs_AdditionalPosition
));
BWPSize
=
n_RB_DLBWP
;
BWPSize
=
n_RB_DLBWP
;
}
}
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
ab3794e6
...
@@ -832,19 +832,10 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -832,19 +832,10 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
if
((
ra
->
Msg2_frame
==
frameP
)
&&
(
ra
->
Msg2_slot
==
slotP
))
{
if
((
ra
->
Msg2_frame
==
frameP
)
&&
(
ra
->
Msg2_slot
==
slotP
))
{
int
mcsIndex
=
0
;
uint8_t
time_domain_assignment
=
0
;
int
startSymbolAndLength
=
53
;
uint8_t
mcsIndex
=
0
;
int
StartSymbolIndex
=
2
;
int
NrOfSymbols
=
12
;
int
StartSymbolIndex_tmp
=
0
;
int
NrOfSymbols_tmp
=
0
;
int
x_Overhead
=
0
;
int
time_domain_assignment
=
0
;
uint8_t
nr_of_candidates
=
0
;
uint8_t
aggregation_level
=
0
;
int
rbStart
=
0
;
int
rbStart
=
0
;
int
rbSize
=
6
;
int
rbSize
=
6
;
uint16_t
*
vrb_map
=
cc
[
CC_id
].
vrb_map
;
NR_SearchSpace_t
*
ss
=
nr_mac
->
sched_ctrlCommon
->
search_space
;
NR_SearchSpace_t
*
ss
=
nr_mac
->
sched_ctrlCommon
->
search_space
;
NR_BWP_Downlink_t
*
bwp
=
nr_mac
->
sched_ctrlCommon
->
active_bwp
;
NR_BWP_Downlink_t
*
bwp
=
nr_mac
->
sched_ctrlCommon
->
active_bwp
;
...
@@ -854,8 +845,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -854,8 +845,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
long
BWPSize
=
NRRIV2BW
(
scc
->
downlinkConfigCommon
->
initialDownlinkBWP
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
long
BWPSize
=
NRRIV2BW
(
scc
->
downlinkConfigCommon
->
initialDownlinkBWP
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
long
BWPStart
=
NRRIV2PRBOFFSET
(
scc
->
downlinkConfigCommon
->
initialDownlinkBWP
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
long
BWPStart
=
NRRIV2PRBOFFSET
(
scc
->
downlinkConfigCommon
->
initialDownlinkBWP
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
nfapi_nr_dl_tti_request_body_t
*
dl_req
=
&
nr_mac
->
DL_req
[
CC_id
].
dl_tti_request_body
;
uint16_t
*
vrb_map
=
cc
[
CC_id
].
vrb_map
;
for
(
int
i
=
0
;
(
i
<
rbSize
)
&&
(
rbStart
<=
(
BWPSize
-
rbSize
));
i
++
)
{
for
(
int
i
=
0
;
(
i
<
rbSize
)
&&
(
rbStart
<=
(
BWPSize
-
rbSize
));
i
++
)
{
if
(
vrb_map
[
rbStart
+
i
])
{
if
(
vrb_map
[
rbStart
+
i
])
{
rbStart
+=
i
;
rbStart
+=
i
;
...
@@ -869,25 +859,27 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -869,25 +859,27 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
}
}
// Checking if the DCI allocation is feasible in current subframe
// Checking if the DCI allocation is feasible in current subframe
nfapi_nr_dl_tti_request_body_t
*
dl_req
=
&
nr_mac
->
DL_req
[
CC_id
].
dl_tti_request_body
;
if
(
dl_req
->
nPDUs
>
NFAPI_NR_MAX_DL_TTI_PDUS
-
2
)
{
if
(
dl_req
->
nPDUs
>
NFAPI_NR_MAX_DL_TTI_PDUS
-
2
)
{
LOG_I
(
MAC
,
"[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d
\n
"
,
slotP
,
ra
->
RA_rnti
);
LOG_I
(
MAC
,
"[RAPROC] Subframe %d: FAPI DL structure is full, skip scheduling UE %d
\n
"
,
slotP
,
ra
->
RA_rnti
);
return
;
return
;
}
}
uint8_t
aggregation_level
;
uint8_t
nr_of_candidates
;
find_aggregation_candidates
(
&
aggregation_level
,
&
nr_of_candidates
,
ss
);
find_aggregation_candidates
(
&
aggregation_level
,
&
nr_of_candidates
,
ss
);
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
int
CCEIndex
=
allocate_nr_CCEs
(
nr_mac
,
bwp
,
coreset
,
aggregation_level
,
0
,
0
,
nr_of_candidates
);
bwp
,
coreset
,
aggregation_level
,
0
,
0
,
nr_of_candidates
);
if
(
CCEIndex
<
0
)
{
if
(
CCEIndex
<
0
)
{
LOG_E
(
MAC
,
"%s(): cannot find free CCE for RA RNTI %04x!
\n
"
,
__func__
,
ra
->
rnti
);
LOG_E
(
MAC
,
"%s(): cannot find free CCE for RA RNTI %04x!
\n
"
,
__func__
,
ra
->
rnti
);
return
;
return
;
}
}
// Calculate number of symbols
int
startSymbolIndex
,
nrOfSymbols
;
const
int
startSymbolAndLength
=
bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
->
list
.
array
[
time_domain_assignment
]
->
startSymbolAndLength
;
SLIV2SL
(
startSymbolAndLength
,
&
startSymbolIndex
,
&
nrOfSymbols
);
AssertFatal
(
startSymbolIndex
>=
0
,
"StartSymbolIndex is negative
\n
"
);
// look up the PDCCH PDU for this CC, BWP, and CORESET. If it does not exist, create it. This is especially
// look up the PDCCH PDU for this CC, BWP, and CORESET. If it does not exist, create it. This is especially
// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
// important if we have multiple RAs, and the DLSCH has to reuse them, so we need to mark them
const
int
bwpid
=
bwp
->
bwp_Id
;
const
int
bwpid
=
bwp
->
bwp_Id
;
...
@@ -914,35 +906,41 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -914,35 +906,41 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
dl_req
->
nPDUs
+=
1
;
dl_req
->
nPDUs
+=
1
;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t
*
pdsch_pdu_rel15
=
&
dl_tti_pdsch_pdu
->
pdsch_pdu
.
pdsch_pdu_rel15
;
nfapi_nr_dl_tti_pdsch_pdu_rel15_t
*
pdsch_pdu_rel15
=
&
dl_tti_pdsch_pdu
->
pdsch_pdu
.
pdsch_pdu_rel15
;
LOG_I
(
NR_MAC
,
"[gNB %d][RAPROC] CC_id %d Frame %d, slotP %d: Generating RA-Msg2 DCI, rnti 0x%x, state %d
\n
"
,
module_idP
,
CC_id
,
frameP
,
slotP
,
ra
->
RA_rnti
,
ra
->
state
);
LOG_I
(
NR_MAC
,
"[gNB %d][RAPROC] CC_id %d Frame %d, slotP %d: Generating RA-Msg2 DCI, rnti 0x%x, state %d
\n
"
,
module_idP
,
CC_id
,
frameP
,
slotP
,
ra
->
RA_rnti
,
ra
->
state
);
AssertFatal
(
ra
->
secondaryCellGroup
,
"no secondaryCellGroup for RNTI %04x
\n
"
,
ra
->
crnti
);
AssertFatal
(
ra
->
secondaryCellGroup
,
"no secondaryCellGroup for RNTI %04x
\n
"
,
ra
->
crnti
);
AssertFatal
(
ra
->
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
downlinkBWP_ToAddModList
->
list
.
count
==
1
,
"downlinkBWP_ToAddModList has %d BWP!
\n
"
,
ra
->
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
downlinkBWP_ToAddModList
->
list
.
count
);
pdsch_pdu_rel15
->
pduBitmap
=
0
;
AssertFatal
(
ra
->
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
downlinkBWP_ToAddModList
->
list
.
count
==
1
,
pdsch_pdu_rel15
->
rnti
=
ra
->
RA_rnti
;
"downlinkBWP_ToAddModList has %d BWP!
\n
"
,
ra
->
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
downlinkBWP_ToAddModList
->
list
.
count
);
// SCF222: PDU index incremented for each PDSCH PDU sent in TX control message. This is used to associate control
// SCF222: PDU index incremented for each PDSCH PDU sent in TX control message. This is used to associate control
// information to data and is reset every slot.
// information to data and is reset every slot.
const
int
pduindex
=
nr_mac
->
pdu_index
[
CC_id
]
++
;
const
int
pduindex
=
nr_mac
->
pdu_index
[
CC_id
]
++
;
uint8_t
mcsTableIdx
=
0
;
if
(
bwp
->
bwp_Dedicated
->
pdsch_Config
->
choice
.
setup
->
mcs_Table
==
NULL
)
mcsTableIdx
=
0
;
else
{
if
(
*
bwp
->
bwp_Dedicated
->
pdsch_Config
->
choice
.
setup
->
mcs_Table
==
0
)
mcsTableIdx
=
1
;
else
mcsTableIdx
=
2
;
}
pdsch_pdu_rel15
->
pduBitmap
=
0
;
pdsch_pdu_rel15
->
rnti
=
ra
->
RA_rnti
;
pdsch_pdu_rel15
->
pduIndex
=
pduindex
;
pdsch_pdu_rel15
->
pduIndex
=
pduindex
;
pdsch_pdu_rel15
->
BWPSize
=
BWPSize
;
pdsch_pdu_rel15
->
BWPSize
=
BWPSize
;
pdsch_pdu_rel15
->
BWPStart
=
BWPStart
;
pdsch_pdu_rel15
->
BWPStart
=
BWPStart
;
pdsch_pdu_rel15
->
SubcarrierSpacing
=
bwp
->
bwp_Common
->
genericParameters
.
subcarrierSpacing
;
pdsch_pdu_rel15
->
SubcarrierSpacing
=
bwp
->
bwp_Common
->
genericParameters
.
subcarrierSpacing
;
pdsch_pdu_rel15
->
CyclicPrefix
=
0
;
pdsch_pdu_rel15
->
CyclicPrefix
=
0
;
pdsch_pdu_rel15
->
NrOfCodewords
=
1
;
pdsch_pdu_rel15
->
NrOfCodewords
=
1
;
pdsch_pdu_rel15
->
targetCodeRate
[
0
]
=
nr_get_code_rate_dl
(
mcsIndex
,
0
);
pdsch_pdu_rel15
->
targetCodeRate
[
0
]
=
nr_get_code_rate_dl
(
mcsIndex
,
mcsTableIdx
);
pdsch_pdu_rel15
->
qamModOrder
[
0
]
=
2
;
pdsch_pdu_rel15
->
qamModOrder
[
0
]
=
2
;
pdsch_pdu_rel15
->
mcsIndex
[
0
]
=
mcsIndex
;
pdsch_pdu_rel15
->
mcsIndex
[
0
]
=
mcsIndex
;
if
(
bwp
->
bwp_Dedicated
->
pdsch_Config
->
choice
.
setup
->
mcs_Table
==
NULL
)
pdsch_pdu_rel15
->
mcsTable
[
0
]
=
mcsTableIdx
;
pdsch_pdu_rel15
->
mcsTable
[
0
]
=
0
;
else
{
if
(
*
bwp
->
bwp_Dedicated
->
pdsch_Config
->
choice
.
setup
->
mcs_Table
==
0
)
pdsch_pdu_rel15
->
mcsTable
[
0
]
=
1
;
else
pdsch_pdu_rel15
->
mcsTable
[
0
]
=
2
;
}
pdsch_pdu_rel15
->
rvIndex
[
0
]
=
0
;
pdsch_pdu_rel15
->
rvIndex
[
0
]
=
0
;
pdsch_pdu_rel15
->
dataScramblingId
=
*
scc
->
physCellId
;
pdsch_pdu_rel15
->
dataScramblingId
=
*
scc
->
physCellId
;
pdsch_pdu_rel15
->
nrOfLayers
=
1
;
pdsch_pdu_rel15
->
nrOfLayers
=
1
;
...
@@ -957,23 +955,16 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -957,23 +955,16 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
pdsch_pdu_rel15
->
rbStart
=
rbStart
;
pdsch_pdu_rel15
->
rbStart
=
rbStart
;
pdsch_pdu_rel15
->
rbSize
=
rbSize
;
pdsch_pdu_rel15
->
rbSize
=
rbSize
;
pdsch_pdu_rel15
->
VRBtoPRBMapping
=
0
;
pdsch_pdu_rel15
->
VRBtoPRBMapping
=
0
;
pdsch_pdu_rel15
->
StartSymbolIndex
=
startSymbolIndex
;
pdsch_pdu_rel15
->
NrOfSymbols
=
nrOfSymbols
;
pdsch_pdu_rel15
->
dlDmrsSymbPos
=
fill_dmrs_mask
(
nr_mac
->
sched_ctrlCommon
->
active_bwp
->
bwp_Dedicated
->
pdsch_Config
->
choice
.
setup
,
nr_mac
->
common_channels
->
ServingCellConfigCommon
->
dmrs_TypeA_Position
,
nrOfSymbols
,
startSymbolIndex
);
// FIXME: should use Initial BWP and maybe Default values from TS 38.214 Table 5.1.2.1.1-1
int
x_Overhead
=
0
;
for
(
int
i
=
0
;
i
<
bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
->
list
.
count
;
i
++
)
{
uint8_t
tb_scaling
=
0
;
startSymbolAndLength
=
bwp
->
bwp_Common
->
pdsch_ConfigCommon
->
choice
.
setup
->
pdsch_TimeDomainAllocationList
->
list
.
array
[
i
]
->
startSymbolAndLength
;
nr_get_tbs_dl
(
&
dl_tti_pdsch_pdu
->
pdsch_pdu
,
x_Overhead
,
pdsch_pdu_rel15
->
numDmrsCdmGrpsNoData
,
tb_scaling
);
SLIV2SL
(
startSymbolAndLength
,
&
StartSymbolIndex_tmp
,
&
NrOfSymbols_tmp
);
//if (NrOfSymbols_tmp < NrOfSymbols) {
NrOfSymbols
=
NrOfSymbols_tmp
;
StartSymbolIndex
=
StartSymbolIndex_tmp
;
time_domain_assignment
=
i
;
// this is short PDSCH added to the config to fit mixed slot
//}
break
;
}
AssertFatal
(
StartSymbolIndex
>=
0
,
"StartSymbolIndex is negative
\n
"
);
pdsch_pdu_rel15
->
StartSymbolIndex
=
StartSymbolIndex
;
pdsch_pdu_rel15
->
NrOfSymbols
=
NrOfSymbols
;
pdsch_pdu_rel15
->
dlDmrsSymbPos
=
fill_dmrs_mask
(
NULL
,
scc
->
dmrs_TypeA_Position
,
NrOfSymbols
,
StartSymbolIndex
);
// Fill PDCCH DL DCI PDU
// Fill PDCCH DL DCI PDU
nfapi_nr_dl_dci_pdu_t
*
dci_pdu
=
&
pdcch_pdu_rel15
->
dci_pdu
[
pdcch_pdu_rel15
->
numDlDci
];
nfapi_nr_dl_dci_pdu_t
*
dci_pdu
=
&
pdcch_pdu_rel15
->
dci_pdu
[
pdcch_pdu_rel15
->
numDlDci
];
...
@@ -994,7 +985,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -994,7 +985,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
dci_payload
.
time_domain_assignment
.
val
=
time_domain_assignment
;
dci_payload
.
time_domain_assignment
.
val
=
time_domain_assignment
;
dci_payload
.
vrb_to_prb_mapping
.
val
=
0
;
dci_payload
.
vrb_to_prb_mapping
.
val
=
0
;
dci_payload
.
mcs
=
pdsch_pdu_rel15
->
mcsIndex
[
0
];
dci_payload
.
mcs
=
pdsch_pdu_rel15
->
mcsIndex
[
0
];
dci_payload
.
tb_scaling
=
0
;
dci_payload
.
tb_scaling
=
tb_scaling
;
LOG_D
(
NR_MAC
,
LOG_D
(
NR_MAC
,
"[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d
\n
"
,
"[RAPROC] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d
\n
"
,
...
@@ -1027,6 +1018,17 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -1027,6 +1018,17 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
// DL TX request
// DL TX request
nfapi_nr_pdu_t
*
tx_req
=
&
nr_mac
->
TX_req
[
CC_id
].
pdu_list
[
nr_mac
->
TX_req
[
CC_id
].
Number_of_PDUs
];
nfapi_nr_pdu_t
*
tx_req
=
&
nr_mac
->
TX_req
[
CC_id
].
pdu_list
[
nr_mac
->
TX_req
[
CC_id
].
Number_of_PDUs
];
// Program UL processing for Msg3
NR_BWP_Uplink_t
*
ubwp
=
ra
->
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
uplinkBWP_ToAddModList
->
list
.
array
[
ra
->
bwp_id
-
1
];
nr_get_Msg3alloc
(
module_idP
,
CC_id
,
scc
,
ubwp
,
slotP
,
frameP
,
ra
);
nr_add_msg3
(
module_idP
,
CC_id
,
frameP
,
slotP
,
ra
,
(
uint8_t
*
)
&
tx_req
->
TLVs
[
0
].
value
.
direct
[
0
]);
LOG_I
(
MAC
,
"Frame %d, Subframe %d: Setting RA-Msg3 reception for Frame %d Subframe %d
\n
"
,
frameP
,
slotP
,
ra
->
Msg3_frame
,
ra
->
Msg3_slot
);
T
(
T_GNB_MAC_DL_RAR_PDU_WITH_DATA
,
T_INT
(
module_idP
),
T_INT
(
CC_id
),
T_INT
(
ra
->
RA_rnti
),
T_INT
(
frameP
),
T_INT
(
slotP
),
T_INT
(
0
),
T_BUFFER
(
&
tx_req
->
TLVs
[
0
].
value
.
direct
[
0
],
tx_req
->
TLVs
[
0
].
length
));
tx_req
->
PDU_length
=
pdsch_pdu_rel15
->
TBSize
[
0
];
tx_req
->
PDU_length
=
pdsch_pdu_rel15
->
TBSize
[
0
];
tx_req
->
PDU_index
=
pduindex
;
tx_req
->
PDU_index
=
pduindex
;
tx_req
->
num_TLV
=
1
;
tx_req
->
num_TLV
=
1
;
...
@@ -1035,25 +1037,13 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
...
@@ -1035,25 +1037,13 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra
nr_mac
->
TX_req
[
CC_id
].
Number_of_PDUs
++
;
nr_mac
->
TX_req
[
CC_id
].
Number_of_PDUs
++
;
nr_mac
->
TX_req
[
CC_id
].
Slot
=
slotP
;
nr_mac
->
TX_req
[
CC_id
].
Slot
=
slotP
;
// Program UL processing for Msg3
NR_BWP_Uplink_t
*
ubwp
=
ra
->
secondaryCellGroup
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
uplinkBWP_ToAddModList
->
list
.
array
[
ra
->
bwp_id
-
1
];
nr_get_Msg3alloc
(
module_idP
,
CC_id
,
scc
,
ubwp
,
slotP
,
frameP
,
ra
);
LOG_I
(
MAC
,
"Frame %d, Subframe %d: Setting RA-Msg3 reception for Frame %d Subframe %d
\n
"
,
frameP
,
slotP
,
ra
->
Msg3_frame
,
ra
->
Msg3_slot
);
nr_add_msg3
(
module_idP
,
CC_id
,
frameP
,
slotP
,
ra
,
(
uint8_t
*
)
&
tx_req
->
TLVs
[
0
].
value
.
direct
[
0
]);
ra
->
state
=
WAIT_Msg3
;
LOG_I
(
MAC
,
"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d
\n
"
,
module_idP
,
frameP
,
slotP
,
ra
->
state
);
x_Overhead
=
0
;
nr_get_tbs_dl
(
&
dl_tti_pdsch_pdu
->
pdsch_pdu
,
x_Overhead
,
pdsch_pdu_rel15
->
numDmrsCdmGrpsNoData
,
dci_payload
.
tb_scaling
);
T
(
T_GNB_MAC_DL_RAR_PDU_WITH_DATA
,
T_INT
(
module_idP
),
T_INT
(
CC_id
),
T_INT
(
ra
->
RA_rnti
),
T_INT
(
frameP
),
T_INT
(
slotP
),
T_INT
(
0
),
T_BUFFER
(
&
tx_req
->
TLVs
[
0
].
value
.
direct
[
0
],
tx_req
->
TLVs
[
0
].
length
));
// Mark the corresponding RBs as used
// Mark the corresponding RBs as used
for
(
int
rb
=
0
;
rb
<
rbSize
;
rb
++
)
{
for
(
int
rb
=
0
;
rb
<
rbSize
;
rb
++
)
{
vrb_map
[
rb
+
rbStart
]
=
1
;
vrb_map
[
rb
+
rbStart
]
=
1
;
}
}
ra
->
state
=
WAIT_Msg3
;
LOG_I
(
MAC
,
"[gNB %d][RAPROC] Frame %d, Subframe %d: RA state %d
\n
"
,
module_idP
,
frameP
,
slotP
,
ra
->
state
);
}
}
}
}
...
...
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