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wangjie
OpenXG-RAN
Commits
c91d689d
Commit
c91d689d
authored
4 years ago
by
Shweta Shrivastava
Browse files
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Plain Diff
Imrpovements for extracting UL DCI, remove hardcoding, blind decoding of DCI
parent
bdc1fa4e
Changes
5
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Showing
5 changed files
with
317 additions
and
153 deletions
+317
-153
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
+8
-2
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
+36
-31
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
+12
-8
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+260
-111
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
+1
-1
No files found.
nfapi/open-nFAPI/nfapi/public_inc/fapi_nr_ue_interface.h
View file @
c91d689d
...
...
@@ -415,8 +415,14 @@ typedef struct {
uint8_t
number_of_candidates
;
uint16_t
CCE
[
64
];
uint8_t
L
[
64
];
uint8_t
dci_length
;
uint8_t
dci_format
;
// 3GPP TS 38.212 Sec. 7.3.1.0, 3GPP TS 138.131 sec. 6.3.2 (SearchSpace)
// The maximum number of DCI lengths allowed by the spec are 4, with max 3 for C-RNTI.
// But a given search space may only support a maximum of 2 DCI formats at a time
// depending on its search space type configured by RRC. Hence for blind decoding, UE
// needs to monitor only upto 2 DCI lengths for a given search space.
uint8_t
num_dci_options
;
// Num DCIs the UE actually needs to decode (1 or 2)
uint8_t
dci_length_options
[
2
];
uint8_t
dci_format_options
[
2
];
}
fapi_nr_dl_config_dci_dl_pdu_rel15_t
;
typedef
struct
{
...
...
This diff is collapsed.
Click to expand it.
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @
c91d689d
...
...
@@ -845,7 +845,6 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
for
(
int
i
=
0
;
i
<
pdcch_vars
->
nb_search_space
;
i
++
)
{
rel15
=
&
pdcch_vars
->
pdcch_config
[
i
];
int
dci_length
=
rel15
->
dci_length
;
//int gNB_id = 0;
int16_t
tmp_e
[
16
*
108
];
rnti_t
n_rnti
;
...
...
@@ -853,41 +852,47 @@ uint8_t nr_dci_decoding_procedure(PHY_VARS_NR_UE *ue,
for
(
int
j
=
0
;
j
<
rel15
->
number_of_candidates
;
j
++
)
{
int
CCEind
=
rel15
->
CCE
[
j
];
int
L
=
rel15
->
L
[
j
];
uint64_t
dci_estimation
[
2
]
=
{
0
};
const
t_nrPolar_params
*
currentPtrDCI
=
nr_polar_params
(
NR_POLAR_DCI_MESSAGE_TYPE
,
dci_length
,
L
,
1
,
&
ue
->
polarList
);
LOG_D
(
PHY
,
"Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d
\n
"
,
j
,
rel15
->
number_of_candidates
,
CCEind
,
CCEind
*
9
*
6
*
2
,
L
);
// Loop over possible DCI lengths
for
(
int
k
=
0
;
k
<
rel15
->
num_dci_options
;
k
++
)
{
int
dci_length
=
rel15
->
dci_length_options
[
k
];
uint64_t
dci_estimation
[
2
]
=
{
0
};
const
t_nrPolar_params
*
currentPtrDCI
=
nr_polar_params
(
NR_POLAR_DCI_MESSAGE_TYPE
,
dci_length
,
L
,
1
,
&
ue
->
polarList
);
LOG_D
(
PHY
,
"Trying DCI candidate %d of %d number of candidates, CCE %d (%d), L %d
\n
"
,
j
,
rel15
->
number_of_candidates
,
CCEind
,
CCEind
*
9
*
6
*
2
,
L
);
nr_pdcch_unscrambling
(
&
pdcch_vars
->
e_rx
[
CCEind
*
108
],
rel15
->
coreset
.
scrambling_rnti
,
L
*
108
,
rel15
->
coreset
.
pdcch_dmrs_scrambling_id
,
tmp_e
);
nr_pdcch_unscrambling
(
&
pdcch_vars
->
e_rx
[
CCEind
*
108
],
rel15
->
coreset
.
scrambling_rnti
,
L
*
108
,
rel15
->
coreset
.
pdcch_dmrs_scrambling_id
,
tmp_e
);
#ifdef DEBUG_DCI_DECODING
uint32_t
*
z
=
(
uint32_t
*
)
&
pdcch_vars
->
e_rx
[
CCEind
*
108
];
for
(
int
index_z
=
0
;
index_z
<
96
;
index_z
++
){
for
(
int
i
=
0
;
i
<
9
;
i
++
)
{
LOG_D
(
PHY
,
"z[%d]=(%d,%d)
\n
"
,
(
9
*
index_z
+
i
),
*
(
int16_t
*
)
&
z
[
index_z
+
i
],
*
(
1
+
(
int16_t
*
)
&
z
[
index_z
+
i
]));
#ifdef DEBUG_DCI_DECODING
uint32_t
*
z
=
(
uint32_t
*
)
&
pdcch_vars
->
e_rx
[
CCEind
*
108
];
for
(
int
index_z
=
0
;
index_z
<
96
;
index_z
++
){
for
(
int
i
=
0
;
i
<
9
;
i
++
)
{
LOG_D
(
PHY
,
"z[%d]=(%d,%d)
\n
"
,
(
9
*
index_z
+
i
),
*
(
int16_t
*
)
&
z
[
index_z
+
i
],
*
(
1
+
(
int16_t
*
)
&
z
[
index_z
+
i
]));
}
}
#endif
uint16_t
crc
=
polar_decoder_int16
(
tmp_e
,
dci_estimation
,
1
,
currentPtrDCI
);
n_rnti
=
rel15
->
rnti
;
if
(
crc
==
n_rnti
)
{
LOG_D
(
PHY
,
"Decoded crc %x matches rnti %x for DCI format %d
\n
"
,
crc
,
n_rnti
,
rel15
->
dci_format_options
[
k
]);
dci_ind
->
SFN
=
frame
;
dci_ind
->
slot
=
slot
;
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
rnti
=
n_rnti
;
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
n_CCE
=
CCEind
;
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
dci_format
=
rel15
->
dci_format_options
[
k
];
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
payloadSize
=
dci_length
;
memcpy
((
void
*
)
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
payloadBits
,(
void
*
)
dci_estimation
,
8
);
dci_ind
->
number_of_dcis
++
;
break
;
// If DCI is found, no need to check for remaining DCI lengths
}
else
{
LOG_D
(
PHY
,
"Decoded crc %x does not match rnti %x for DCI format %d
\n
"
,
crc
,
n_rnti
,
rel15
->
dci_format_options
[
k
]);
}
#endif
uint16_t
crc
=
polar_decoder_int16
(
tmp_e
,
dci_estimation
,
1
,
currentPtrDCI
);
n_rnti
=
rel15
->
rnti
;
if
(
crc
==
n_rnti
)
{
LOG_D
(
PHY
,
"Decoded crc %x matches rnti %x for DCI format %d
\n
"
,
crc
,
n_rnti
,
rel15
->
dci_format
);
dci_ind
->
SFN
=
frame
;
dci_ind
->
slot
=
slot
;
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
rnti
=
n_rnti
;
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
n_CCE
=
CCEind
;
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
dci_format
=
rel15
->
dci_format
;
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
payloadSize
=
dci_length
;
memcpy
((
void
*
)
dci_ind
->
dci_list
[
dci_ind
->
number_of_dcis
].
payloadBits
,(
void
*
)
dci_estimation
,
8
);
dci_ind
->
number_of_dcis
++
;
}
else
{
LOG_D
(
PHY
,
"Decoded crc %x does not match rnti %x for DCI format %d
\n
"
,
crc
,
n_rnti
,
rel15
->
dci_format
);
}
}
}
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_UE/nr_ue_dci_configuration.c
View file @
c91d689d
...
...
@@ -64,7 +64,7 @@ void fill_dci_search_candidates(NR_SearchSpace_t *ss,fapi_nr_dl_config_dci_dl_pd
}
void
config_dci_pdu
(
NR_UE_MAC_INST_t
*
mac
,
fapi_nr_dl_config_dci_dl_pdu_rel15_t
*
rel15
,
fapi_nr_dl_config_request_t
*
dl_config
,
int
rnti_type
,
int
ss_id
,
uint8_t
dci_format
){
void
config_dci_pdu
(
NR_UE_MAC_INST_t
*
mac
,
fapi_nr_dl_config_dci_dl_pdu_rel15_t
*
rel15
,
fapi_nr_dl_config_request_t
*
dl_config
,
int
rnti_type
,
int
ss_id
){
uint16_t
monitoringSymbolsWithinSlot
;
uint8_t
bwp_id
=
1
,
coreset_id
=
1
;
...
...
@@ -76,9 +76,6 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
NR_BWP_DownlinkCommon_t
*
initialDownlinkBWP
=
scc
->
downlinkConfigCommon
->
initialDownlinkBWP
;
NR_SearchSpace_t
*
ss
=
mac
->
SSpace
[
bwp_id
-
1
][
coreset_id
-
1
][
ss_id
];
// DCI format configuration
rel15
->
dci_format
=
dci_format
;
// CORESET configuration
NR_ControlResourceSet_t
*
coreset
=
mac
->
coreset
[
bwp_id
-
1
][
coreset_id
-
1
];
rel15
->
coreset
.
duration
=
coreset
->
duration
;
...
...
@@ -123,7 +120,9 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15
->
BWPSize
=
NRRIV2BW
(
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
rel15
->
BWPStart
=
NRRIV2PRBOFFSET
(
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
rel15
->
SubcarrierSpacing
=
bwp_Common
->
genericParameters
.
subcarrierSpacing
;
rel15
->
dci_length
=
nr_dci_size
(
scc
,
mac
->
scg
,
def_dci_pdu_rel15
,
rel15
->
dci_format
,
NR_RNTI_C
,
rel15
->
BWPSize
,
bwp_id
);
for
(
int
i
=
0
;
i
<
rel15
->
num_dci_options
;
i
++
)
{
rel15
->
dci_length_options
[
i
]
=
nr_dci_size
(
scc
,
mac
->
scg
,
def_dci_pdu_rel15
,
rel15
->
dci_format_options
[
i
],
NR_RNTI_C
,
rel15
->
BWPSize
,
bwp_id
);
}
break
;
case
NR_RNTI_RA
:
// we use the initial DL BWP
...
...
@@ -133,7 +132,7 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15
->
BWPSize
=
NRRIV2BW
(
initialDownlinkBWP
->
genericParameters
.
locationAndBandwidth
,
275
);
rel15
->
BWPStart
=
NRRIV2PRBOFFSET
(
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
275
);
//NRRIV2PRBOFFSET(initialDownlinkBWP->genericParameters.locationAndBandwidth, 275);
rel15
->
SubcarrierSpacing
=
initialDownlinkBWP
->
genericParameters
.
subcarrierSpacing
;
rel15
->
dci_length
=
nr_dci_size
(
scc
,
mac
->
scg
,
def_dci_pdu_rel15
,
rel15
->
dci_format
,
NR_RNTI_RA
,
rel15
->
BWPSize
,
bwp_id
);
rel15
->
dci_length
_options
[
0
]
=
nr_dci_size
(
scc
,
mac
->
scg
,
def_dci_pdu_rel15
,
rel15
->
dci_format_options
[
0
]
,
NR_RNTI_RA
,
rel15
->
BWPSize
,
bwp_id
);
break
;
case
NR_RNTI_P
:
break
;
...
...
@@ -215,7 +214,9 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
LOG_D
(
MAC
,
"[DCI_CONFIG] Configure monitoring of PDCCH candidates in Type1-PDCCH common random access search space
\n
"
);
switch
(
mac
->
ra_state
){
case
WAIT_RAR
:
config_dci_pdu
(
mac
,
rel15
,
dl_config
,
NR_RNTI_RA
,
ss_id
,
NR_DL_DCI_FORMAT_1_0
);
rel15
->
num_dci_options
=
1
;
rel15
->
dci_format_options
[
0
]
=
NR_DL_DCI_FORMAT_1_0
;
config_dci_pdu
(
mac
,
rel15
,
dl_config
,
NR_RNTI_RA
,
ss_id
);
fill_dci_search_candidates
(
ss
,
rel15
);
break
;
case
WAIT_CONTENTION_RESOLUTION
:
...
...
@@ -286,7 +287,10 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
// Monitors DCI 01 and 11 scrambled with C-RNTI, or CS-RNTI(s), or SP-CSI-RNTI
if
(
get_softmodem_params
()
->
phy_test
==
1
&&
mac
->
crnti
>
0
)
{
LOG_D
(
MAC
,
"[DCI_CONFIG] Configure monitoring of PDCCH candidates in the user specific search space
\n
"
);
config_dci_pdu
(
mac
,
rel15
,
dl_config
,
NR_RNTI_C
,
ss_id
,
NR_DL_DCI_FORMAT_1_1
);
rel15
->
num_dci_options
=
2
;
rel15
->
dci_format_options
[
0
]
=
NR_DL_DCI_FORMAT_1_1
;
rel15
->
dci_format_options
[
1
]
=
NR_UL_DCI_FORMAT_0_1
;
config_dci_pdu
(
mac
,
rel15
,
dl_config
,
NR_RNTI_C
,
ss_id
);
fill_dci_search_candidates
(
ss
,
rel15
);
#ifdef DEBUG_DCI
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @
c91d689d
...
...
@@ -778,25 +778,27 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
NR_UE_MAC_INST_t
*
mac
=
get_mac_inst
(
mod_id
);
uint8_t
access_mode
=
SCHEDULED_ACCESS
;
// program PUSCH
. this should actually be done upon reception of an UL DCI
// program PUSCH
with UL DCI parameters
nr_dcireq_t
dcireq
;
nr_scheduled_response_t
scheduled_response
;
fapi_nr_tx_request_t
tx_req
;
fapi_nr_tx_request_body_t
tx_req_body
;
//--------------------------Temporary configuration-----------------------------//
uint16_t
rnti
=
0x1234
;
uint32_t
rb_size
=
50
;
uint32_t
rb_start
=
0
;
uint8_t
nr_of_symbols
=
11
;
uint8_t
start_symbol_index
=
0
;
fapi_nr_ul_config_request_pdu_t
*
ulcfg_pdu
=
&
mac
->
ul_config_request
.
ul_config_list
[
0
];
uint16_t
rnti
=
ulcfg_pdu
->
pusch_config_pdu
.
rnti
;
uint32_t
rb_size
=
ulcfg_pdu
->
pusch_config_pdu
.
rb_size
;
uint32_t
rb_start
=
ulcfg_pdu
->
pusch_config_pdu
.
rb_start
;
uint8_t
nr_of_symbols
=
ulcfg_pdu
->
pusch_config_pdu
.
nr_of_symbols
;
uint8_t
start_symbol_index
=
ulcfg_pdu
->
pusch_config_pdu
.
start_symbol_index
;
uint8_t
nrOfLayers
=
1
;
uint8_t
mcs_index
=
9
;
uint8_t
mcs_table
=
0
;
uint8_t
harq_process_id
=
0
;
uint8_t
rv_index
=
0
;
uint8_t
mcs_index
=
ulcfg_pdu
->
pusch_config_pdu
.
mcs_index
;
uint8_t
harq_process_id
=
ulcfg_pdu
->
pusch_config_pdu
.
pusch_data
.
harq_process_id
;
uint8_t
rv_index
=
ulcfg_pdu
->
pusch_config_pdu
.
pusch_data
.
rv_index
;
uint16_t
l_prime_mask
=
get_l_prime
(
nr_of_symbols
,
typeB
,
pusch_dmrs_pos0
,
pusch_len1
);
uint8_t
dmrs_config_type
=
0
;
// These should come from RRC config!!!
uint8_t
ptrs_mcs1
=
2
;
uint8_t
ptrs_mcs2
=
4
;
uint8_t
ptrs_mcs3
=
10
;
...
...
@@ -808,7 +810,15 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
uint8_t
no_data_in_dmrs
=
1
;
uint16_t
number_dmrs_symbols
=
0
;
uint16_t
ul_dmrs_symb_pos
=
l_prime_mask
<<
start_symbol_index
;
//------------------------------------------------------------------------------//
#ifdef DEBUG_DCI
LOG_I
(
MAC
,
" UL config params
\n
rnti: %x
\n
rb_size: %d
\n
"
,
rnti
,
rb_size
);
LOG_I
(
MAC
,
"rb_start: %x
\n
nr_of_symbols: %d
\n
start_symbol_index: %d
\n
nrOfLayers: %d
\n
mcs_index: %d
\n
\
mcs_table: %d
\n
harq_process_id: %d
\n
ndi: %d
\n
num_cb: %d
\n
rv_index: %d
\n
"
,
rb_start
,
nr_of_symbols
,
start_symbol_index
,
nrOfLayers
,
mcs_index
,
mcs_table
,
harq_process_id
,
ndi
,
num_cb
,
rv_index
);
#endif
for
(
i
=
start_symbol_index
;
i
<
start_symbol_index
+
nr_of_symbols
;
i
++
)
{
if
((
ul_dmrs_symb_pos
>>
i
)
&
0x01
)
...
...
@@ -2261,13 +2271,22 @@ int8_t nr_ue_process_dci_time_dom_resource_assignment(NR_UE_MAC_INST_t *mac,
*/
if
(
pusch_config_pdu
!=
NULL
){
NR_PUSCH_TimeDomainResourceAllocationList_t
*
pusch_TimeDomainAllocationList
=
NULL
;
if
(
mac
->
ULbwp
[
0
]
->
bwp_Dedicated
->
pusch_Config
)
if
(
mac
->
ULbwp
[
0
]
->
bwp_Dedicated
->
pusch_Config
->
choice
.
setup
->
pusch_TimeDomainAllocationList
)
{
pusch_TimeDomainAllocationList
=
mac
->
ULbwp
[
0
]
->
bwp_Dedicated
->
pusch_Config
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
choice
.
setup
;
}
else
if
(
mac
->
ULbwp
[
0
]
->
bwp_Common
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
)
{
pusch_TimeDomainAllocationList
=
mac
->
ULbwp
[
0
]
->
bwp_Common
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
;
}
if
(
pusch_TimeDomainAllocationList
)
{
AssertFatal
(
pusch_TimeDomainAllocationList
->
list
.
count
>
time_domain_ind
,
"time_domain_ind %d >= pdsch->TimeDomainAllocationList->list.count %d
\n
"
,
time_domain_ind
,
pusch_TimeDomainAllocationList
->
list
.
count
);
if
(
time_domain_ind
>=
pusch_TimeDomainAllocationList
->
list
.
count
)
{
LOG_E
(
MAC
,
"time_domain_ind %d >= pusch->TimeDomainAllocationList->list.count %d
\n
"
,
time_domain_ind
,
pusch_TimeDomainAllocationList
->
list
.
count
);
pusch_config_pdu
->
start_symbol_index
=
0
;
pusch_config_pdu
->
nr_of_symbols
=
0
;
return
-
1
;
}
int
startSymbolAndLength
=
pusch_TimeDomainAllocationList
->
list
.
array
[
time_domain_ind
]
->
startSymbolAndLength
;
int
S
,
L
;
SLIV2SL
(
startSymbolAndLength
,
&
S
,
&
L
);
...
...
@@ -3128,6 +3147,33 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
int
pos
=
0
;
int
fsize
=
0
;
if
(
rnti_type
==
NR_RNTI_C
)
{
// First find out the DCI format from the first bit (UE performed blind decoding)
pos
++
;
dci_pdu_rel15
->
format_indicator
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
1
;
#ifdef DEBUG_EXTRACT_DCI
LOG_D
(
MAC
,
"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
format_indicator
,
1
,
N_RB
,
dci_size
-
pos
,
*
dci_pdu
);
#endif
if
(
dci_format
==
NR_UL_DCI_FORMAT_0_0
||
dci_format
==
NR_DL_DCI_FORMAT_1_0
)
{
if
(
dci_pdu_rel15
->
format_indicator
==
0
)
dci_format
=
NR_UL_DCI_FORMAT_0_0
;
else
dci_format
=
NR_DL_DCI_FORMAT_1_0
;
}
else
if
(
dci_format
==
NR_UL_DCI_FORMAT_0_1
||
dci_format
==
NR_DL_DCI_FORMAT_1_1
)
{
// In case the sizes of formats 0_1 and 1_1 happen to be the same
if
(
dci_pdu_rel15
->
format_indicator
==
0
)
dci_format
=
NR_UL_DCI_FORMAT_0_1
;
else
dci_format
=
NR_DL_DCI_FORMAT_1_1
;
}
}
#ifdef DEBUG_EXTRACT_DCI
LOG_D
(
MAC
,
"DCI format is %d
\n
"
,
dci_format
);
#endif
switch
(
dci_format
)
{
case
NR_DL_DCI_FORMAT_1_0
:
...
...
@@ -3170,13 +3216,6 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
case
NR_RNTI_C
:
// indicating a DL DCI format 1bit
pos
++
;
dci_pdu_rel15
->
format_indicator
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
1
;
#ifdef DEBUG_EXTRACT_DCI
LOG_D
(
MAC
,
"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)
\n
"
,
dci_pdu_rel15
->
format_indicator
,
1
,
N_RB
,
dci_size
-
pos
,
*
dci_pdu
);
#endif
// Freq domain assignment (275rb >> fsize = 16)
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
pos
+=
fsize
;
...
...
@@ -3377,18 +3416,16 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
switch
(
rnti_type
)
{
case
NR_RNTI_C
:
// indicating a DL DCI format 1bit
dci_pdu_rel15
->
format_indicator
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
1
;
// Freq domain assignment max 16 bit
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB_UL
*
(
N_RB_UL
+
1
))
>>
1
)
);
pos
+=
fsize
;
dci_pdu_rel15
->
frequency_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
fsize
)
-
1
);
// Time domain assignment 4bit
pos
+=
4
;
dci_pdu_rel15
->
time_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0xf
;
// Frequency hopping flag – 1 bit
pos
++
;
dci_pdu_rel15
->
frequency_hopping_flag
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
1
;
// This is not supported yet - Skip for now
// Frequency hopping flag – 1 bit
//pos++;
//dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
// MCS 5 bit
pos
+=
5
;
dci_pdu_rel15
->
mcs
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1f
;
...
...
@@ -3452,89 +3489,201 @@ void nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
break
;
case
NR_DL_DCI_FORMAT_1_1
:
// Format indicator
pos
=
1
;
dci_pdu_rel15
->
format_indicator
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
1
;
// Carrier indicator
pos
+=
dci_pdu_rel15
->
carrier_indicator
.
nbits
;
dci_pdu_rel15
->
carrier_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
carrier_indicator
.
nbits
)
-
1
);
// BWP Indicator
pos
+=
dci_pdu_rel15
->
bwp_indicator
.
nbits
;
dci_pdu_rel15
->
bwp_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
bwp_indicator
.
nbits
)
-
1
);
// Frequency domain resource assignment
pos
+=
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
;
dci_pdu_rel15
->
frequency_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
)
-
1
);
// Time domain resource assignment
pos
+=
dci_pdu_rel15
->
time_domain_assignment
.
nbits
;
dci_pdu_rel15
->
time_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
time_domain_assignment
.
nbits
)
-
1
);
// VRB-to-PRB mapping
pos
+=
dci_pdu_rel15
->
vrb_to_prb_mapping
.
nbits
;
dci_pdu_rel15
->
vrb_to_prb_mapping
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
vrb_to_prb_mapping
.
nbits
)
-
1
);
// PRB bundling size indicator
pos
+=
dci_pdu_rel15
->
prb_bundling_size_indicator
.
nbits
;
dci_pdu_rel15
->
prb_bundling_size_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
prb_bundling_size_indicator
.
nbits
)
-
1
);
// Rate matching indicator
pos
+=
dci_pdu_rel15
->
rate_matching_indicator
.
nbits
;
dci_pdu_rel15
->
rate_matching_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
rate_matching_indicator
.
nbits
)
-
1
);
// ZP CSI-RS trigger
pos
+=
dci_pdu_rel15
->
zp_csi_rs_trigger
.
nbits
;
dci_pdu_rel15
->
zp_csi_rs_trigger
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
zp_csi_rs_trigger
.
nbits
)
-
1
);
//TB1
// MCS 5bit
pos
+=
5
;
dci_pdu_rel15
->
mcs
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1f
;
// New data indicator 1bit
pos
+=
1
;
dci_pdu_rel15
->
ndi
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1
;
// Redundancy version 2bit
pos
+=
2
;
dci_pdu_rel15
->
rv
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x3
;
//TB2
// MCS 5bit
pos
+=
dci_pdu_rel15
->
mcs2
.
nbits
;
dci_pdu_rel15
->
mcs2
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
mcs2
.
nbits
)
-
1
);
// New data indicator 1bit
pos
+=
dci_pdu_rel15
->
ndi2
.
nbits
;
dci_pdu_rel15
->
ndi2
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
ndi2
.
nbits
)
-
1
);
// Redundancy version 2bit
pos
+=
dci_pdu_rel15
->
rv2
.
nbits
;
dci_pdu_rel15
->
rv2
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
rv2
.
nbits
)
-
1
);
// HARQ process number 4bit
pos
+=
4
;
dci_pdu_rel15
->
harq_pid
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0xf
;
// Downlink assignment index
pos
+=
dci_pdu_rel15
->
dai
[
0
].
nbits
;
dci_pdu_rel15
->
dai
[
0
].
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
dai
[
0
].
nbits
)
-
1
);
// TPC command for scheduled PUCCH 2bit
pos
+=
2
;
dci_pdu_rel15
->
tpc
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x3
;
// PUCCH resource indicator 3bit
pos
+=
3
;
dci_pdu_rel15
->
pucch_resource_indicator
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x3
;
// PDSCH-to-HARQ_feedback timing indicator
pos
+=
dci_pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
.
nbits
;
dci_pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
.
nbits
)
-
1
);
// Antenna ports
pos
+=
dci_pdu_rel15
->
antenna_ports
.
nbits
;
dci_pdu_rel15
->
antenna_ports
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
antenna_ports
.
nbits
)
-
1
);
// TCI
pos
+=
dci_pdu_rel15
->
transmission_configuration_indication
.
nbits
;
dci_pdu_rel15
->
transmission_configuration_indication
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
transmission_configuration_indication
.
nbits
)
-
1
);
// SRS request
pos
+=
dci_pdu_rel15
->
srs_request
.
nbits
;
dci_pdu_rel15
->
srs_request
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
srs_request
.
nbits
)
-
1
);
// CBG transmission information
pos
+=
dci_pdu_rel15
->
cbgti
.
nbits
;
dci_pdu_rel15
->
cbgti
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
cbgti
.
nbits
)
-
1
);
// CBG flushing out information
pos
+=
dci_pdu_rel15
->
cbgfi
.
nbits
;
dci_pdu_rel15
->
cbgfi
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
cbgfi
.
nbits
)
-
1
);
// DMRS sequence init
pos
+=
1
;
dci_pdu_rel15
->
dmrs_sequence_initialization
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1
;
break
;
switch
(
rnti_type
)
{
case
NR_RNTI_C
:
// Carrier indicator
pos
+=
dci_pdu_rel15
->
carrier_indicator
.
nbits
;
dci_pdu_rel15
->
carrier_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
carrier_indicator
.
nbits
)
-
1
);
// BWP Indicator
pos
+=
dci_pdu_rel15
->
bwp_indicator
.
nbits
;
dci_pdu_rel15
->
bwp_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
bwp_indicator
.
nbits
)
-
1
);
// Frequency domain resource assignment
pos
+=
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
;
dci_pdu_rel15
->
frequency_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
)
-
1
);
// Time domain resource assignment
pos
+=
dci_pdu_rel15
->
time_domain_assignment
.
nbits
;
dci_pdu_rel15
->
time_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
time_domain_assignment
.
nbits
)
-
1
);
// VRB-to-PRB mapping
pos
+=
dci_pdu_rel15
->
vrb_to_prb_mapping
.
nbits
;
dci_pdu_rel15
->
vrb_to_prb_mapping
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
vrb_to_prb_mapping
.
nbits
)
-
1
);
// PRB bundling size indicator
pos
+=
dci_pdu_rel15
->
prb_bundling_size_indicator
.
nbits
;
dci_pdu_rel15
->
prb_bundling_size_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
prb_bundling_size_indicator
.
nbits
)
-
1
);
// Rate matching indicator
pos
+=
dci_pdu_rel15
->
rate_matching_indicator
.
nbits
;
dci_pdu_rel15
->
rate_matching_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
rate_matching_indicator
.
nbits
)
-
1
);
// ZP CSI-RS trigger
pos
+=
dci_pdu_rel15
->
zp_csi_rs_trigger
.
nbits
;
dci_pdu_rel15
->
zp_csi_rs_trigger
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
zp_csi_rs_trigger
.
nbits
)
-
1
);
//TB1
// MCS 5bit
pos
+=
5
;
dci_pdu_rel15
->
mcs
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1f
;
// New data indicator 1bit
pos
+=
1
;
dci_pdu_rel15
->
ndi
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1
;
// Redundancy version 2bit
pos
+=
2
;
dci_pdu_rel15
->
rv
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x3
;
//TB2
// MCS 5bit
pos
+=
dci_pdu_rel15
->
mcs2
.
nbits
;
dci_pdu_rel15
->
mcs2
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
mcs2
.
nbits
)
-
1
);
// New data indicator 1bit
pos
+=
dci_pdu_rel15
->
ndi2
.
nbits
;
dci_pdu_rel15
->
ndi2
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
ndi2
.
nbits
)
-
1
);
// Redundancy version 2bit
pos
+=
dci_pdu_rel15
->
rv2
.
nbits
;
dci_pdu_rel15
->
rv2
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
rv2
.
nbits
)
-
1
);
// HARQ process number 4bit
pos
+=
4
;
dci_pdu_rel15
->
harq_pid
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0xf
;
// Downlink assignment index
pos
+=
dci_pdu_rel15
->
dai
[
0
].
nbits
;
dci_pdu_rel15
->
dai
[
0
].
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
dai
[
0
].
nbits
)
-
1
);
// TPC command for scheduled PUCCH 2bit
pos
+=
2
;
dci_pdu_rel15
->
tpc
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x3
;
// PUCCH resource indicator 3bit
pos
+=
3
;
dci_pdu_rel15
->
pucch_resource_indicator
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x3
;
// PDSCH-to-HARQ_feedback timing indicator
pos
+=
dci_pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
.
nbits
;
dci_pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
.
nbits
)
-
1
);
// Antenna ports
pos
+=
dci_pdu_rel15
->
antenna_ports
.
nbits
;
dci_pdu_rel15
->
antenna_ports
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
antenna_ports
.
nbits
)
-
1
);
// TCI
pos
+=
dci_pdu_rel15
->
transmission_configuration_indication
.
nbits
;
dci_pdu_rel15
->
transmission_configuration_indication
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
transmission_configuration_indication
.
nbits
)
-
1
);
// SRS request
pos
+=
dci_pdu_rel15
->
srs_request
.
nbits
;
dci_pdu_rel15
->
srs_request
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
srs_request
.
nbits
)
-
1
);
// CBG transmission information
pos
+=
dci_pdu_rel15
->
cbgti
.
nbits
;
dci_pdu_rel15
->
cbgti
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
cbgti
.
nbits
)
-
1
);
// CBG flushing out information
pos
+=
dci_pdu_rel15
->
cbgfi
.
nbits
;
dci_pdu_rel15
->
cbgfi
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
cbgfi
.
nbits
)
-
1
);
// DMRS sequence init
pos
+=
1
;
dci_pdu_rel15
->
dmrs_sequence_initialization
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1
;
break
;
}
break
;
}
case
NR_UL_DCI_FORMAT_0_1
:
switch
(
rnti_type
)
{
case
NR_RNTI_C
:
// Carrier indicator
pos
+=
dci_pdu_rel15
->
carrier_indicator
.
nbits
;
dci_pdu_rel15
->
carrier_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
carrier_indicator
.
nbits
)
-
1
);
// UL/SUL Indicator
pos
+=
dci_pdu_rel15
->
ul_sul_indicator
.
nbits
;
dci_pdu_rel15
->
ul_sul_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
ul_sul_indicator
.
nbits
)
-
1
);
// BWP Indicator
pos
+=
dci_pdu_rel15
->
bwp_indicator
.
nbits
;
dci_pdu_rel15
->
bwp_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
bwp_indicator
.
nbits
)
-
1
);
// Freq domain assignment max 16 bit
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB_UL
*
(
N_RB_UL
+
1
))
>>
1
)
);
//pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
pos
+=
fsize
;
//pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
dci_pdu_rel15
->
frequency_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
fsize
)
-
1
);
// Time domain assignment 4bit
//pos+=4;
pos
+=
dci_pdu_rel15
->
time_domain_assignment
.
nbits
;
dci_pdu_rel15
->
time_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x3
;
// Not supported yet - skip for now
// Frequency hopping flag – 1 bit
//pos++;
//dci_pdu_rel15->frequency_hopping_flag.val= (*dci_pdu>>(dci_size-pos))&1;
// MCS 5 bit
pos
+=
5
;
dci_pdu_rel15
->
mcs
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1f
;
// New data indicator 1bit
pos
++
;
dci_pdu_rel15
->
ndi
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
1
;
// Redundancy version 2bit
pos
+=
2
;
dci_pdu_rel15
->
rv
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
3
;
// HARQ process number 4bit
pos
+=
4
;
dci_pdu_rel15
->
harq_pid
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0xf
;
// 1st Downlink assignment index
pos
+=
dci_pdu_rel15
->
dai
[
0
].
nbits
;
dci_pdu_rel15
->
dai
[
0
].
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
dai
[
0
].
nbits
)
-
1
);
// 2nd Downlink assignment index
pos
+=
dci_pdu_rel15
->
dai
[
1
].
nbits
;
dci_pdu_rel15
->
dai
[
1
].
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
dai
[
1
].
nbits
)
-
1
);
// TPC command for scheduled PUSCH – 2 bits
pos
+=
2
;
dci_pdu_rel15
->
tpc
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
3
;
// SRS resource indicator
pos
+=
dci_pdu_rel15
->
srs_resource_indicator
.
nbits
;
dci_pdu_rel15
->
srs_resource_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
srs_resource_indicator
.
nbits
)
-
1
);
// Precoding info and n. of layers
pos
+=
dci_pdu_rel15
->
precoding_information
.
nbits
;
dci_pdu_rel15
->
precoding_information
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
precoding_information
.
nbits
)
-
1
);
// Antenna ports
pos
+=
dci_pdu_rel15
->
antenna_ports
.
nbits
;
dci_pdu_rel15
->
antenna_ports
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
antenna_ports
.
nbits
)
-
1
);
// SRS request
pos
+=
dci_pdu_rel15
->
srs_request
.
nbits
;
dci_pdu_rel15
->
srs_request
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
srs_request
.
nbits
)
-
1
);
// CSI request
pos
+=
dci_pdu_rel15
->
csi_request
.
nbits
;
dci_pdu_rel15
->
csi_request
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
csi_request
.
nbits
)
-
1
);
// CBG transmission information
pos
+=
dci_pdu_rel15
->
cbgti
.
nbits
;
dci_pdu_rel15
->
cbgti
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
cbgti
.
nbits
)
-
1
);
// PTRS DMRS association
pos
+=
dci_pdu_rel15
->
ptrs_dmrs_association
.
nbits
;
dci_pdu_rel15
->
ptrs_dmrs_association
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
ptrs_dmrs_association
.
nbits
)
-
1
);
// Beta offset indicator
pos
+=
dci_pdu_rel15
->
beta_offset_indicator
.
nbits
;
dci_pdu_rel15
->
beta_offset_indicator
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
beta_offset_indicator
.
nbits
)
-
1
);
// DMRS sequence initialization
pos
+=
dci_pdu_rel15
->
dmrs_sequence_initialization
.
nbits
;
dci_pdu_rel15
->
dmrs_sequence_initialization
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
dci_pdu_rel15
->
dmrs_sequence_initialization
.
nbits
)
-
1
);
// UL-SCH indicator
pos
+=
1
;
dci_pdu_rel15
->
ulsch_indicator
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
0x1
;
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value)
dci_pdu->= ((uint64_t)*dci_pdu>>(dci_size-pos)ul_sul_indicator&1)<<(dci_size-pos++);
*/
break
;
}
break
;
}
}
...
...
This diff is collapsed.
Click to expand it.
openair2/NR_UE_PHY_INTERFACE/NR_IF_Module.c
View file @
c91d689d
...
...
@@ -155,7 +155,7 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info, NR_UL_TIME_ALIGNMENT_
ul_config
->
number_pdus
=
0
;
//hook up pointers
mac
->
scheduled_response
.
dl_config
=
dl_config
;
mac
->
scheduled_response
.
ul_config
=
ul_config
;
mac
->
scheduled_response
.
ul_config
=
NULL
;
mac
->
scheduled_response
.
tx_request
=
&
mac
->
tx_request
;
mac
->
scheduled_response
.
module_id
=
dl_info
->
module_id
;
mac
->
scheduled_response
.
CC_id
=
dl_info
->
cc_id
;
...
...
This diff is collapsed.
Click to expand it.
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