Commit fad5fbda authored by hardy's avatar hardy

Merge remote-tracking branch 'origin/NR_CSIRS_tomerge' into integration_2021_wk30

parents d7839d8a 618e33ac
...@@ -283,7 +283,7 @@ The following features are valid for the gNB and the 5G-NR UE. ...@@ -283,7 +283,7 @@ The following features are valid for the gNB and the 5G-NR UE.
- PTRS support - PTRS support
- Support for 1, 2 and 4 TX antennas - Support for 1, 2 and 4 TX antennas
- Support for up to 2 layers (currently limited to DMRS configuration type 2) - Support for up to 2 layers (currently limited to DMRS configuration type 2)
* NR-CSI Generation of sequence at PHY (**under integration**) * NR-CSIRS Generation of sequence at PHY
* NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). * NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc).
- PUSCH mapping type A and B - PUSCH mapping type A and B
- DMRS configuration type 1 and 2 - DMRS configuration type 1 and 2
...@@ -319,6 +319,7 @@ The following features are valid for the gNB and the 5G-NR UE. ...@@ -319,6 +319,7 @@ The following features are valid for the gNB and the 5G-NR UE.
- MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU - MAC <-> PHY data interface using FAPI P7 interface for BCH PDU, DCI PDU, PDSCH PDU
- Scheduler procedures for SIB1 - Scheduler procedures for SIB1
- Scheduler procedures for RA - Scheduler procedures for RA
- Scheduler procedures for CSI-RS
- MAC downlink scheduler (fixed allocations) - MAC downlink scheduler (fixed allocations)
- MAC header generation (including timing advance) - MAC header generation (including timing advance)
- ACK / NACK handling and HARQ procedures for downlink - ACK / NACK handling and HARQ procedures for downlink
...@@ -349,7 +350,6 @@ The following features are valid for the gNB and the 5G-NR UE. ...@@ -349,7 +350,6 @@ The following features are valid for the gNB and the 5G-NR UE.
- PTRS support - PTRS support
- Support for 1, 2 and 4 RX antennas - Support for 1, 2 and 4 RX antennas
- Support for up to 2 layers (currently limited to DMRS configuration type 2) - Support for up to 2 layers (currently limited to DMRS configuration type 2)
* NR-CSI Generation of sequence at PHY (**under integration**)
* NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc). * NR-PUSCH (including Segmentation, LDPC encoding, rate matching, scrambling, modulation, RB mapping, etc).
- PUSCH mapping type A and B - PUSCH mapping type A and B
- DMRS configuration type 1 and 2 - DMRS configuration type 1 and 2
......
...@@ -1571,8 +1571,7 @@ typedef struct ...@@ -1571,8 +1571,7 @@ typedef struct
{ {
uint8_t csi_part1_crc; uint8_t csi_part1_crc;
uint16_t csi_part1_bit_len; uint16_t csi_part1_bit_len;
//! fixme uint8_t* csi_part1_payload;
uint8_t* csi_part1_payload;//uint8_t[ceil(csiPart1BitLen/8)]
} nfapi_nr_csi_part1_pdu_t; } nfapi_nr_csi_part1_pdu_t;
...@@ -1581,8 +1580,7 @@ typedef struct ...@@ -1581,8 +1580,7 @@ typedef struct
{ {
uint8_t csi_part2_crc; uint8_t csi_part2_crc;
uint16_t csi_part2_bit_len; uint16_t csi_part2_bit_len;
//! fixme uint8_t* csi_part2_payload;
uint8_t* csi_part2_payload;//uint8_t[ceil(csiPart2BitLen/8)]
} nfapi_nr_csi_part2_pdu_t; } nfapi_nr_csi_part2_pdu_t;
//table 3-63 //table 3-63
......
...@@ -227,16 +227,14 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB, ...@@ -227,16 +227,14 @@ int phy_init_nr_gNB(PHY_VARS_gNB *gNB,
} }
} }
nr_init_csi_rs(gNB, cfg->cell_config.phy_cell_id.value);
/* Generate low PAPR type 1 sequences for PUSCH DMRS, these are used if transform precoding is enabled. */ /* Generate low PAPR type 1 sequences for PUSCH DMRS, these are used if transform precoding is enabled. */
generate_lowpapr_typ1_refsig_sequences(SHRT_MAX); generate_lowpapr_typ1_refsig_sequences(SHRT_MAX);
nr_init_csi_rs(gNB, 0); // TODO scramblingID currently hardcoded to 0, to be taken from higher layer parameter scramblingID when implemented
/// Transport init necessary for NR synchro /// Transport init necessary for NR synchro
init_nr_transport(gNB); init_nr_transport(gNB);
gNB->first_run_I0_measurements = 1; gNB->first_run_I0_measurements = 1;
common_vars->rxdata = (int32_t **)malloc16(Prx*sizeof(int32_t*)); common_vars->rxdata = (int32_t **)malloc16(Prx*sizeof(int32_t*));
......
...@@ -145,7 +145,7 @@ void nr_init_csi_rs(PHY_VARS_gNB* gNB, uint32_t Nid) ...@@ -145,7 +145,7 @@ void nr_init_csi_rs(PHY_VARS_gNB* gNB, uint32_t Nid)
reset = 1; reset = 1;
x2 = ((1<<10) * (fp->symbols_per_slot*slot+symb+1) * ((Nid<<1)+1) + (Nid)); x2 = ((1<<10) * (fp->symbols_per_slot*slot+symb+1) * ((Nid<<1)+1) + (Nid));
for (uint32_t n=0; n<NR_MAX_PDCCH_DMRS_INIT_LENGTH_DWORD; n++) { for (uint32_t n=0; n<NR_MAX_CSI_RS_INIT_LENGTH_DWORD; n++) {
csi_rs[slot][symb][n] = lte_gold_generic(&x1, &x2, reset); csi_rs[slot][symb][n] = lte_gold_generic(&x1, &x2, reset);
reset = 0; reset = 0;
} }
......
...@@ -22,17 +22,22 @@ ...@@ -22,17 +22,22 @@
#include "PHY/NR_TRANSPORT/nr_transport_proto.h" #include "PHY/NR_TRANSPORT/nr_transport_proto.h"
#include "PHY/MODULATION/nr_modulation.h" #include "PHY/MODULATION/nr_modulation.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
//#define NR_CSIRS_DEBUG //#define NR_CSIRS_DEBUG
int nr_generate_csi_rs(uint32_t **gold_csi_rs,
int32_t** txdataF,
int16_t amp,
NR_DL_FRAME_PARMS frame_parms,
nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_params)
{
int16_t mod_csi[frame_parms.symbols_per_slot][NR_MAX_CSI_RS_LENGTH>>1]; void nr_generate_csi_rs(PHY_VARS_gNB *gNB,
int16_t amp,
nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_params,
uint16_t cell_id,
int slot){
NR_DL_FRAME_PARMS frame_parms=gNB->frame_parms;
int32_t **txdataF = gNB->common_vars.txdataF;
int txdataF_offset = (slot%2)*frame_parms.samples_per_slot_wCP;
uint32_t **gold_csi_rs = gNB->nr_gold_csi_rs[slot];
int16_t mod_csi[frame_parms.symbols_per_slot][NR_MAX_CSI_RS_LENGTH>>1] __attribute__((aligned(16)));;
uint16_t b = csi_params.freq_domain; uint16_t b = csi_params.freq_domain;
uint16_t n, csi_bw, csi_start, p, k, l, mprime, na, kpn, csi_length; uint16_t n, csi_bw, csi_start, p, k, l, mprime, na, kpn, csi_length;
uint8_t size, ports, kprime, lprime, i, gs; uint8_t size, ports, kprime, lprime, i, gs;
...@@ -45,6 +50,22 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs, ...@@ -45,6 +50,22 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs,
AssertFatal(b!=0, "Invalid CSI frequency domain mapping: no bit selected in bitmap\n"); AssertFatal(b!=0, "Invalid CSI frequency domain mapping: no bit selected in bitmap\n");
// pre-computed for scrambling id equel to cell id
// if the scrambling id is not the cell id we need to re-initialize the rs
if (csi_params.scramb_id != cell_id) {
uint8_t reset;
uint32_t x1, x2;
uint32_t Nid = csi_params.scramb_id;
for (uint8_t symb=0; symb<frame_parms.symbols_per_slot; symb++) {
reset = 1;
x2 = ((1<<10) * (frame_parms.symbols_per_slot*slot+symb+1) * ((Nid<<1)+1) + (Nid));
for (uint32_t n=0; n<NR_MAX_CSI_RS_INIT_LENGTH_DWORD; n++) {
gold_csi_rs[symb][n] = lte_gold_generic(&x1, &x2, reset);
reset = 0;
}
}
}
switch (csi_params.row) { switch (csi_params.row) {
// implementation of table 7.4.1.5.3-1 of 38.211 // implementation of table 7.4.1.5.3-1 of 38.211
// lprime and kprime are the max value of l' and k' // lprime and kprime are the max value of l' and k'
...@@ -519,19 +540,15 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs, ...@@ -519,19 +540,15 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs,
case 0: case 0:
beta = (amp*ONE_OVER_SQRT2_Q15)>>15; beta = (amp*ONE_OVER_SQRT2_Q15)>>15;
break; break;
case 1: case 1:
beta = amp; beta = amp;
break; break;
case 2: case 2:
beta = (amp*ONE_OVER_SQRT2_Q15)>>14; beta = (amp*ONE_OVER_SQRT2_Q15)>>14;
break; break;
case 3: case 3:
beta = amp<<1; beta = amp<<1;
break; break;
default: default:
AssertFatal(0==1, "Invalid SS power offset density index for CSI\n"); AssertFatal(0==1, "Invalid SS power offset density index for CSI\n");
} }
...@@ -548,7 +565,6 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs, ...@@ -548,7 +565,6 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs,
nr_modulation(gold_csi_rs[symb+1], csi_length, DMRS_MOD_ORDER, mod_csi[symb+1]); nr_modulation(gold_csi_rs[symb+1], csi_length, DMRS_MOD_ORDER, mod_csi[symb+1]);
} }
} }
} }
uint16_t start_sc = frame_parms.first_carrier_offset; uint16_t start_sc = frame_parms.first_carrier_offset;
...@@ -586,16 +602,17 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs, ...@@ -586,16 +602,17 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs,
} }
// ZP CSI RS // ZP CSI RS
if (csi_params.csi_type == 2) { if (csi_params.csi_type == 2) {
((int16_t*)txdataF[p])[(l*frame_parms.ofdm_symbol_size + k)<<1] = 0; ((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1)+(2*txdataF_offset)] = 0;
((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = 0; ((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1)+1+(2*txdataF_offset)] = 0;
} }
else { else {
((int16_t*)txdataF[p])[(l*frame_parms.ofdm_symbol_size + k)<<1] = (beta*wt*wf*mod_csi[l][mprime<<1]) >> 15; ((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1)+(2*txdataF_offset)] = (beta*wt*wf*mod_csi[l][mprime<<1]) >> 15;
((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1] = (beta*wt*wf*mod_csi[l][(mprime<<1) + 1]) >> 15; ((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1)+1+(2*txdataF_offset)] = (beta*wt*wf*mod_csi[l][(mprime<<1) + 1]) >> 15;
} }
#ifdef NR_CSIRS_DEBUG #ifdef NR_CSIRS_DEBUG
printf("l,k (%d %d) seq. index %d \t port %d \t (%d,%d)\n",l,k-start_sc,mprime,p+3000,((int16_t*)txdataF[p])[(l*frame_parms.ofdm_symbol_size + k)<<1], printf("l,k (%d %d) seq. index %d \t port %d \t (%d,%d)\n",l,k,mprime,p+3000,
((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1) + 1]); ((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1)+(2*txdataF_offset)],
((int16_t*)txdataF[p])[((l*frame_parms.ofdm_symbol_size + k)<<1)+1+(2*txdataF_offset)]);
#endif #endif
} }
} }
...@@ -603,6 +620,4 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs, ...@@ -603,6 +620,4 @@ int nr_generate_csi_rs(uint32_t **gold_csi_rs,
} }
} }
} }
return 0;
} }
...@@ -326,11 +326,11 @@ void init_prach_list(PHY_VARS_gNB *gNB); ...@@ -326,11 +326,11 @@ void init_prach_list(PHY_VARS_gNB *gNB);
void init_prach_ru_list(RU_t *ru); void init_prach_ru_list(RU_t *ru);
void free_nr_ru_prach_entry(RU_t *ru, int prach_id); void free_nr_ru_prach_entry(RU_t *ru, int prach_id);
int nr_generate_csi_rs(uint32_t **gold_csi_rs, void nr_generate_csi_rs(PHY_VARS_gNB *gNB,
int32_t **txdataF,
int16_t amp, int16_t amp,
NR_DL_FRAME_PARMS frame_parms, nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_params,
nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_params); uint16_t cell_id,
int slot);
void free_nr_prach_entry(PHY_VARS_gNB *gNB, int prach_id); void free_nr_prach_entry(PHY_VARS_gNB *gNB, int prach_id);
......
...@@ -289,7 +289,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB, ...@@ -289,7 +289,7 @@ void nr_decode_pucch0(PHY_VARS_gNB *gNB,
int32_t corr_re[2]; int32_t corr_re[2];
int32_t corr_im[2]; int32_t corr_im[2];
//int32_t no_corr = 0;
int seq_index; int seq_index;
int64_t temp; int64_t temp;
int64_t av_corr=0; int64_t av_corr=0;
...@@ -1375,7 +1375,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, ...@@ -1375,7 +1375,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
rp2_im[aa] = (__m256i*)r_im_ext2[aa]; rp2_im[aa] = (__m256i*)r_im_ext2[aa];
} }
__m256i prod_re[Prx2],prod_im[Prx2]; __m256i prod_re[Prx2],prod_im[Prx2];
int64_t corr=0; uint64_t corr=0;
int cw_ML=0; int cw_ML=0;
...@@ -1389,7 +1389,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, ...@@ -1389,7 +1389,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
} }
printf("\n"); printf("\n");
#endif #endif
int64_t corr_tmp = 0; uint64_t corr_tmp = 0;
for (int group=0;group<ngroup;group++) { for (int group=0;group<ngroup;group++) {
// do complex correlation // do complex correlation
...@@ -1503,7 +1503,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, ...@@ -1503,7 +1503,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
corr_re = ( corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_re[aa]))[0]); corr_re = ( corr32_re[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_re[aa]))[0]);
corr_im = ( corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_im[aa]))[0]); corr_im = ( corr32_im[half_prb>>2][aa]/(2*nc_group_size*4/2)+((int16_t*)(&prod_im[aa]))[0]);
corr_tmp += corr_re*corr_re + corr_im*corr_im; corr_tmp += corr_re*corr_re + corr_im*corr_im;
/*
LOG_D(PHY,"pucch2 half_prb %d cw %d (%d,%d) aa %d: (%d,%d,%d,%d,%d,%d,%d,%d)x(%d,%d,%d,%d,%d,%d,%d,%d) (%d,%d)+(%d,%d) = (%d,%d) => %d\n", LOG_D(PHY,"pucch2 half_prb %d cw %d (%d,%d) aa %d: (%d,%d,%d,%d,%d,%d,%d,%d)x(%d,%d,%d,%d,%d,%d,%d,%d) (%d,%d)+(%d,%d) = (%d,%d) => %d\n",
half_prb,cw,cw&15,cw>>4,aa, half_prb,cw,cw&15,cw>>4,aa,
((int16_t*)&pucch2_polar_4bit[cw&15])[0],((int16_t*)&pucch2_polar_4bit[cw>>4])[0], ((int16_t*)&pucch2_polar_4bit[cw&15])[0],((int16_t*)&pucch2_polar_4bit[cw>>4])[0],
...@@ -1520,15 +1520,15 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, ...@@ -1520,15 +1520,15 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
corr_re, corr_re,
corr_im, corr_im,
corr_tmp); corr_tmp);
*/
} }
corr16 = _mm_set1_epi16((int16_t)(corr_tmp>>8)); corr16 = _mm_set1_epi16((int16_t)(corr_tmp>>8));
/*
LOG_D(PHY,"half_prb %d cw %d corr16 %d\n",half_prb,cw,corr_tmp>>8); LOG_D(PHY,"half_prb %d cw %d corr16 %d\n",half_prb,cw,corr_tmp>>8);
*/
llr_num = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_num_lut[cw]),llr_num); llr_num = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_num_lut[cw]),llr_num);
llr_den = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_den_lut[cw]),llr_den); llr_den = _mm_max_epi16(_mm_mullo_epi16(corr16,pucch2_polar_llr_den_lut[cw]),llr_den);
/*
LOG_D(PHY,"lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n", LOG_D(PHY,"lut_num (%d,%d,%d,%d,%d,%d,%d,%d)\n",
((int16_t*)&pucch2_polar_llr_num_lut[cw])[0], ((int16_t*)&pucch2_polar_llr_num_lut[cw])[0],
((int16_t*)&pucch2_polar_llr_num_lut[cw])[1], ((int16_t*)&pucch2_polar_llr_num_lut[cw])[1],
...@@ -1557,7 +1557,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB, ...@@ -1557,7 +1557,7 @@ void nr_decode_pucch2(PHY_VARS_gNB *gNB,
((int16_t*)&llr_den)[5], ((int16_t*)&llr_den)[5],
((int16_t*)&llr_den)[6], ((int16_t*)&llr_den)[6],
((int16_t*)&llr_den)[7]); ((int16_t*)&llr_den)[7]);
*/
} }
// compute llrs // compute llrs
llrs[half_prb] = _mm_subs_epi16(llr_num,llr_den); llrs[half_prb] = _mm_subs_epi16(llr_num,llr_den);
......
...@@ -120,6 +120,13 @@ typedef struct { ...@@ -120,6 +120,13 @@ typedef struct {
nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu; nfapi_nr_dl_tti_pdcch_pdu pdcch_pdu;
} NR_gNB_PDCCH_t; } NR_gNB_PDCCH_t;
typedef struct {
uint8_t active;
int frame;
int slot;
nfapi_nr_dl_tti_csi_rs_pdu csirs_pdu;
} NR_gNB_CSIRS_t;
typedef struct { typedef struct {
int frame; int frame;
int slot; int slot;
...@@ -760,6 +767,7 @@ typedef struct PHY_VARS_gNB_s { ...@@ -760,6 +767,7 @@ typedef struct PHY_VARS_gNB_s {
NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX]; NR_gNB_PUSCH *pusch_vars[NUMBER_OF_NR_ULSCH_MAX];
NR_gNB_PUCCH_t *pucch[NUMBER_OF_NR_PUCCH_MAX]; NR_gNB_PUCCH_t *pucch[NUMBER_OF_NR_PUCCH_MAX];
NR_gNB_PDCCH_t pdcch_pdu[NUMBER_OF_NR_PDCCH_MAX]; NR_gNB_PDCCH_t pdcch_pdu[NUMBER_OF_NR_PDCCH_MAX];
NR_gNB_CSIRS_t csirs_pdu[NUMBER_OF_NR_CSIRS_MAX];
NR_gNB_UL_PDCCH_t ul_pdcch_pdu[NUMBER_OF_NR_PDCCH_MAX]; NR_gNB_UL_PDCCH_t ul_pdcch_pdu[NUMBER_OF_NR_PDCCH_MAX];
NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams NR_gNB_DLSCH_t *dlsch[NUMBER_OF_NR_DLSCH_MAX][2]; // Nusers times two spatial streams
NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords] NR_gNB_ULSCH_t *ulsch[NUMBER_OF_NR_ULSCH_MAX][2]; // [Nusers times][2 codewords]
......
...@@ -111,10 +111,9 @@ void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, ...@@ -111,10 +111,9 @@ void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB,
nr_fill_dci(gNB,frame,slot,pdcch_pdu); nr_fill_dci(gNB,frame,slot,pdcch_pdu);
} }
void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB, void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB,
int frame, int slot, int frame, int slot,
nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu) { nfapi_nr_ul_dci_request_pdus_t *ul_dci_request_pdu) {
...@@ -128,6 +127,30 @@ void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB, ...@@ -128,6 +127,30 @@ void handle_nfapi_nr_ul_dci_pdu(PHY_VARS_gNB *gNB,
} }
void handle_nfapi_nr_csirs_pdu(PHY_VARS_gNB *gNB,
int frame, int slot,
nfapi_nr_dl_tti_csi_rs_pdu *csirs_pdu) {
int found = 0;
for (int id=0; id<NUMBER_OF_NR_CSIRS_MAX; id++) {
NR_gNB_CSIRS_t *csirs = &gNB->csirs_pdu[id];
if (csirs->active == 0) {
LOG_D(PHY,"Frame %d Slot %d CSI_RS with ID %d is now active\n",frame,slot,id);
csirs->frame = frame;
csirs->slot = slot;
csirs->active = 1;
memcpy((void*)&csirs->csirs_pdu, (void*)csirs_pdu, sizeof(nfapi_nr_dl_tti_csi_rs_pdu));
found = 1;
break;
}
}
if (found == 0)
LOG_E(MAC,"CSI-RS list is full\n");
}
void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot, void handle_nr_nfapi_pdsch_pdu(PHY_VARS_gNB *gNB,int frame,int slot,
nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu, nfapi_nr_dl_tti_pdsch_pdu *pdsch_pdu,
uint8_t *sdu) uint8_t *sdu)
...@@ -195,6 +218,12 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){ ...@@ -195,6 +218,12 @@ void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO){
pdcch_received = 1; pdcch_received = 1;
break; break;
case NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE:
LOG_D(PHY,"frame %d, slot %d, Got NFAPI_NR_DL_TTI_CSI_RS_PDU_TYPE for %d.%d\n",frame,slot,DL_req->SFN,DL_req->Slot);
handle_nfapi_nr_csirs_pdu(gNB,
frame, slot,
&dl_tti_pdu->csi_rs_pdu);
break;
case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE: case NFAPI_NR_DL_TTI_PDSCH_PDU_TYPE:
{ {
......
...@@ -43,6 +43,10 @@ void handle_nr_nfapi_ssb_pdu(PHY_VARS_gNB *gNB, ...@@ -43,6 +43,10 @@ void handle_nr_nfapi_ssb_pdu(PHY_VARS_gNB *gNB,
void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO); void nr_schedule_response(NR_Sched_Rsp_t *Sched_INFO);
void handle_nfapi_nr_csirs_pdu(PHY_VARS_gNB *gNB,
int frame, int slot,
nfapi_nr_dl_tti_csi_rs_pdu *csirs_pdu);
void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB, void handle_nfapi_nr_pdcch_pdu(PHY_VARS_gNB *gNB,
int frame, int subframe, int frame, int subframe,
nfapi_nr_dl_tti_pdcch_pdu *dcl_dl_pdu); nfapi_nr_dl_tti_pdcch_pdu *dcl_dl_pdu);
......
...@@ -194,6 +194,18 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB, ...@@ -194,6 +194,18 @@ void phy_procedures_gNB_TX(PHY_VARS_gNB *gNB,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0); VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_GENERATE_DLSCH,0);
} }
for (int i=0;i<NUMBER_OF_NR_CSIRS_MAX;i++){
NR_gNB_CSIRS_t *csirs = &gNB->csirs_pdu[i];
if ((csirs->active == 1) &&
(csirs->frame == frame) &&
(csirs->slot == slot) ) {
LOG_D(PHY, "CSI-RS generation started in frame %d.%d\n",frame,slot);
nfapi_nr_dl_tti_csi_rs_pdu_rel15_t csi_params = csirs->csirs_pdu.csi_rs_pdu_rel15;
nr_generate_csi_rs(gNB, AMP, csi_params, gNB->gNB_config.cell_config.phy_cell_id.value, slot);
csirs->active = 0;
}
}
if (do_meas==1) stop_meas(&gNB->phy_proc_tx); if (do_meas==1) stop_meas(&gNB->phy_proc_tx);
if ((frame&127) == 0) dump_pdsch_stats(gNB); if ((frame&127) == 0) dump_pdsch_stats(gNB);
......
...@@ -430,6 +430,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -430,6 +430,9 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
// This schedule SR // This schedule SR
nr_sr_reporting(module_idP, frame, slot); nr_sr_reporting(module_idP, frame, slot);
// Schedule CSI-RS transmission
nr_csirs_scheduling(module_idP, frame, slot, nr_slots_per_frame[*scc->ssbSubcarrierSpacing]);
// Schedule CSI measurement reporting: check in slot 0 for the whole frame // Schedule CSI measurement reporting: check in slot 0 for the whole frame
if (slot == 0) if (slot == 0)
nr_csi_meas_reporting(module_idP, frame, slot); nr_csi_meas_reporting(module_idP, frame, slot);
......
...@@ -178,7 +178,13 @@ void nr_schedule_pucch(int Mod_idP, ...@@ -178,7 +178,13 @@ void nr_schedule_pucch(int Mod_idP,
frame_t frameP, frame_t frameP,
sub_frame_t slotP); sub_frame_t slotP);
void csi_period_offset(const NR_CSI_ReportConfig_t *csirep, void nr_csirs_scheduling(int Mod_idP,
frame_t frame,
sub_frame_t slot,
int n_slots_frame);
void csi_period_offset(NR_CSI_ReportConfig_t *csirep,
NR_NZP_CSI_RS_Resource_t *nzpcsi,
int *period, int *offset); int *period, int *offset);
void nr_csi_meas_reporting(int Mod_idP, void nr_csi_meas_reporting(int Mod_idP,
......
...@@ -440,7 +440,8 @@ struct CRI_RI_LI_PMI_CQI { ...@@ -440,7 +440,8 @@ struct CRI_RI_LI_PMI_CQI {
uint8_t li; uint8_t li;
uint8_t pmi_x1; uint8_t pmi_x1;
uint8_t pmi_x2; uint8_t pmi_x2;
uint8_t cqi; uint8_t wb_cqi_1tb;
uint8_t wb_cqi_2tb;
}; };
typedef struct CRI_SSB_RSRP { typedef struct CRI_SSB_RSRP {
......
This diff is collapsed.
...@@ -13,7 +13,8 @@ ...@@ -13,7 +13,8 @@
# define NUMBER_OF_NR_ULSCH_MAX 8 # define NUMBER_OF_NR_ULSCH_MAX 8
# define NUMBER_OF_NR_DLSCH_MAX 8 # define NUMBER_OF_NR_DLSCH_MAX 8
# define NUMBER_OF_NR_UCI_MAX 16 # define NUMBER_OF_NR_UCI_MAX 16
# define nUMBER_OF_NR_SRS_MAX 16 # define NUMBER_OF_NR_SRS_MAX 16
# define NUMBER_OF_NR_CSIRS_MAX 16
# define NUMBER_OF_SCH_STATS_MAX 16 # define NUMBER_OF_SCH_STATS_MAX 16
# define NUMBER_OF_NR_SCH_STATS_MAX 16 # define NUMBER_OF_NR_SCH_STATS_MAX 16
......
...@@ -263,7 +263,7 @@ RUs = ( ...@@ -263,7 +263,7 @@ RUs = (
max_pdschReferenceSignalPower = -27; max_pdschReferenceSignalPower = -27;
max_rxgain = 118; max_rxgain = 118;
eNB_instances = [0]; eNB_instances = [0];
clock_src = "external"; clock_src = "internal";
} }
); );
......
...@@ -249,7 +249,7 @@ RUs = ( ...@@ -249,7 +249,7 @@ RUs = (
max_pdschReferenceSignalPower = -27; max_pdschReferenceSignalPower = -27;
max_rxgain = 114; max_rxgain = 114;
eNB_instances = [0]; eNB_instances = [0];
#clock_src = "external"; clock_src = "internal";
} }
); );
......
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