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Commit 408d06a3 authored by Ruhung's avatar Ruhung Committed by GitHub
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arm/neon riscv64: additional RVV implementations - part1 (#1188) 

Contains RVV implementations for the following Neon instructions.

`abs`, `addl`, `addl_high`, `addlv`, `addv`, `cge`, `cgt`, `cle`, `clez`, `clt`, `cnt`, `fma`, `fms`, `fms_n`, `get_high`, `get_low`, `hsub`, `mla`, `mla_n`, `mlal`, `mlal_high`, `mlal_high_n`, `mlal_n`, `mls`, `mls_n`, `mlsl`, `mlsl_high`, `mlsl_high_n`, `mlsl_n`, `qsub`, `qtbl`, `qtbx`, `rbit`, `recpe`, `rev16`, `rev32`, `rev64`, `subl`, `subl_high`, `subw`, `subw_high`, `tbl`, `tbx`
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arm/neon/abs.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_ABS_H) #if !defined(SIMDE_ARM_NEON_ABS_H)
...@@ -74,10 +75,14 @@ simde_vabs_f16(simde_float16x4_t a) { ...@@ -74,10 +75,14 @@ simde_vabs_f16(simde_float16x4_t a) {
r_, r_,
a_ = simde_float16x4_to_private(a); a_ = simde_float16x4_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
r_.sv64 = __riscv_vfabs_v_f16m1(a_.sv64 , 4);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_vabsh_f16(a_.values[i]); r_.values[i] = simde_vabsh_f16(a_.values[i]);
} }
#endif
return simde_float16x4_from_private(r_); return simde_float16x4_from_private(r_);
#endif #endif
...@@ -97,10 +102,14 @@ simde_vabs_f32(simde_float32x2_t a) { ...@@ -97,10 +102,14 @@ simde_vabs_f32(simde_float32x2_t a) {
r_, r_,
a_ = simde_float32x2_to_private(a); a_ = simde_float32x2_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vfabs_v_f32m1(a_.sv64 , 2);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = a_.values[i] < 0 ? -a_.values[i] : a_.values[i]; r_.values[i] = a_.values[i] < 0 ? -a_.values[i] : a_.values[i];
} }
#endif
return simde_float32x2_from_private(r_); return simde_float32x2_from_private(r_);
#endif #endif
...@@ -120,10 +129,14 @@ simde_vabs_f64(simde_float64x1_t a) { ...@@ -120,10 +129,14 @@ simde_vabs_f64(simde_float64x1_t a) {
r_, r_,
a_ = simde_float64x1_to_private(a); a_ = simde_float64x1_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vfabs_v_f64m1(a_.sv64 , 1);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = a_.values[i] < 0 ? -a_.values[i] : a_.values[i]; r_.values[i] = a_.values[i] < 0 ? -a_.values[i] : a_.values[i];
} }
#endif
return simde_float64x1_from_private(r_); return simde_float64x1_from_private(r_);
#endif #endif
...@@ -145,6 +158,8 @@ simde_vabs_s8(simde_int8x8_t a) { ...@@ -145,6 +158,8 @@ simde_vabs_s8(simde_int8x8_t a) {
#if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_abs_pi8(a_.m64); r_.m64 = _mm_abs_pi8(a_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmax_vv_i8m1(a_.sv64 , __riscv_vneg_v_i8m1(a_.sv64 , 8) , 8);
#elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762) #elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT8_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT8_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
...@@ -175,6 +190,8 @@ simde_vabs_s16(simde_int16x4_t a) { ...@@ -175,6 +190,8 @@ simde_vabs_s16(simde_int16x4_t a) {
#if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_abs_pi16(a_.m64); r_.m64 = _mm_abs_pi16(a_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmax_vv_i16m1(a_.sv64 , __riscv_vneg_v_i16m1(a_.sv64 , 4) , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100761) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100761)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT16_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT16_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
...@@ -205,6 +222,8 @@ simde_vabs_s32(simde_int32x2_t a) { ...@@ -205,6 +222,8 @@ simde_vabs_s32(simde_int32x2_t a) {
#if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_abs_pi32(a_.m64); r_.m64 = _mm_abs_pi32(a_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmax_vv_i32m1(a_.sv64 , __riscv_vneg_v_i32m1(a_.sv64 , 2) , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100761) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100761)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT32_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT32_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
...@@ -233,7 +252,9 @@ simde_vabs_s64(simde_int64x1_t a) { ...@@ -233,7 +252,9 @@ simde_vabs_s64(simde_int64x1_t a) {
r_, r_,
a_ = simde_int64x1_to_private(a); a_ = simde_int64x1_to_private(a);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmax_vv_i64m1(a_.sv64 , __riscv_vneg_v_i64m1(a_.sv64 , 1) , 1);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT64_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT64_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
#else #else
...@@ -261,10 +282,14 @@ simde_vabsq_f16(simde_float16x8_t a) { ...@@ -261,10 +282,14 @@ simde_vabsq_f16(simde_float16x8_t a) {
r_, r_,
a_ = simde_float16x8_to_private(a); a_ = simde_float16x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
r_.sv128 = __riscv_vfabs_v_f16m1(a_.sv128 , 8);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_vabsh_f16(a_.values[i]); r_.values[i] = simde_vabsh_f16(a_.values[i]);
} }
#endif
return simde_float16x8_from_private(r_); return simde_float16x8_from_private(r_);
#endif #endif
...@@ -288,6 +313,8 @@ simde_vabsq_f32(simde_float32x4_t a) { ...@@ -288,6 +313,8 @@ simde_vabsq_f32(simde_float32x4_t a) {
#if defined(SIMDE_WASM_SIMD128_NATIVE) #if defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_f32x4_abs(a_.v128); r_.v128 = wasm_f32x4_abs(a_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfabs_v_f32m1(a_.sv128 , 4);
#elif defined(SIMDE_X86_SSE_NATIVE) #elif defined(SIMDE_X86_SSE_NATIVE)
simde_float32 mask_; simde_float32 mask_;
uint32_t u32_ = UINT32_C(0x7FFFFFFF); uint32_t u32_ = UINT32_C(0x7FFFFFFF);
...@@ -325,6 +352,8 @@ simde_vabsq_f64(simde_float64x2_t a) { ...@@ -325,6 +352,8 @@ simde_vabsq_f64(simde_float64x2_t a) {
uint64_t u64_ = UINT64_C(0x7FFFFFFFFFFFFFFF); uint64_t u64_ = UINT64_C(0x7FFFFFFFFFFFFFFF);
simde_memcpy(&mask_, &u64_, sizeof(u64_)); simde_memcpy(&mask_, &u64_, sizeof(u64_));
r_.m128d = _mm_and_pd(_mm_set1_pd(mask_), a_.m128d); r_.m128d = _mm_and_pd(_mm_set1_pd(mask_), a_.m128d);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfabs_v_f64m1(a_.sv128 , 2);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -358,6 +387,8 @@ simde_vabsq_s8(simde_int8x16_t a) { ...@@ -358,6 +387,8 @@ simde_vabsq_s8(simde_int8x16_t a) {
r_.m128i = _mm_min_epu8(a_.m128i, _mm_sub_epi8(_mm_setzero_si128(), a_.m128i)); r_.m128i = _mm_min_epu8(a_.m128i, _mm_sub_epi8(_mm_setzero_si128(), a_.m128i));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i8x16_abs(a_.v128); r_.v128 = wasm_i8x16_abs(a_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmax_vv_i8m1(a_.sv128 , __riscv_vneg_v_i8m1(a_.sv128 , 16) , 16);
#elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT8_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT8_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
...@@ -394,6 +425,8 @@ simde_vabsq_s16(simde_int16x8_t a) { ...@@ -394,6 +425,8 @@ simde_vabsq_s16(simde_int16x8_t a) {
r_.m128i = _mm_max_epi16(a_.m128i, _mm_sub_epi16(_mm_setzero_si128(), a_.m128i)); r_.m128i = _mm_max_epi16(a_.m128i, _mm_sub_epi16(_mm_setzero_si128(), a_.m128i));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i16x8_abs(a_.v128); r_.v128 = wasm_i16x8_abs(a_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmax_vv_i16m1(a_.sv128 , __riscv_vneg_v_i16m1(a_.sv128 , 8) , 8);
#elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT16_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT16_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
...@@ -431,6 +464,8 @@ simde_vabsq_s32(simde_int32x4_t a) { ...@@ -431,6 +464,8 @@ simde_vabsq_s32(simde_int32x4_t a) {
r_.m128i = _mm_sub_epi32(_mm_xor_si128(a_.m128i, m), m); r_.m128i = _mm_sub_epi32(_mm_xor_si128(a_.m128i, m), m);
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i32x4_abs(a_.v128); r_.v128 = wasm_i32x4_abs(a_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmax_vv_i32m1(a_.sv128 , __riscv_vneg_v_i32m1(a_.sv128 , 4) , 4);
#elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif (SIMDE_NATURAL_VECTOR_SIZE > 0) && defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT32_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT32_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
...@@ -452,6 +487,7 @@ simde_vabsq_s32(simde_int32x4_t a) { ...@@ -452,6 +487,7 @@ simde_vabsq_s32(simde_int32x4_t a) {
SIMDE_FUNCTION_ATTRIBUTES SIMDE_FUNCTION_ATTRIBUTES
simde_int64x2_t simde_int64x2_t
simde_vabsq_s64(simde_int64x2_t a) { simde_vabsq_s64(simde_int64x2_t a) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vabsq_s64(a); return vabsq_s64(a);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) #elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
...@@ -470,6 +506,8 @@ simde_vabsq_s64(simde_int64x2_t a) { ...@@ -470,6 +506,8 @@ simde_vabsq_s64(simde_int64x2_t a) {
r_.m128i = _mm_sub_epi64(_mm_xor_si128(a_.m128i, m), m); r_.m128i = _mm_sub_epi64(_mm_xor_si128(a_.m128i, m), m);
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i64x2_abs(a_.v128); r_.v128 = wasm_i64x2_abs(a_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmax_vv_i64m1(a_.sv128 , __riscv_vneg_v_i64m1(a_.sv128 , 2) , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
__typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT64_C(0)); __typeof__(r_.values) m = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), a_.values < INT64_C(0));
r_.values = (-a_.values & m) | (a_.values & ~m); r_.values = (-a_.values & m) | (a_.values & ~m);
......
arm/neon/addl.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_ADDL_H) #if !defined(SIMDE_ARM_NEON_ADDL_H)
...@@ -42,6 +43,13 @@ simde_int16x8_t ...@@ -42,6 +43,13 @@ simde_int16x8_t
simde_vaddl_s8(simde_int8x8_t a, simde_int8x8_t b) { simde_vaddl_s8(simde_int8x8_t a, simde_int8x8_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddl_s8(a, b); return vaddl_s8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private r_;
simde_int8x8_private a_ = simde_int8x8_to_private(a);
simde_int8x8_private b_ = simde_int8x8_to_private(b);
r_.sv128 = __riscv_vwadd_vv_i16m1(__riscv_vlmul_trunc_v_i8m1_i8mf2(a_.sv64) , __riscv_vlmul_trunc_v_i8m1_i8mf2(b_.sv64) , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vaddq_s16(simde_vmovl_s8(a), simde_vmovl_s8(b)); return simde_vaddq_s16(simde_vmovl_s8(a), simde_vmovl_s8(b));
#endif #endif
...@@ -56,6 +64,13 @@ simde_int32x4_t ...@@ -56,6 +64,13 @@ simde_int32x4_t
simde_vaddl_s16(simde_int16x4_t a, simde_int16x4_t b) { simde_vaddl_s16(simde_int16x4_t a, simde_int16x4_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddl_s16(a, b); return vaddl_s16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int16x4_private a_ = simde_int16x4_to_private(a);
simde_int16x4_private b_ = simde_int16x4_to_private(b);
r_.sv128 = __riscv_vwadd_vv_i32m1(__riscv_vlmul_trunc_v_i16m1_i16mf2(a_.sv64) , __riscv_vlmul_trunc_v_i16m1_i16mf2(b_.sv64) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vaddq_s32(simde_vmovl_s16(a), simde_vmovl_s16(b)); return simde_vaddq_s32(simde_vmovl_s16(a), simde_vmovl_s16(b));
#endif #endif
...@@ -70,6 +85,13 @@ simde_int64x2_t ...@@ -70,6 +85,13 @@ simde_int64x2_t
simde_vaddl_s32(simde_int32x2_t a, simde_int32x2_t b) { simde_vaddl_s32(simde_int32x2_t a, simde_int32x2_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddl_s32(a, b); return vaddl_s32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int32x2_private a_ = simde_int32x2_to_private(a);
simde_int32x2_private b_ = simde_int32x2_to_private(b);
r_.sv128 = __riscv_vwadd_vv_i64m1(__riscv_vlmul_trunc_v_i32m1_i32mf2(a_.sv64) , __riscv_vlmul_trunc_v_i32m1_i32mf2(b_.sv64) , 2);
return simde_int64x2_from_private(r_);
#else #else
return simde_vaddq_s64(simde_vmovl_s32(a), simde_vmovl_s32(b)); return simde_vaddq_s64(simde_vmovl_s32(a), simde_vmovl_s32(b));
#endif #endif
...@@ -84,6 +106,13 @@ simde_uint16x8_t ...@@ -84,6 +106,13 @@ simde_uint16x8_t
simde_vaddl_u8(simde_uint8x8_t a, simde_uint8x8_t b) { simde_vaddl_u8(simde_uint8x8_t a, simde_uint8x8_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddl_u8(a, b); return vaddl_u8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private r_;
simde_uint8x8_private a_ = simde_uint8x8_to_private(a);
simde_uint8x8_private b_ = simde_uint8x8_to_private(b);
r_.sv128 = __riscv_vwaddu_vv_u16m1(__riscv_vlmul_trunc_v_u8m1_u8mf2 (a_.sv64) , __riscv_vlmul_trunc_v_u8m1_u8mf2 (b_.sv64) , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vaddq_u16(simde_vmovl_u8(a), simde_vmovl_u8(b)); return simde_vaddq_u16(simde_vmovl_u8(a), simde_vmovl_u8(b));
#endif #endif
...@@ -98,6 +127,13 @@ simde_uint32x4_t ...@@ -98,6 +127,13 @@ simde_uint32x4_t
simde_vaddl_u16(simde_uint16x4_t a, simde_uint16x4_t b) { simde_vaddl_u16(simde_uint16x4_t a, simde_uint16x4_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddl_u16(a, b); return vaddl_u16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint16x4_private a_ = simde_uint16x4_to_private(a);
simde_uint16x4_private b_ = simde_uint16x4_to_private(b);
r_.sv128 = __riscv_vwaddu_vv_u32m1(__riscv_vlmul_trunc_v_u16m1_u16mf2 (a_.sv64) , __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv64) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vaddq_u32(simde_vmovl_u16(a), simde_vmovl_u16(b)); return simde_vaddq_u32(simde_vmovl_u16(a), simde_vmovl_u16(b));
#endif #endif
...@@ -112,6 +148,13 @@ simde_uint64x2_t ...@@ -112,6 +148,13 @@ simde_uint64x2_t
simde_vaddl_u32(simde_uint32x2_t a, simde_uint32x2_t b) { simde_vaddl_u32(simde_uint32x2_t a, simde_uint32x2_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vaddl_u32(a, b); return vaddl_u32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint32x2_private a_ = simde_uint32x2_to_private(a);
simde_uint32x2_private b_ = simde_uint32x2_to_private(b);
r_.sv128 = __riscv_vwaddu_vv_u64m1(__riscv_vlmul_trunc_v_u32m1_u32mf2 (a_.sv64) , __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv64) , 4);
return simde_uint64x2_from_private(r_);
#else #else
return simde_vaddq_u64(simde_vmovl_u32(a), simde_vmovl_u32(b)); return simde_vaddq_u64(simde_vmovl_u32(a), simde_vmovl_u32(b));
#endif #endif
......
arm/neon/addl_high.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_ADDL_HIGH_H) #if !defined(SIMDE_ARM_NEON_ADDL_HIGH_H)
...@@ -42,6 +43,15 @@ simde_int16x8_t ...@@ -42,6 +43,15 @@ simde_int16x8_t
simde_vaddl_high_s8(simde_int8x16_t a, simde_int8x16_t b) { simde_vaddl_high_s8(simde_int8x16_t a, simde_int8x16_t b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddl_high_s8(a, b); return vaddl_high_s8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private r_;
simde_int8x16_private a_ = simde_int8x16_to_private(a);
simde_int8x16_private b_ = simde_int8x16_to_private(b);
a_.sv128 = __riscv_vslidedown_vx_i8m1(a_.sv128 , 8 , 16);
b_.sv128 = __riscv_vslidedown_vx_i8m1(b_.sv128 , 8 , 16);
r_.sv128 = __riscv_vwadd_vv_i16m1(__riscv_vlmul_trunc_v_i8m1_i8mf2(a_.sv128) , __riscv_vlmul_trunc_v_i8m1_i8mf2(b_.sv128) , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vaddq_s16(simde_vmovl_high_s8(a), simde_vmovl_high_s8(b)); return simde_vaddq_s16(simde_vmovl_high_s8(a), simde_vmovl_high_s8(b));
#endif #endif
...@@ -56,6 +66,15 @@ simde_int32x4_t ...@@ -56,6 +66,15 @@ simde_int32x4_t
simde_vaddl_high_s16(simde_int16x8_t a, simde_int16x8_t b) { simde_vaddl_high_s16(simde_int16x8_t a, simde_int16x8_t b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddl_high_s16(a, b); return vaddl_high_s16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int16x8_private a_ = simde_int16x8_to_private(a);
simde_int16x8_private b_ = simde_int16x8_to_private(b);
a_.sv128 = __riscv_vslidedown_vx_i16m1(a_.sv128 , 4 , 8);
b_.sv128 = __riscv_vslidedown_vx_i16m1(b_.sv128 , 4 , 8);
r_.sv128 = __riscv_vwadd_vv_i32m1(__riscv_vlmul_trunc_v_i16m1_i16mf2(a_.sv128) , __riscv_vlmul_trunc_v_i16m1_i16mf2(b_.sv128) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vaddq_s32(simde_vmovl_high_s16(a), simde_vmovl_high_s16(b)); return simde_vaddq_s32(simde_vmovl_high_s16(a), simde_vmovl_high_s16(b));
#endif #endif
...@@ -70,6 +89,15 @@ simde_int64x2_t ...@@ -70,6 +89,15 @@ simde_int64x2_t
simde_vaddl_high_s32(simde_int32x4_t a, simde_int32x4_t b) { simde_vaddl_high_s32(simde_int32x4_t a, simde_int32x4_t b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddl_high_s32(a, b); return vaddl_high_s32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int32x4_private b_ = simde_int32x4_to_private(b);
a_.sv128 = __riscv_vslidedown_vx_i32m1(a_.sv128 , 2, 4);
b_.sv128 = __riscv_vslidedown_vx_i32m1(b_.sv128 , 2, 4);
r_.sv128 = __riscv_vwadd_vv_i64m1(__riscv_vlmul_trunc_v_i32m1_i32mf2(a_.sv128) , __riscv_vlmul_trunc_v_i32m1_i32mf2(b_.sv128) , 2);
return simde_int64x2_from_private(r_);
#else #else
return simde_vaddq_s64(simde_vmovl_high_s32(a), simde_vmovl_high_s32(b)); return simde_vaddq_s64(simde_vmovl_high_s32(a), simde_vmovl_high_s32(b));
#endif #endif
...@@ -84,6 +112,15 @@ simde_uint16x8_t ...@@ -84,6 +112,15 @@ simde_uint16x8_t
simde_vaddl_high_u8(simde_uint8x16_t a, simde_uint8x16_t b) { simde_vaddl_high_u8(simde_uint8x16_t a, simde_uint8x16_t b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddl_high_u8(a, b); return vaddl_high_u8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private r_;
simde_uint8x16_private a_ = simde_uint8x16_to_private(a);
simde_uint8x16_private b_ = simde_uint8x16_to_private(b);
a_.sv128 = __riscv_vslidedown_vx_u8m1(a_.sv128 , 8 , 16);
b_.sv128 = __riscv_vslidedown_vx_u8m1(b_.sv128 , 8 , 16);
r_.sv128 = __riscv_vwaddu_vv_u16m1(__riscv_vlmul_trunc_v_u8m1_u8mf2 (a_.sv128) , __riscv_vlmul_trunc_v_u8m1_u8mf2 (b_.sv128) , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vaddq_u16(simde_vmovl_high_u8(a), simde_vmovl_high_u8(b)); return simde_vaddq_u16(simde_vmovl_high_u8(a), simde_vmovl_high_u8(b));
#endif #endif
...@@ -98,6 +135,15 @@ simde_uint32x4_t ...@@ -98,6 +135,15 @@ simde_uint32x4_t
simde_vaddl_high_u16(simde_uint16x8_t a, simde_uint16x8_t b) { simde_vaddl_high_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddl_high_u16(a, b); return vaddl_high_u16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
simde_uint16x8_private b_ = simde_uint16x8_to_private(b);
a_.sv128 = __riscv_vslidedown_vx_u16m1(a_.sv128 , 4 , 8);
b_.sv128 = __riscv_vslidedown_vx_u16m1(b_.sv128 , 4 , 8);
r_.sv128 = __riscv_vwaddu_vv_u32m1(__riscv_vlmul_trunc_v_u16m1_u16mf2 (a_.sv128) , __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv128) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vaddq_u32(simde_vmovl_high_u16(a), simde_vmovl_high_u16(b)); return simde_vaddq_u32(simde_vmovl_high_u16(a), simde_vmovl_high_u16(b));
#endif #endif
...@@ -112,6 +158,15 @@ simde_uint64x2_t ...@@ -112,6 +158,15 @@ simde_uint64x2_t
simde_vaddl_high_u32(simde_uint32x4_t a, simde_uint32x4_t b) { simde_vaddl_high_u32(simde_uint32x4_t a, simde_uint32x4_t b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddl_high_u32(a, b); return vaddl_high_u32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint32x4_private b_ = simde_uint32x4_to_private(b);
a_.sv128 = __riscv_vslidedown_vx_u32m1(a_.sv128 , 2, 4);
b_.sv128 = __riscv_vslidedown_vx_u32m1(b_.sv128 , 2, 4);
r_.sv128 = __riscv_vwaddu_vv_u64m1(__riscv_vlmul_trunc_v_u32m1_u32mf2 (a_.sv128) , __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv128) , 2);
return simde_uint64x2_from_private(r_);
#else #else
return simde_vaddq_u64(simde_vmovl_high_u32(a), simde_vmovl_high_u32(b)); return simde_vaddq_u64(simde_vmovl_high_u32(a), simde_vmovl_high_u32(b));
#endif #endif
......
arm/neon/addlv.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_ADDLV_H) #if !defined(SIMDE_ARM_NEON_ADDLV_H)
...@@ -40,16 +41,22 @@ int16_t ...@@ -40,16 +41,22 @@ int16_t
simde_vaddlv_s8(simde_int8x8_t a) { simde_vaddlv_s8(simde_int8x8_t a) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddlv_s8(a); return vaddlv_s8(a);
#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddvq_s16(simde_vmovl_s8(a)); return simde_vaddvq_s16(simde_vmovl_s8(a));
#else #else
simde_int8x8_private a_ = simde_int8x8_to_private(a); simde_int8x8_private a_ = simde_int8x8_to_private(a);
int16_t r = 0; int16_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vint16m1_t zero = __riscv_vmv_v_x_i16m1(0 , 1);
vint16m1_t sum = __riscv_vwredsum_vs_i8m1_i16m1(a_.sv64 , zero , 8);
r = __riscv_vmv_x_s_i16m1_i16 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -64,16 +71,22 @@ int32_t ...@@ -64,16 +71,22 @@ int32_t
simde_vaddlv_s16(simde_int16x4_t a) { simde_vaddlv_s16(simde_int16x4_t a) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddlv_s16(a); return vaddlv_s16(a);
#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddvq_s32(simde_vmovl_s16(a)); return simde_vaddvq_s32(simde_vmovl_s16(a));
#else #else
simde_int16x4_private a_ = simde_int16x4_to_private(a); simde_int16x4_private a_ = simde_int16x4_to_private(a);
int32_t r = 0; int32_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vint32m1_t zero = __riscv_vmv_v_x_i32m1(0 , 1);
vint32m1_t sum = __riscv_vwredsum_vs_i16m1_i32m1(a_.sv64 , zero , 4);
r = __riscv_vmv_x_s_i32m1_i32 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -88,16 +101,22 @@ int64_t ...@@ -88,16 +101,22 @@ int64_t
simde_vaddlv_s32(simde_int32x2_t a) { simde_vaddlv_s32(simde_int32x2_t a) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddlv_s32(a); return vaddlv_s32(a);
#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddvq_s64(simde_vmovl_s32(a)); return simde_vaddvq_s64(simde_vmovl_s32(a));
#else #else
simde_int32x2_private a_ = simde_int32x2_to_private(a); simde_int32x2_private a_ = simde_int32x2_to_private(a);
int64_t r = 0; int64_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vint64m1_t zero = __riscv_vmv_v_x_i64m1(0 , 1);
vint64m1_t sum = __riscv_vwredsum_vs_i32m1_i64m1(a_.sv64 , zero , 2);
r = __riscv_vmv_x_s_i64m1_i64 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -112,16 +131,22 @@ uint16_t ...@@ -112,16 +131,22 @@ uint16_t
simde_vaddlv_u8(simde_uint8x8_t a) { simde_vaddlv_u8(simde_uint8x8_t a) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddlv_u8(a); return vaddlv_u8(a);
#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddvq_u16(simde_vmovl_u8(a)); return simde_vaddvq_u16(simde_vmovl_u8(a));
#else #else
simde_uint8x8_private a_ = simde_uint8x8_to_private(a); simde_uint8x8_private a_ = simde_uint8x8_to_private(a);
uint16_t r = 0; uint16_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vuint16m1_t zero = __riscv_vmv_v_x_u16m1(0 , 1);
vuint16m1_t sum = __riscv_vwredsumu_vs_u8m1_u16m1(a_.sv64 , zero , 8);
r = __riscv_vmv_x_s_u16m1_u16 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -136,16 +161,22 @@ uint32_t ...@@ -136,16 +161,22 @@ uint32_t
simde_vaddlv_u16(simde_uint16x4_t a) { simde_vaddlv_u16(simde_uint16x4_t a) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddlv_u16(a); return vaddlv_u16(a);
#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddvq_u32(simde_vmovl_u16(a)); return simde_vaddvq_u32(simde_vmovl_u16(a));
#else #else
simde_uint16x4_private a_ = simde_uint16x4_to_private(a); simde_uint16x4_private a_ = simde_uint16x4_to_private(a);
uint32_t r = 0; uint32_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vuint32m1_t zero = __riscv_vmv_v_x_u32m1(0 , 1);
vuint32m1_t sum = __riscv_vwredsumu_vs_u16m1_u32m1(a_.sv64 , zero , 4);
r = __riscv_vmv_x_s_u32m1_u32 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -160,16 +191,22 @@ uint64_t ...@@ -160,16 +191,22 @@ uint64_t
simde_vaddlv_u32(simde_uint32x2_t a) { simde_vaddlv_u32(simde_uint32x2_t a) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vaddlv_u32(a); return vaddlv_u32(a);
#elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_GE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddvq_u64(simde_vmovl_u32(a)); return simde_vaddvq_u64(simde_vmovl_u32(a));
#else #else
simde_uint32x2_private a_ = simde_uint32x2_to_private(a); simde_uint32x2_private a_ = simde_uint32x2_to_private(a);
uint64_t r = 0; uint64_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vuint64m1_t zero = __riscv_vmv_v_x_u64m1(0 , 1);
vuint64m1_t sum = __riscv_vwredsumu_vs_u32m1_u64m1(a_.sv64 , zero , 2);
r = __riscv_vmv_x_s_u64m1_u64 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -194,10 +231,16 @@ simde_vaddlvq_s8(simde_int8x16_t a) { ...@@ -194,10 +231,16 @@ simde_vaddlvq_s8(simde_int8x16_t a) {
simde_int8x16_private a_ = simde_int8x16_to_private(a); simde_int8x16_private a_ = simde_int8x16_to_private(a);
int16_t r = 0; int16_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vint16m1_t zero = __riscv_vmv_v_x_i16m1(0 , 1);
vint16m1_t sum = __riscv_vwredsum_vs_i8m1_i16m1(a_.sv128 , zero , 16);
r = __riscv_vmv_x_s_i16m1_i16 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -223,10 +266,16 @@ simde_vaddlvq_s16(simde_int16x8_t a) { ...@@ -223,10 +266,16 @@ simde_vaddlvq_s16(simde_int16x8_t a) {
simde_int16x8_private a_ = simde_int16x8_to_private(a); simde_int16x8_private a_ = simde_int16x8_to_private(a);
int32_t r = 0; int32_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vint32m1_t zero = __riscv_vmv_v_x_i32m1(0 , 1);
vint32m1_t sum = __riscv_vwredsum_vs_i16m1_i32m1(a_.sv128 , zero , 8);
r = __riscv_vmv_x_s_i32m1_i32 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -245,10 +294,16 @@ simde_vaddlvq_s32(simde_int32x4_t a) { ...@@ -245,10 +294,16 @@ simde_vaddlvq_s32(simde_int32x4_t a) {
simde_int32x4_private a_ = simde_int32x4_to_private(a); simde_int32x4_private a_ = simde_int32x4_to_private(a);
int64_t r = 0; int64_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vint64m1_t zero = __riscv_vmv_v_x_i64m1(0 , 1);
vint64m1_t sum = __riscv_vwredsum_vs_i32m1_i64m1(a_.sv128 , zero , 4);
r = __riscv_vmv_x_s_i64m1_i64 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -272,10 +327,16 @@ simde_vaddlvq_u8(simde_uint8x16_t a) { ...@@ -272,10 +327,16 @@ simde_vaddlvq_u8(simde_uint8x16_t a) {
simde_uint8x16_private a_ = simde_uint8x16_to_private(a); simde_uint8x16_private a_ = simde_uint8x16_to_private(a);
uint16_t r = 0; uint16_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vuint16m1_t zero = __riscv_vmv_v_x_u16m1(0 , 1);
vuint16m1_t sum = __riscv_vwredsumu_vs_u8m1_u16m1(a_.sv128 , zero , 16);
r = __riscv_vmv_x_s_u16m1_u16 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
...@@ -298,14 +359,20 @@ simde_vaddlvq_u16(simde_uint16x8_t a) { ...@@ -298,14 +359,20 @@ simde_vaddlvq_u16(simde_uint16x8_t a) {
return HEDLEY_STATIC_CAST(uint32_t, _mm_cvtsi128_si32(a_)); return HEDLEY_STATIC_CAST(uint32_t, _mm_cvtsi128_si32(a_));
#else #else
simde_uint16x8_private a_ = simde_uint16x8_to_private(a); simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
uint32_t r = 0;
uint32_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vuint32m1_t zero = __riscv_vmv_v_x_u32m1(0 , 1);
vuint32m1_t sum = __riscv_vwredsumu_vs_u16m1_u32m1(a_.sv128 , zero , 8);
r = __riscv_vmv_x_s_u32m1_u32 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
} }
#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES) #if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
...@@ -322,10 +389,16 @@ simde_vaddlvq_u32(simde_uint32x4_t a) { ...@@ -322,10 +389,16 @@ simde_vaddlvq_u32(simde_uint32x4_t a) {
simde_uint32x4_private a_ = simde_uint32x4_to_private(a); simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
uint64_t r = 0; uint64_t r = 0;
#if defined(SIMDE_RISCV_V_NATIVE)
vuint64m1_t zero = __riscv_vmv_v_x_u64m1(0 , 1);
vuint64m1_t sum = __riscv_vwredsumu_vs_u32m1_u64m1(a_.sv128 , zero , 4);
r = __riscv_vmv_x_s_u64m1_u64 (sum);
#else
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif
return r; return r;
#endif #endif
......
arm/neon/addv.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_ADDV_H) #if !defined(SIMDE_ARM_NEON_ADDV_H)
...@@ -43,12 +44,18 @@ simde_vaddv_f32(simde_float32x2_t a) { ...@@ -43,12 +44,18 @@ simde_vaddv_f32(simde_float32x2_t a) {
#else #else
simde_float32x2_private a_ = simde_float32x2_to_private(a); simde_float32x2_private a_ = simde_float32x2_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vfloat32m1_t zero = __riscv_vfmv_v_f_f32m1(0 , 1);
vfloat32m1_t sum = __riscv_vfredosum_vs_f32m1_f32m1(a_.sv64 , zero , 2);
r = __riscv_vfmv_f_s_f32m1_f32 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -67,12 +74,18 @@ simde_vaddv_s8(simde_int8x8_t a) { ...@@ -67,12 +74,18 @@ simde_vaddv_s8(simde_int8x8_t a) {
#else #else
simde_int8x8_private a_ = simde_int8x8_to_private(a); simde_int8x8_private a_ = simde_int8x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vint8m1_t zero = __riscv_vmv_v_x_i8m1(0 , 1);
vint8m1_t sum = __riscv_vredsum_vs_i8m1_i8m1(a_.sv64 , zero , 8);
r = __riscv_vmv_x_s_i8m1_i8 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -91,12 +104,18 @@ simde_vaddv_s16(simde_int16x4_t a) { ...@@ -91,12 +104,18 @@ simde_vaddv_s16(simde_int16x4_t a) {
#else #else
simde_int16x4_private a_ = simde_int16x4_to_private(a); simde_int16x4_private a_ = simde_int16x4_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vint16m1_t zero = __riscv_vmv_v_x_i16m1(0 , 1);
vint16m1_t sum = __riscv_vredsum_vs_i16m1_i16m1(a_.sv64 , zero , 4);
r = __riscv_vmv_x_s_i16m1_i16 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -115,12 +134,18 @@ simde_vaddv_s32(simde_int32x2_t a) { ...@@ -115,12 +134,18 @@ simde_vaddv_s32(simde_int32x2_t a) {
#else #else
simde_int32x2_private a_ = simde_int32x2_to_private(a); simde_int32x2_private a_ = simde_int32x2_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vint32m1_t zero = __riscv_vmv_v_x_i32m1(0 , 1);
vint32m1_t sum = __riscv_vredsum_vs_i32m1_i32m1(a_.sv64 , zero , 2);
r = __riscv_vmv_x_s_i32m1_i32 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -139,12 +164,18 @@ simde_vaddv_u8(simde_uint8x8_t a) { ...@@ -139,12 +164,18 @@ simde_vaddv_u8(simde_uint8x8_t a) {
#else #else
simde_uint8x8_private a_ = simde_uint8x8_to_private(a); simde_uint8x8_private a_ = simde_uint8x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint8m1_t zero = __riscv_vmv_v_x_u8m1(0 , 1);
vuint8m1_t sum = __riscv_vredsum_vs_u8m1_u8m1(a_.sv64 , zero , 8);
r = __riscv_vmv_x_s_u8m1_u8 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -163,12 +194,18 @@ simde_vaddv_u16(simde_uint16x4_t a) { ...@@ -163,12 +194,18 @@ simde_vaddv_u16(simde_uint16x4_t a) {
#else #else
simde_uint16x4_private a_ = simde_uint16x4_to_private(a); simde_uint16x4_private a_ = simde_uint16x4_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint16m1_t zero = __riscv_vmv_v_x_u16m1(0 , 1);
vuint16m1_t sum = __riscv_vredsum_vs_u16m1_u16m1(a_.sv64 , zero , 4);
r = __riscv_vmv_x_s_u16m1_u16(sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -187,12 +224,18 @@ simde_vaddv_u32(simde_uint32x2_t a) { ...@@ -187,12 +224,18 @@ simde_vaddv_u32(simde_uint32x2_t a) {
#else #else
simde_uint32x2_private a_ = simde_uint32x2_to_private(a); simde_uint32x2_private a_ = simde_uint32x2_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint32m1_t zero = __riscv_vmv_v_x_u32m1(0 , 1);
vuint32m1_t sum = __riscv_vredsum_vs_u32m1_u32m1(a_.sv64 , zero , 2);
r = __riscv_vmv_x_s_u32m1_u32 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -211,12 +254,18 @@ simde_vaddvq_f32(simde_float32x4_t a) { ...@@ -211,12 +254,18 @@ simde_vaddvq_f32(simde_float32x4_t a) {
#else #else
simde_float32x4_private a_ = simde_float32x4_to_private(a); simde_float32x4_private a_ = simde_float32x4_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vfloat32m1_t zero = __riscv_vfmv_v_f_f32m1(0 , 1);
vfloat32m1_t sum = __riscv_vfredosum_vs_f32m1_f32m1(a_.sv128 , zero , 4);
r = __riscv_vfmv_f_s_f32m1_f32 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -235,12 +284,18 @@ simde_vaddvq_f64(simde_float64x2_t a) { ...@@ -235,12 +284,18 @@ simde_vaddvq_f64(simde_float64x2_t a) {
#else #else
simde_float64x2_private a_ = simde_float64x2_to_private(a); simde_float64x2_private a_ = simde_float64x2_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vfloat64m1_t zero = __riscv_vfmv_v_f_f64m1(0 , 1);
vfloat64m1_t sum = __riscv_vfredosum_vs_f64m1_f64m1(a_.sv128 , zero , 2);
r = __riscv_vfmv_f_s_f64m1_f64 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -259,12 +314,18 @@ simde_vaddvq_s8(simde_int8x16_t a) { ...@@ -259,12 +314,18 @@ simde_vaddvq_s8(simde_int8x16_t a) {
#else #else
simde_int8x16_private a_ = simde_int8x16_to_private(a); simde_int8x16_private a_ = simde_int8x16_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vint8m1_t zero = __riscv_vmv_v_x_i8m1(0 , 1);
vint8m1_t sum = __riscv_vredsum_vs_i8m1_i8m1(a_.sv128 , zero , 16);
r = __riscv_vmv_x_s_i8m1_i8 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -283,12 +344,18 @@ simde_vaddvq_s16(simde_int16x8_t a) { ...@@ -283,12 +344,18 @@ simde_vaddvq_s16(simde_int16x8_t a) {
#else #else
simde_int16x8_private a_ = simde_int16x8_to_private(a); simde_int16x8_private a_ = simde_int16x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vint16m1_t zero = __riscv_vmv_v_x_i16m1(0 , 1);
vint16m1_t sum = __riscv_vredsum_vs_i16m1_i16m1(a_.sv128 , zero , 8);
r = __riscv_vmv_x_s_i16m1_i16 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -307,12 +374,18 @@ simde_vaddvq_s32(simde_int32x4_t a) { ...@@ -307,12 +374,18 @@ simde_vaddvq_s32(simde_int32x4_t a) {
#else #else
simde_int32x4_private a_ = simde_int32x4_to_private(a); simde_int32x4_private a_ = simde_int32x4_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vint32m1_t zero = __riscv_vmv_v_x_i32m1(0 , 1);
vint32m1_t sum = __riscv_vredsum_vs_i32m1_i32m1(a_.sv128 , zero , 4);
r = __riscv_vmv_x_s_i32m1_i32 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -331,12 +404,18 @@ simde_vaddvq_s64(simde_int64x2_t a) { ...@@ -331,12 +404,18 @@ simde_vaddvq_s64(simde_int64x2_t a) {
#else #else
simde_int64x2_private a_ = simde_int64x2_to_private(a); simde_int64x2_private a_ = simde_int64x2_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vint64m1_t zero = __riscv_vmv_v_x_i64m1(0 , 1);
vint64m1_t sum = __riscv_vredsum_vs_i64m1_i64m1(a_.sv128 , zero , 2);
r = __riscv_vmv_x_s_i64m1_i64 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -360,12 +439,18 @@ simde_vaddvq_u8(simde_uint8x16_t a) { ...@@ -360,12 +439,18 @@ simde_vaddvq_u8(simde_uint8x16_t a) {
#else #else
simde_uint8x16_private a_ = simde_uint8x16_to_private(a); simde_uint8x16_private a_ = simde_uint8x16_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint8m1_t zero = __riscv_vmv_v_x_u8m1(0 , 1);
vuint8m1_t sum = __riscv_vredsum_vs_u8m1_u8m1(a_.sv128 , zero , 16);
r = __riscv_vmv_x_s_u8m1_u8 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -384,12 +469,18 @@ simde_vaddvq_u16(simde_uint16x8_t a) { ...@@ -384,12 +469,18 @@ simde_vaddvq_u16(simde_uint16x8_t a) {
#else #else
simde_uint16x8_private a_ = simde_uint16x8_to_private(a); simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint16m1_t zero = __riscv_vmv_v_x_u16m1(0 , 1);
vuint16m1_t sum = __riscv_vredsum_vs_u16m1_u16m1(a_.sv128 , zero , 8);
r = __riscv_vmv_x_s_u16m1_u16(sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -408,12 +499,18 @@ simde_vaddvq_u32(simde_uint32x4_t a) { ...@@ -408,12 +499,18 @@ simde_vaddvq_u32(simde_uint32x4_t a) {
#else #else
simde_uint32x4_private a_ = simde_uint32x4_to_private(a); simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint32m1_t zero = __riscv_vmv_v_x_u32m1(0 , 1);
vuint32m1_t sum = __riscv_vredsum_vs_u32m1_u32m1(a_.sv128 , zero , 4);
r = __riscv_vmv_x_s_u32m1_u32 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
...@@ -432,12 +529,18 @@ simde_vaddvq_u64(simde_uint64x2_t a) { ...@@ -432,12 +529,18 @@ simde_vaddvq_u64(simde_uint64x2_t a) {
#else #else
simde_uint64x2_private a_ = simde_uint64x2_to_private(a); simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint64m1_t zero = __riscv_vmv_v_x_u64m1(0 , 1);
vuint64m1_t sum = __riscv_vredsum_vs_u64m1_u64m1(a_.sv128 , zero , 2);
r = __riscv_vmv_x_s_u64m1_u64 (sum);
#else
r = 0; r = 0;
SIMDE_VECTORIZE_REDUCTION(+:r) SIMDE_VECTORIZE_REDUCTION(+:r)
for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(a_.values) / sizeof(a_.values[0])) ; i++) {
r += a_.values[i]; r += a_.values[i];
} }
#endif #endif
#endif
return r; return r;
} }
......
arm/neon/cge.h
View file @ 408d06a3
This diff is collapsed.
arm/neon/cgt.h
View file @ 408d06a3
This diff is collapsed.
arm/neon/cle.h
View file @ 408d06a3
This diff is collapsed.
arm/neon/clez.h
View file @ 408d06a3
This diff is collapsed.
arm/neon/clt.h
View file @ 408d06a3
This diff is collapsed.
arm/neon/cnt.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_CNT_H) #if !defined(SIMDE_ARM_NEON_CNT_H)
...@@ -55,10 +56,24 @@ simde_vcnt_s8(simde_int8x8_t a) { ...@@ -55,10 +56,24 @@ simde_vcnt_s8(simde_int8x8_t a) {
r_, r_,
a_ = simde_int8x8_to_private(a); a_ = simde_int8x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE)
vuint8m1_t p = __riscv_vreinterpret_v_i8m1_u8m1(a_.sv64);
vuint8m1_t tmp = __riscv_vand_vv_u8m1(__riscv_vsrl_vx_u8m1(p , 1 , 8) , __riscv_vmv_v_x_u8m1(0x55 , 8) , 8);
p = __riscv_vsub_vv_u8m1(p , tmp , 8);
tmp = p;
p = __riscv_vand_vv_u8m1(p , __riscv_vmv_v_x_u8m1(0x33 , 8) , 8);
tmp = __riscv_vand_vv_u8m1(__riscv_vsrl_vx_u8m1(tmp , 2 , 8) , __riscv_vmv_v_x_u8m1(0x33 , 8) , 8);
p = __riscv_vadd_vv_u8m1(p , tmp , 8);
tmp = __riscv_vsrl_vx_u8m1(p, 4 , 8);
p = __riscv_vadd_vv_u8m1(p , tmp , 8);
p = __riscv_vand_vv_u8m1(p , __riscv_vmv_v_x_u8m1(0xf , 8) , 8);
r_.sv64 = __riscv_vreinterpret_v_u8m1_i8m1(p);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = HEDLEY_STATIC_CAST(int8_t, simde_x_arm_neon_cntb(HEDLEY_STATIC_CAST(uint8_t, a_.values[i]))); r_.values[i] = HEDLEY_STATIC_CAST(int8_t, simde_x_arm_neon_cntb(HEDLEY_STATIC_CAST(uint8_t, a_.values[i])));
} }
#endif
return simde_int8x8_from_private(r_); return simde_int8x8_from_private(r_);
#endif #endif
...@@ -140,6 +155,16 @@ simde_vcntq_s8(simde_int8x16_t a) { ...@@ -140,6 +155,16 @@ simde_vcntq_s8(simde_int8x16_t a) {
tmp = _mm_srli_epi16(a_.m128i, 4); tmp = _mm_srli_epi16(a_.m128i, 4);
a_.m128i = _mm_add_epi8(a_.m128i, tmp); a_.m128i = _mm_add_epi8(a_.m128i, tmp);
r_.m128i = _mm_and_si128(a_.m128i, _mm_set1_epi8(0x0f)); r_.m128i = _mm_and_si128(a_.m128i, _mm_set1_epi8(0x0f));
#elif defined(SIMDE_RISCV_V_NATIVE)
vint8m1_t tmp = __riscv_vand_vv_i8m1(__riscv_vsra_vx_i8m1(a_.sv128 , 1 , 16) , __riscv_vmv_v_x_i8m1(0x55 , 16) , 16);
a_.sv128 = __riscv_vsub_vv_i8m1(a_.sv128 , tmp , 16);
tmp = a_.sv128;
a_.sv128 = __riscv_vand_vv_i8m1(a_.sv128 , __riscv_vmv_v_x_i8m1(0x33 , 16) , 16);
tmp = __riscv_vand_vv_i8m1(__riscv_vsra_vx_i8m1(tmp , 2 , 16) , __riscv_vmv_v_x_i8m1(0x33 , 16) , 16);
a_.sv128 = __riscv_vadd_vv_i8m1(a_.sv128 , tmp , 16);
tmp = __riscv_vsra_vx_i8m1(a_.sv128, 4 , 16);
a_.sv128 = __riscv_vadd_vv_i8m1(a_.sv128 , tmp , 16);
r_.sv128 = __riscv_vand_vv_i8m1(a_.sv128 , __riscv_vmv_v_x_i8m1(0xf , 16) , 16);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
......
arm/neon/fma.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2021 Atharva Nimbalkar <atharvakn@gmail.com> * 2021 Atharva Nimbalkar <atharvakn@gmail.com>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_FMA_H) #if !defined(SIMDE_ARM_NEON_FMA_H)
...@@ -54,6 +55,15 @@ simde_float32x2_t ...@@ -54,6 +55,15 @@ simde_float32x2_t
simde_vfma_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) { simde_vfma_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
return vfma_f32(a, b, c); return vfma_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x2_private
r_,
a_ = simde_float32x2_to_private(a),
b_ = simde_float32x2_to_private(b),
c_ = simde_float32x2_to_private(c);
r_.sv64 = __riscv_vfmacc_vv_f32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_float32x2_from_private(r_);
#else #else
return simde_vadd_f32(a, simde_vmul_f32(b, c)); return simde_vadd_f32(a, simde_vmul_f32(b, c));
#endif #endif
...@@ -68,6 +78,15 @@ simde_float64x1_t ...@@ -68,6 +78,15 @@ simde_float64x1_t
simde_vfma_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) { simde_vfma_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
return vfma_f64(a, b, c); return vfma_f64(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float64x1_private
r_,
a_ = simde_float64x1_to_private(a),
b_ = simde_float64x1_to_private(b),
c_ = simde_float64x1_to_private(c);
r_.sv64 = __riscv_vfmacc_vv_f64m1(a_.sv64 , b_.sv64 , c_.sv64 , 1);
return simde_float64x1_from_private(r_);
#else #else
return simde_vadd_f64(a, simde_vmul_f64(b, c)); return simde_vadd_f64(a, simde_vmul_f64(b, c));
#endif #endif
...@@ -82,6 +101,15 @@ simde_float16x4_t ...@@ -82,6 +101,15 @@ simde_float16x4_t
simde_vfma_f16(simde_float16x4_t a, simde_float16x4_t b, simde_float16x4_t c) { simde_vfma_f16(simde_float16x4_t a, simde_float16x4_t b, simde_float16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16) #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16)
return vfma_f16(a, b, c); return vfma_f16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
simde_float16x4_private
r_,
a_ = simde_float16x4_to_private(a),
b_ = simde_float16x4_to_private(b),
c_ = simde_float16x4_to_private(c);
r_.sv64 = __riscv_vfmacc_vv_f16m1(a_.sv64 , b_.sv64 , c_.sv64 , 4);
return simde_float16x4_from_private(r_);
#else #else
return simde_vadd_f16(a, simde_vmul_f16(b, c)); return simde_vadd_f16(a, simde_vmul_f16(b, c));
#endif #endif
...@@ -96,6 +124,15 @@ simde_float16x8_t ...@@ -96,6 +124,15 @@ simde_float16x8_t
simde_vfmaq_f16(simde_float16x8_t a, simde_float16x8_t b, simde_float16x8_t c) { simde_vfmaq_f16(simde_float16x8_t a, simde_float16x8_t b, simde_float16x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16) #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16)
return vfmaq_f16(a, b, c); return vfmaq_f16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
simde_float16x8_private
r_,
a_ = simde_float16x8_to_private(a),
b_ = simde_float16x8_to_private(b),
c_ = simde_float16x8_to_private(c);
r_.sv128 = __riscv_vfmacc_vv_f16m1(a_.sv128 , b_.sv128 , c_.sv128 , 8);
return simde_float16x8_from_private(r_);
#else #else
return simde_vaddq_f16(a, simde_vmulq_f16(b, c)); return simde_vaddq_f16(a, simde_vmulq_f16(b, c));
#endif #endif
...@@ -113,7 +150,7 @@ simde_vfmaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) { ...@@ -113,7 +150,7 @@ simde_vfmaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) {
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) #elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
return vec_madd(b, c, a); return vec_madd(b, c, a);
#elif \ #elif \
defined(SIMDE_X86_FMA_NATIVE) defined(SIMDE_X86_FMA_NATIVE) || defined(SIMDE_RISCV_V_NATIVE)
simde_float32x4_private simde_float32x4_private
r_, r_,
a_ = simde_float32x4_to_private(a), a_ = simde_float32x4_to_private(a),
...@@ -122,6 +159,8 @@ simde_vfmaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) { ...@@ -122,6 +159,8 @@ simde_vfmaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) {
#if defined(SIMDE_X86_FMA_NATIVE) #if defined(SIMDE_X86_FMA_NATIVE)
r_.m128 = _mm_fmadd_ps(b_.m128, c_.m128, a_.m128); r_.m128 = _mm_fmadd_ps(b_.m128, c_.m128, a_.m128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfmacc_vv_f32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
#endif #endif
return simde_float32x4_from_private(r_); return simde_float32x4_from_private(r_);
...@@ -142,7 +181,7 @@ simde_vfmaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) { ...@@ -142,7 +181,7 @@ simde_vfmaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) {
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE) #elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
return vec_madd(b, c, a); return vec_madd(b, c, a);
#elif \ #elif \
defined(SIMDE_X86_FMA_NATIVE) defined(SIMDE_X86_FMA_NATIVE) || defined(SIMDE_RISCV_V_NATIVE)
simde_float64x2_private simde_float64x2_private
r_, r_,
a_ = simde_float64x2_to_private(a), a_ = simde_float64x2_to_private(a),
...@@ -151,6 +190,8 @@ simde_vfmaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) { ...@@ -151,6 +190,8 @@ simde_vfmaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) {
#if defined(SIMDE_X86_FMA_NATIVE) #if defined(SIMDE_X86_FMA_NATIVE)
r_.m128d = _mm_fmadd_pd(b_.m128d, c_.m128d, a_.m128d); r_.m128d = _mm_fmadd_pd(b_.m128d, c_.m128d, a_.m128d);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfmacc_vv_f64m1(a_.sv128 , b_.sv128 , c_.sv128 , 2);
#endif #endif
return simde_float64x2_from_private(r_); return simde_float64x2_from_private(r_);
......
arm/neon/fms.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_FMS_H) #if !defined(SIMDE_ARM_NEON_FMS_H)
...@@ -54,6 +55,14 @@ simde_float32x2_t ...@@ -54,6 +55,14 @@ simde_float32x2_t
simde_vfms_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) { simde_vfms_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
return vfms_f32(a, b, c); return vfms_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x2_private
r_,
a_ = simde_float32x2_to_private(a),
b_ = simde_float32x2_to_private(b),
c_ = simde_float32x2_to_private(c);
r_.sv64 = __riscv_vfnmsac_vv_f32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_float32x2_from_private(r_);
#else #else
return simde_vadd_f32(a, simde_vneg_f32(simde_vmul_f32(b, c))); return simde_vadd_f32(a, simde_vneg_f32(simde_vmul_f32(b, c)));
#endif #endif
...@@ -68,6 +77,14 @@ simde_float64x1_t ...@@ -68,6 +77,14 @@ simde_float64x1_t
simde_vfms_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) { simde_vfms_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
return vfms_f64(a, b, c); return vfms_f64(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float64x1_private
r_,
a_ = simde_float64x1_to_private(a),
b_ = simde_float64x1_to_private(b),
c_ = simde_float64x1_to_private(c);
r_.sv64 = __riscv_vfnmsac_vv_f64m1(a_.sv64 , b_.sv64 , c_.sv64 , 1);
return simde_float64x1_from_private(r_);
#else #else
return simde_vadd_f64(a, simde_vneg_f64(simde_vmul_f64(b, c))); return simde_vadd_f64(a, simde_vneg_f64(simde_vmul_f64(b, c)));
#endif #endif
...@@ -82,6 +99,14 @@ simde_float16x4_t ...@@ -82,6 +99,14 @@ simde_float16x4_t
simde_vfms_f16(simde_float16x4_t a, simde_float16x4_t b, simde_float16x4_t c) { simde_vfms_f16(simde_float16x4_t a, simde_float16x4_t b, simde_float16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16) #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16)
return vfms_f16(a, b, c); return vfms_f16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
simde_float16x4_private
r_,
a_ = simde_float16x4_to_private(a),
b_ = simde_float16x4_to_private(b),
c_ = simde_float16x4_to_private(c);
r_.sv64 = __riscv_vfnmsac_vv_f16m1(a_.sv64 , b_.sv64 , c_.sv64 , 4);
return simde_float16x4_from_private(r_);
#else #else
return simde_vadd_f16(a, simde_vneg_f16(simde_vmul_f16(b, c))); return simde_vadd_f16(a, simde_vneg_f16(simde_vmul_f16(b, c)));
#endif #endif
...@@ -96,6 +121,14 @@ simde_float16x8_t ...@@ -96,6 +121,14 @@ simde_float16x8_t
simde_vfmsq_f16(simde_float16x8_t a, simde_float16x8_t b, simde_float16x8_t c) { simde_vfmsq_f16(simde_float16x8_t a, simde_float16x8_t b, simde_float16x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16) #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && defined(SIMDE_ARM_NEON_FP16)
return vfmsq_f16(a, b, c); return vfmsq_f16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
simde_float16x8_private
r_,
a_ = simde_float16x8_to_private(a),
b_ = simde_float16x8_to_private(b),
c_ = simde_float16x8_to_private(c);
r_.sv128 = __riscv_vfnmsac_vv_f16m1(a_.sv128 , b_.sv128 , c_.sv128 , 8);
return simde_float16x8_from_private(r_);
#else #else
return simde_vaddq_f16(a, simde_vnegq_f16(simde_vmulq_f16(b, c))); return simde_vaddq_f16(a, simde_vnegq_f16(simde_vmulq_f16(b, c)));
#endif #endif
...@@ -110,6 +143,14 @@ simde_float32x4_t ...@@ -110,6 +143,14 @@ simde_float32x4_t
simde_vfmsq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) { simde_vfmsq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
return vfmsq_f32(a, b, c); return vfmsq_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x4_private
r_,
a_ = simde_float32x4_to_private(a),
b_ = simde_float32x4_to_private(b),
c_ = simde_float32x4_to_private(c);
r_.sv128 = __riscv_vfnmsac_vv_f32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
return simde_float32x4_from_private(r_);
#else #else
return simde_vaddq_f32(a, simde_vnegq_f32(simde_vmulq_f32(b, c))); return simde_vaddq_f32(a, simde_vnegq_f32(simde_vmulq_f32(b, c)));
#endif #endif
...@@ -124,6 +165,14 @@ simde_float64x2_t ...@@ -124,6 +165,14 @@ simde_float64x2_t
simde_vfmsq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) { simde_vfmsq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
return vfmsq_f64(a, b, c); return vfmsq_f64(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float64x2_private
r_,
a_ = simde_float64x2_to_private(a),
b_ = simde_float64x2_to_private(b),
c_ = simde_float64x2_to_private(c);
r_.sv128 = __riscv_vfnmsac_vv_f64m1(a_.sv128 , b_.sv128 , c_.sv128 , 2);
return simde_float64x2_from_private(r_);
#else #else
return simde_vaddq_f64(a, simde_vnegq_f64(simde_vmulq_f64(b, c))); return simde_vaddq_f64(a, simde_vnegq_f64(simde_vmulq_f64(b, c)));
#endif #endif
......
arm/neon/fms_n.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_FMS_N_H) #if !defined(SIMDE_ARM_NEON_FMS_N_H)
...@@ -40,6 +41,13 @@ simde_float16x4_t ...@@ -40,6 +41,13 @@ simde_float16x4_t
simde_vfms_n_f16(simde_float16x4_t a, simde_float16x4_t b, simde_float16_t c) { simde_vfms_n_f16(simde_float16x4_t a, simde_float16x4_t b, simde_float16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399) && defined(SIMDE_ARM_NEON_FP16) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399) && defined(SIMDE_ARM_NEON_FP16)
return vfms_n_f16(a, b, c); return vfms_n_f16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
simde_float16x4_private
r_,
a_ = simde_float16x4_to_private(a),
b_ = simde_float16x4_to_private(b);
r_.sv64 = __riscv_vfnmsac_vf_f16m1(a_.sv64 , c , b_.sv64 , 4);
return simde_float16x4_from_private(r_);
#else #else
return simde_vfms_f16(a, b, simde_vdup_n_f16(c)); return simde_vfms_f16(a, b, simde_vdup_n_f16(c));
#endif #endif
...@@ -54,6 +62,13 @@ simde_float16x8_t ...@@ -54,6 +62,13 @@ simde_float16x8_t
simde_vfmsq_n_f16(simde_float16x8_t a, simde_float16x8_t b, simde_float16_t c) { simde_vfmsq_n_f16(simde_float16x8_t a, simde_float16x8_t b, simde_float16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399) && defined(SIMDE_ARM_NEON_FP16) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399) && defined(SIMDE_ARM_NEON_FP16)
return vfmsq_n_f16(a, b, c); return vfmsq_n_f16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
simde_float16x8_private
r_,
a_ = simde_float16x8_to_private(a),
b_ = simde_float16x8_to_private(b);
r_.sv128 = __riscv_vfnmsac_vf_f16m1(a_.sv128 , c , b_.sv128 , 8);
return simde_float16x8_from_private(r_);
#else #else
return simde_vfmsq_f16(a, b, simde_vdupq_n_f16(c)); return simde_vfmsq_f16(a, b, simde_vdupq_n_f16(c));
#endif #endif
...@@ -68,6 +83,13 @@ simde_float32x2_t ...@@ -68,6 +83,13 @@ simde_float32x2_t
simde_vfms_n_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32_t c) { simde_vfms_n_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399)
return vfms_n_f32(a, b, c); return vfms_n_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x2_private
r_,
a_ = simde_float32x2_to_private(a),
b_ = simde_float32x2_to_private(b);
r_.sv64 = __riscv_vfnmsac_vf_f32m1(a_.sv64 , c , b_.sv64 , 2);
return simde_float32x2_from_private(r_);
#else #else
return simde_vfms_f32(a, b, simde_vdup_n_f32(c)); return simde_vfms_f32(a, b, simde_vdup_n_f32(c));
#endif #endif
...@@ -82,6 +104,13 @@ simde_float64x1_t ...@@ -82,6 +104,13 @@ simde_float64x1_t
simde_vfms_n_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64_t c) { simde_vfms_n_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0))
return vfms_n_f64(a, b, c); return vfms_n_f64(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float64x1_private
r_,
a_ = simde_float64x1_to_private(a),
b_ = simde_float64x1_to_private(b);
r_.sv64 = __riscv_vfnmsac_vf_f64m1(a_.sv64 , c , b_.sv64 , 1);
return simde_float64x1_from_private(r_);
#else #else
return simde_vfms_f64(a, b, simde_vdup_n_f64(c)); return simde_vfms_f64(a, b, simde_vdup_n_f64(c));
#endif #endif
...@@ -96,6 +125,13 @@ simde_float32x4_t ...@@ -96,6 +125,13 @@ simde_float32x4_t
simde_vfmsq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32_t c) { simde_vfmsq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399)
return vfmsq_n_f32(a, b, c); return vfmsq_n_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x4_private
r_,
a_ = simde_float32x4_to_private(a),
b_ = simde_float32x4_to_private(b);
r_.sv128 = __riscv_vfnmsac_vf_f32m1(a_.sv128 , c , b_.sv128 , 4);
return simde_float32x4_from_private(r_);
#else #else
return simde_vfmsq_f32(a, b, simde_vdupq_n_f32(c)); return simde_vfmsq_f32(a, b, simde_vdupq_n_f32(c));
#endif #endif
...@@ -110,6 +146,13 @@ simde_float64x2_t ...@@ -110,6 +146,13 @@ simde_float64x2_t
simde_vfmsq_n_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64_t c) { simde_vfmsq_n_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0))
return vfmsq_n_f64(a, b, c); return vfmsq_n_f64(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float64x2_private
r_,
a_ = simde_float64x2_to_private(a),
b_ = simde_float64x2_to_private(b);
r_.sv128 = __riscv_vfnmsac_vf_f64m1(a_.sv128 , c , b_.sv128 , 2);
return simde_float64x2_from_private(r_);
#else #else
return simde_vfmsq_f64(a, b, simde_vdupq_n_f64(c)); return simde_vfmsq_f64(a, b, simde_vdupq_n_f64(c));
#endif #endif
......
arm/neon/get_high.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_GET_HIGH_H) #if !defined(SIMDE_ARM_NEON_GET_HIGH_H)
...@@ -43,12 +44,14 @@ simde_vget_high_f16(simde_float16x8_t a) { ...@@ -43,12 +44,14 @@ simde_vget_high_f16(simde_float16x8_t a) {
#else #else
simde_float16x4_private r_; simde_float16x4_private r_;
simde_float16x8_private a_ = simde_float16x8_to_private(a); simde_float16x8_private a_ = simde_float16x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE) && SIMDE_ARCH_RISCV_ZVFH
r_.sv64 = __riscv_vslidedown_vx_f16m1(a_.sv128 , 4 , 8);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = a_.values[i + (sizeof(r_.values) / sizeof(r_.values[0]))]; r_.values[i] = a_.values[i + (sizeof(r_.values) / sizeof(r_.values[0]))];
} }
#endif
return simde_float16x4_from_private(r_); return simde_float16x4_from_private(r_);
#endif #endif
} }
...@@ -66,7 +69,9 @@ simde_vget_high_f32(simde_float32x4_t a) { ...@@ -66,7 +69,9 @@ simde_vget_high_f32(simde_float32x4_t a) {
simde_float32x2_private r_; simde_float32x2_private r_;
simde_float32x4_private a_ = simde_float32x4_to_private(a); simde_float32x4_private a_ = simde_float32x4_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_f32m1(a_.sv128 , 2 , 4);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 2, 3); r_.values = __builtin_shufflevector(a_.values, a_.values, 2, 3);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -92,7 +97,9 @@ simde_vget_high_f64(simde_float64x2_t a) { ...@@ -92,7 +97,9 @@ simde_vget_high_f64(simde_float64x2_t a) {
simde_float64x1_private r_; simde_float64x1_private r_;
simde_float64x2_private a_ = simde_float64x2_to_private(a); simde_float64x2_private a_ = simde_float64x2_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_f64m1(a_.sv128 , 1 , 2);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 1); r_.values = __builtin_shufflevector(a_.values, a_.values, 1);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -118,7 +125,9 @@ simde_vget_high_s8(simde_int8x16_t a) { ...@@ -118,7 +125,9 @@ simde_vget_high_s8(simde_int8x16_t a) {
simde_int8x8_private r_; simde_int8x8_private r_;
simde_int8x16_private a_ = simde_int8x16_to_private(a); simde_int8x16_private a_ = simde_int8x16_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_i8m1(a_.sv128 , 8 , 16);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 8, 9, 10, 11, 12, 13, 14, 15); r_.values = __builtin_shufflevector(a_.values, a_.values, 8, 9, 10, 11, 12, 13, 14, 15);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -144,7 +153,9 @@ simde_vget_high_s16(simde_int16x8_t a) { ...@@ -144,7 +153,9 @@ simde_vget_high_s16(simde_int16x8_t a) {
simde_int16x4_private r_; simde_int16x4_private r_;
simde_int16x8_private a_ = simde_int16x8_to_private(a); simde_int16x8_private a_ = simde_int16x8_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_i16m1(a_.sv128 , 4 , 8);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 4, 5, 6, 7); r_.values = __builtin_shufflevector(a_.values, a_.values, 4, 5, 6, 7);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -170,7 +181,9 @@ simde_vget_high_s32(simde_int32x4_t a) { ...@@ -170,7 +181,9 @@ simde_vget_high_s32(simde_int32x4_t a) {
simde_int32x2_private r_; simde_int32x2_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a); simde_int32x4_private a_ = simde_int32x4_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_i32m1(a_.sv128 , 2 , 4);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 2, 3); r_.values = __builtin_shufflevector(a_.values, a_.values, 2, 3);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -196,7 +209,9 @@ simde_vget_high_s64(simde_int64x2_t a) { ...@@ -196,7 +209,9 @@ simde_vget_high_s64(simde_int64x2_t a) {
simde_int64x1_private r_; simde_int64x1_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a); simde_int64x2_private a_ = simde_int64x2_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_i64m1(a_.sv128 , 1 , 2);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 1); r_.values = __builtin_shufflevector(a_.values, a_.values, 1);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -222,7 +237,9 @@ simde_vget_high_u8(simde_uint8x16_t a) { ...@@ -222,7 +237,9 @@ simde_vget_high_u8(simde_uint8x16_t a) {
simde_uint8x8_private r_; simde_uint8x8_private r_;
simde_uint8x16_private a_ = simde_uint8x16_to_private(a); simde_uint8x16_private a_ = simde_uint8x16_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_u8m1(a_.sv128 , 8 , 16);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 8, 9, 10, 11, 12, 13, 14,15); r_.values = __builtin_shufflevector(a_.values, a_.values, 8, 9, 10, 11, 12, 13, 14,15);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -248,7 +265,9 @@ simde_vget_high_u16(simde_uint16x8_t a) { ...@@ -248,7 +265,9 @@ simde_vget_high_u16(simde_uint16x8_t a) {
simde_uint16x4_private r_; simde_uint16x4_private r_;
simde_uint16x8_private a_ = simde_uint16x8_to_private(a); simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_u16m1(a_.sv128 , 4 , 8);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 4, 5, 6, 7); r_.values = __builtin_shufflevector(a_.values, a_.values, 4, 5, 6, 7);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -274,7 +293,9 @@ simde_vget_high_u32(simde_uint32x4_t a) { ...@@ -274,7 +293,9 @@ simde_vget_high_u32(simde_uint32x4_t a) {
simde_uint32x2_private r_; simde_uint32x2_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a); simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_u32m1(a_.sv128 , 2 , 4);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 2, 3); r_.values = __builtin_shufflevector(a_.values, a_.values, 2, 3);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -300,7 +321,9 @@ simde_vget_high_u64(simde_uint64x2_t a) { ...@@ -300,7 +321,9 @@ simde_vget_high_u64(simde_uint64x2_t a) {
simde_uint64x1_private r_; simde_uint64x1_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a); simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vslidedown_vx_u64m1(a_.sv128 , 1 , 2);
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 1); r_.values = __builtin_shufflevector(a_.values, a_.values, 1);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
......
arm/neon/get_low.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_GET_LOW_H) #if !defined(SIMDE_ARM_NEON_GET_LOW_H)
...@@ -44,10 +45,14 @@ simde_vget_low_f16(simde_float16x8_t a) { ...@@ -44,10 +45,14 @@ simde_vget_low_f16(simde_float16x8_t a) {
simde_float16x4_private r_; simde_float16x4_private r_;
simde_float16x8_private a_ = simde_float16x8_to_private(a); simde_float16x8_private a_ = simde_float16x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
r_.sv64 = a_.sv128;
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = a_.values[i]; r_.values[i] = a_.values[i];
} }
#endif
return simde_float16x4_from_private(r_); return simde_float16x4_from_private(r_);
#endif #endif
...@@ -66,7 +71,9 @@ simde_vget_low_f32(simde_float32x4_t a) { ...@@ -66,7 +71,9 @@ simde_vget_low_f32(simde_float32x4_t a) {
simde_float32x2_private r_; simde_float32x2_private r_;
simde_float32x4_private a_ = simde_float32x4_to_private(a); simde_float32x4_private a_ = simde_float32x4_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1); r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -92,7 +99,9 @@ simde_vget_low_f64(simde_float64x2_t a) { ...@@ -92,7 +99,9 @@ simde_vget_low_f64(simde_float64x2_t a) {
simde_float64x1_private r_; simde_float64x1_private r_;
simde_float64x2_private a_ = simde_float64x2_to_private(a); simde_float64x2_private a_ = simde_float64x2_to_private(a);
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0); r_.values = __builtin_shufflevector(a_.values, a_.values, 0);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -120,6 +129,8 @@ simde_vget_low_s8(simde_int8x16_t a) { ...@@ -120,6 +129,8 @@ simde_vget_low_s8(simde_int8x16_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3, 4, 5, 6, 7); r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3, 4, 5, 6, 7);
...@@ -150,6 +161,8 @@ simde_vget_low_s16(simde_int16x8_t a) { ...@@ -150,6 +161,8 @@ simde_vget_low_s16(simde_int16x8_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3); r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3);
...@@ -180,6 +193,8 @@ simde_vget_low_s32(simde_int32x4_t a) { ...@@ -180,6 +193,8 @@ simde_vget_low_s32(simde_int32x4_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1); r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1);
...@@ -210,6 +225,8 @@ simde_vget_low_s64(simde_int64x2_t a) { ...@@ -210,6 +225,8 @@ simde_vget_low_s64(simde_int64x2_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0); r_.values = __builtin_shufflevector(a_.values, a_.values, 0);
...@@ -240,6 +257,8 @@ simde_vget_low_u8(simde_uint8x16_t a) { ...@@ -240,6 +257,8 @@ simde_vget_low_u8(simde_uint8x16_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3, 4, 5, 6, 7); r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3, 4, 5, 6, 7);
...@@ -270,6 +289,8 @@ simde_vget_low_u16(simde_uint16x8_t a) { ...@@ -270,6 +289,8 @@ simde_vget_low_u16(simde_uint16x8_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3); r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1, 2, 3);
...@@ -300,6 +321,8 @@ simde_vget_low_u32(simde_uint32x4_t a) { ...@@ -300,6 +321,8 @@ simde_vget_low_u32(simde_uint32x4_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1); r_.values = __builtin_shufflevector(a_.values, a_.values, 0, 1);
...@@ -330,6 +353,8 @@ simde_vget_low_u64(simde_uint64x2_t a) { ...@@ -330,6 +353,8 @@ simde_vget_low_u64(simde_uint64x2_t a) {
#if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE2_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_movepi64_pi64(a_.m128i); r_.m64 = _mm_movepi64_pi64(a_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = a_.sv128;
#else #else
#if HEDLEY_HAS_BUILTIN(__builtin_shufflevector) #if HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
r_.values = __builtin_shufflevector(a_.values, a_.values, 0); r_.values = __builtin_shufflevector(a_.values, a_.values, 0);
......
arm/neon/hsub.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
/* TODO: the 128-bit versions only require AVX-512 because of the final /* TODO: the 128-bit versions only require AVX-512 because of the final
...@@ -46,6 +47,14 @@ simde_int8x8_t ...@@ -46,6 +47,14 @@ simde_int8x8_t
simde_vhsub_s8(simde_int8x8_t a, simde_int8x8_t b) { simde_vhsub_s8(simde_int8x8_t a, simde_int8x8_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vhsub_s8(a, b); return vhsub_s8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int8x8_private
r_,
a_ = simde_int8x8_to_private(a),
b_ = simde_int8x8_to_private(b);
r_.sv64 = __riscv_vasub_vv_i8m1(a_.sv64, b_.sv64, 2, 8);
return simde_int8x8_from_private(r_);
#else #else
return simde_vmovn_s16(simde_vshrq_n_s16(simde_vsubl_s8(a, b), 1)); return simde_vmovn_s16(simde_vshrq_n_s16(simde_vsubl_s8(a, b), 1));
#endif #endif
...@@ -60,6 +69,14 @@ simde_int16x4_t ...@@ -60,6 +69,14 @@ simde_int16x4_t
simde_vhsub_s16(simde_int16x4_t a, simde_int16x4_t b) { simde_vhsub_s16(simde_int16x4_t a, simde_int16x4_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vhsub_s16(a, b); return vhsub_s16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x4_private
r_,
a_ = simde_int16x4_to_private(a),
b_ = simde_int16x4_to_private(b);
r_.sv64 = __riscv_vasub_vv_i16m1(a_.sv64, b_.sv64, 2, 4);
return simde_int16x4_from_private(r_);
#else #else
return simde_vmovn_s32(simde_vshrq_n_s32(simde_vsubl_s16(a, b), 1)); return simde_vmovn_s32(simde_vshrq_n_s32(simde_vsubl_s16(a, b), 1));
#endif #endif
...@@ -74,6 +91,14 @@ simde_int32x2_t ...@@ -74,6 +91,14 @@ simde_int32x2_t
simde_vhsub_s32(simde_int32x2_t a, simde_int32x2_t b) { simde_vhsub_s32(simde_int32x2_t a, simde_int32x2_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vhsub_s32(a, b); return vhsub_s32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x2_private
r_,
a_ = simde_int32x2_to_private(a),
b_ = simde_int32x2_to_private(b);
r_.sv64 = __riscv_vasub_vv_i32m1(a_.sv64, b_.sv64, 2, 2);
return simde_int32x2_from_private(r_);
#else #else
return simde_vmovn_s64(simde_vshrq_n_s64(simde_vsubl_s32(a, b), 1)); return simde_vmovn_s64(simde_vshrq_n_s64(simde_vsubl_s32(a, b), 1));
#endif #endif
...@@ -88,6 +113,14 @@ simde_uint8x8_t ...@@ -88,6 +113,14 @@ simde_uint8x8_t
simde_vhsub_u8(simde_uint8x8_t a, simde_uint8x8_t b) { simde_vhsub_u8(simde_uint8x8_t a, simde_uint8x8_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vhsub_u8(a, b); return vhsub_u8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint8x8_private
r_,
a_ = simde_uint8x8_to_private(a),
b_ = simde_uint8x8_to_private(b);
r_.sv64 = __riscv_vasubu_vv_u8m1(a_.sv64, b_.sv64, 2, 8);
return simde_uint8x8_from_private(r_);
#else #else
return simde_vmovn_u16(simde_vshrq_n_u16(simde_vsubl_u8(a, b), 1)); return simde_vmovn_u16(simde_vshrq_n_u16(simde_vsubl_u8(a, b), 1));
#endif #endif
...@@ -102,6 +135,14 @@ simde_uint16x4_t ...@@ -102,6 +135,14 @@ simde_uint16x4_t
simde_vhsub_u16(simde_uint16x4_t a, simde_uint16x4_t b) { simde_vhsub_u16(simde_uint16x4_t a, simde_uint16x4_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vhsub_u16(a, b); return vhsub_u16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x4_private
r_,
a_ = simde_uint16x4_to_private(a),
b_ = simde_uint16x4_to_private(b);
r_.sv64 = __riscv_vasubu_vv_u16m1(a_.sv64, b_.sv64, 2, 4);
return simde_uint16x4_from_private(r_);
#else #else
return simde_vmovn_u32(simde_vshrq_n_u32(simde_vsubl_u16(a, b), 1)); return simde_vmovn_u32(simde_vshrq_n_u32(simde_vsubl_u16(a, b), 1));
#endif #endif
...@@ -116,6 +157,14 @@ simde_uint32x2_t ...@@ -116,6 +157,14 @@ simde_uint32x2_t
simde_vhsub_u32(simde_uint32x2_t a, simde_uint32x2_t b) { simde_vhsub_u32(simde_uint32x2_t a, simde_uint32x2_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vhsub_u32(a, b); return vhsub_u32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x2_private
r_,
a_ = simde_uint32x2_to_private(a),
b_ = simde_uint32x2_to_private(b);
r_.sv64 = __riscv_vasubu_vv_u32m1(a_.sv64, b_.sv64, 2, 2);
return simde_uint32x2_from_private(r_);
#else #else
return simde_vmovn_u64(simde_vshrq_n_u64(simde_vsubl_u32(a, b), 1)); return simde_vmovn_u64(simde_vshrq_n_u64(simde_vsubl_u32(a, b), 1));
#endif #endif
...@@ -138,6 +187,8 @@ simde_vhsubq_s8(simde_int8x16_t a, simde_int8x16_t b) { ...@@ -138,6 +187,8 @@ simde_vhsubq_s8(simde_int8x16_t a, simde_int8x16_t b) {
#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE) #if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
r_.m128i = _mm256_cvtepi16_epi8(_mm256_srai_epi16(_mm256_sub_epi16(_mm256_cvtepi8_epi16(a_.m128i), _mm256_cvtepi8_epi16(b_.m128i)), 1)); r_.m128i = _mm256_cvtepi16_epi8(_mm256_srai_epi16(_mm256_sub_epi16(_mm256_cvtepi8_epi16(a_.m128i), _mm256_cvtepi8_epi16(b_.m128i)), 1));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vasub_vv_i8m1(a_.sv128, b_.sv128, 2, 16);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -166,6 +217,8 @@ simde_vhsubq_s16(simde_int16x8_t a, simde_int16x8_t b) { ...@@ -166,6 +217,8 @@ simde_vhsubq_s16(simde_int16x8_t a, simde_int16x8_t b) {
#if defined(SIMDE_X86_AVX512VL_NATIVE) #if defined(SIMDE_X86_AVX512VL_NATIVE)
r_.m128i = _mm256_cvtepi32_epi16(_mm256_srai_epi32(_mm256_sub_epi32(_mm256_cvtepi16_epi32(a_.m128i), _mm256_cvtepi16_epi32(b_.m128i)), 1)); r_.m128i = _mm256_cvtepi32_epi16(_mm256_srai_epi32(_mm256_sub_epi32(_mm256_cvtepi16_epi32(a_.m128i), _mm256_cvtepi16_epi32(b_.m128i)), 1));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vasub_vv_i16m1(a_.sv128, b_.sv128, 2, 8);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -194,6 +247,8 @@ simde_vhsubq_s32(simde_int32x4_t a, simde_int32x4_t b) { ...@@ -194,6 +247,8 @@ simde_vhsubq_s32(simde_int32x4_t a, simde_int32x4_t b) {
#if defined(SIMDE_X86_AVX512VL_NATIVE) #if defined(SIMDE_X86_AVX512VL_NATIVE)
r_.m128i = _mm256_cvtepi64_epi32(_mm256_srai_epi64(_mm256_sub_epi64(_mm256_cvtepi32_epi64(a_.m128i), _mm256_cvtepi32_epi64(b_.m128i)), 1)); r_.m128i = _mm256_cvtepi64_epi32(_mm256_srai_epi64(_mm256_sub_epi64(_mm256_cvtepi32_epi64(a_.m128i), _mm256_cvtepi32_epi64(b_.m128i)), 1));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vasub_vv_i32m1(a_.sv128, b_.sv128, 2, 4);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -222,6 +277,8 @@ simde_vhsubq_u8(simde_uint8x16_t a, simde_uint8x16_t b) { ...@@ -222,6 +277,8 @@ simde_vhsubq_u8(simde_uint8x16_t a, simde_uint8x16_t b) {
#if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE) #if defined(SIMDE_X86_AVX512VL_NATIVE) && defined(SIMDE_X86_AVX512BW_NATIVE)
r_.m128i = _mm256_cvtepi16_epi8(_mm256_srli_epi16(_mm256_sub_epi16(_mm256_cvtepu8_epi16(a_.m128i), _mm256_cvtepu8_epi16(b_.m128i)), 1)); r_.m128i = _mm256_cvtepi16_epi8(_mm256_srli_epi16(_mm256_sub_epi16(_mm256_cvtepu8_epi16(a_.m128i), _mm256_cvtepu8_epi16(b_.m128i)), 1));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vasubu_vv_u8m1(a_.sv128, b_.sv128, 2, 16);
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
v128_t lo = v128_t lo =
wasm_u16x8_shr(wasm_i16x8_sub(wasm_u16x8_extend_low_u8x16(a_.v128), wasm_u16x8_shr(wasm_i16x8_sub(wasm_u16x8_extend_low_u8x16(a_.v128),
...@@ -261,6 +318,8 @@ simde_vhsubq_u16(simde_uint16x8_t a, simde_uint16x8_t b) { ...@@ -261,6 +318,8 @@ simde_vhsubq_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
#if defined(SIMDE_X86_AVX512VL_NATIVE) #if defined(SIMDE_X86_AVX512VL_NATIVE)
r_.m128i = _mm256_cvtepi32_epi16(_mm256_srli_epi32(_mm256_sub_epi32(_mm256_cvtepu16_epi32(a_.m128i), _mm256_cvtepu16_epi32(b_.m128i)), 1)); r_.m128i = _mm256_cvtepi32_epi16(_mm256_srli_epi32(_mm256_sub_epi32(_mm256_cvtepu16_epi32(a_.m128i), _mm256_cvtepu16_epi32(b_.m128i)), 1));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vasubu_vv_u16m1(a_.sv128, b_.sv128, 2, 8);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -289,6 +348,8 @@ simde_vhsubq_u32(simde_uint32x4_t a, simde_uint32x4_t b) { ...@@ -289,6 +348,8 @@ simde_vhsubq_u32(simde_uint32x4_t a, simde_uint32x4_t b) {
#if defined(SIMDE_X86_AVX512VL_NATIVE) #if defined(SIMDE_X86_AVX512VL_NATIVE)
r_.m128i = _mm256_cvtepi64_epi32(_mm256_srli_epi64(_mm256_sub_epi64(_mm256_cvtepu32_epi64(a_.m128i), _mm256_cvtepu32_epi64(b_.m128i)), 1)); r_.m128i = _mm256_cvtepi64_epi32(_mm256_srli_epi64(_mm256_sub_epi64(_mm256_cvtepu32_epi64(a_.m128i), _mm256_cvtepu32_epi64(b_.m128i)), 1));
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vasubu_vv_u32m1(a_.sv128, b_.sv128, 2, 4);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
......
arm/neon/mla.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLA_H) #if !defined(SIMDE_ARM_NEON_MLA_H)
...@@ -41,6 +42,15 @@ simde_float32x2_t ...@@ -41,6 +42,15 @@ simde_float32x2_t
simde_vmla_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) { simde_vmla_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmla_f32(a, b, c); return vmla_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x2_private
r_,
a_ = simde_float32x2_to_private(a),
b_ = simde_float32x2_to_private(b),
c_ = simde_float32x2_to_private(c);
r_.sv64 = __riscv_vfmacc_vv_f32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_float32x2_from_private(r_);
#else #else
return simde_vadd_f32(simde_vmul_f32(b, c), a); return simde_vadd_f32(simde_vmul_f32(b, c), a);
#endif #endif
...@@ -55,6 +65,15 @@ simde_float64x1_t ...@@ -55,6 +65,15 @@ simde_float64x1_t
simde_vmla_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) { simde_vmla_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmla_f64(a, b, c); return vmla_f64(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float64x1_private
r_,
a_ = simde_float64x1_to_private(a),
b_ = simde_float64x1_to_private(b),
c_ = simde_float64x1_to_private(c);
r_.sv64 = __riscv_vfmacc_vv_f64m1(a_.sv64 , b_.sv64 , c_.sv64 , 1);
return simde_float64x1_from_private(r_);
#else #else
return simde_vadd_f64(simde_vmul_f64(b, c), a); return simde_vadd_f64(simde_vmul_f64(b, c), a);
#endif #endif
...@@ -69,6 +88,15 @@ simde_int8x8_t ...@@ -69,6 +88,15 @@ simde_int8x8_t
simde_vmla_s8(simde_int8x8_t a, simde_int8x8_t b, simde_int8x8_t c) { simde_vmla_s8(simde_int8x8_t a, simde_int8x8_t b, simde_int8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmla_s8(a, b, c); return vmla_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int8x8_private
r_,
a_ = simde_int8x8_to_private(a),
b_ = simde_int8x8_to_private(b),
c_ = simde_int8x8_to_private(c);
r_.sv64 = __riscv_vmacc_vv_i8m1(a_.sv64 , b_.sv64 , c_.sv64 , 8);
return simde_int8x8_from_private(r_);
#else #else
return simde_vadd_s8(simde_vmul_s8(b, c), a); return simde_vadd_s8(simde_vmul_s8(b, c), a);
#endif #endif
...@@ -83,6 +111,15 @@ simde_int16x4_t ...@@ -83,6 +111,15 @@ simde_int16x4_t
simde_vmla_s16(simde_int16x4_t a, simde_int16x4_t b, simde_int16x4_t c) { simde_vmla_s16(simde_int16x4_t a, simde_int16x4_t b, simde_int16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmla_s16(a, b, c); return vmla_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x4_private
r_,
a_ = simde_int16x4_to_private(a),
b_ = simde_int16x4_to_private(b),
c_ = simde_int16x4_to_private(c);
r_.sv64 = __riscv_vmacc_vv_i16m1(a_.sv64 , b_.sv64 , c_.sv64 , 4);
return simde_int16x4_from_private(r_);
#else #else
return simde_vadd_s16(simde_vmul_s16(b, c), a); return simde_vadd_s16(simde_vmul_s16(b, c), a);
#endif #endif
...@@ -97,6 +134,15 @@ simde_int32x2_t ...@@ -97,6 +134,15 @@ simde_int32x2_t
simde_vmla_s32(simde_int32x2_t a, simde_int32x2_t b, simde_int32x2_t c) { simde_vmla_s32(simde_int32x2_t a, simde_int32x2_t b, simde_int32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmla_s32(a, b, c); return vmla_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x2_private
r_,
a_ = simde_int32x2_to_private(a),
b_ = simde_int32x2_to_private(b),
c_ = simde_int32x2_to_private(c);
r_.sv64 = __riscv_vmacc_vv_i32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_int32x2_from_private(r_);
#else #else
return simde_vadd_s32(simde_vmul_s32(b, c), a); return simde_vadd_s32(simde_vmul_s32(b, c), a);
#endif #endif
...@@ -111,6 +157,15 @@ simde_uint8x8_t ...@@ -111,6 +157,15 @@ simde_uint8x8_t
simde_vmla_u8(simde_uint8x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) { simde_vmla_u8(simde_uint8x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmla_u8(a, b, c); return vmla_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint8x8_private
r_,
a_ = simde_uint8x8_to_private(a),
b_ = simde_uint8x8_to_private(b),
c_ = simde_uint8x8_to_private(c);
r_.sv64 = __riscv_vmacc_vv_u8m1(a_.sv64 , b_.sv64 , c_.sv64 , 8);
return simde_uint8x8_from_private(r_);
#else #else
return simde_vadd_u8(simde_vmul_u8(b, c), a); return simde_vadd_u8(simde_vmul_u8(b, c), a);
#endif #endif
...@@ -125,6 +180,15 @@ simde_uint16x4_t ...@@ -125,6 +180,15 @@ simde_uint16x4_t
simde_vmla_u16(simde_uint16x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) { simde_vmla_u16(simde_uint16x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmla_u16(a, b, c); return vmla_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x4_private
r_,
a_ = simde_uint16x4_to_private(a),
b_ = simde_uint16x4_to_private(b),
c_ = simde_uint16x4_to_private(c);
r_.sv64 = __riscv_vmacc_vv_u16m1(a_.sv64 , b_.sv64 , c_.sv64 , 4);
return simde_uint16x4_from_private(r_);
#else #else
return simde_vadd_u16(simde_vmul_u16(b, c), a); return simde_vadd_u16(simde_vmul_u16(b, c), a);
#endif #endif
...@@ -139,6 +203,15 @@ simde_uint32x2_t ...@@ -139,6 +203,15 @@ simde_uint32x2_t
simde_vmla_u32(simde_uint32x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) { simde_vmla_u32(simde_uint32x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmla_u32(a, b, c); return vmla_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x2_private
r_,
a_ = simde_uint32x2_to_private(a),
b_ = simde_uint32x2_to_private(b),
c_ = simde_uint32x2_to_private(c);
r_.sv64 = __riscv_vmacc_vv_u32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_uint32x2_from_private(r_);
#else #else
return simde_vadd_u32(simde_vmul_u32(b, c), a); return simde_vadd_u32(simde_vmul_u32(b, c), a);
#endif #endif
...@@ -156,7 +229,7 @@ simde_vmlaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) { ...@@ -156,7 +229,7 @@ simde_vmlaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) {
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE) #elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
return vec_madd(b, c, a); return vec_madd(b, c, a);
#elif \ #elif \
defined(SIMDE_X86_FMA_NATIVE) defined(SIMDE_X86_FMA_NATIVE) || defined(SIMDE_RISCV_V_NATIVE)
simde_float32x4_private simde_float32x4_private
r_, r_,
a_ = simde_float32x4_to_private(a), a_ = simde_float32x4_to_private(a),
...@@ -165,6 +238,8 @@ simde_vmlaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) { ...@@ -165,6 +238,8 @@ simde_vmlaq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) {
#if defined(SIMDE_X86_FMA_NATIVE) #if defined(SIMDE_X86_FMA_NATIVE)
r_.m128 = _mm_fmadd_ps(b_.m128, c_.m128, a_.m128); r_.m128 = _mm_fmadd_ps(b_.m128, c_.m128, a_.m128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfmacc_vv_f32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
#endif #endif
return simde_float32x4_from_private(r_); return simde_float32x4_from_private(r_);
...@@ -185,7 +260,7 @@ simde_vmlaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) { ...@@ -185,7 +260,7 @@ simde_vmlaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) {
#elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) #elif defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
return vec_madd(b, c, a); return vec_madd(b, c, a);
#elif \ #elif \
defined(SIMDE_X86_FMA_NATIVE) defined(SIMDE_X86_FMA_NATIVE) || defined(SIMDE_RISCV_V_NATIVE)
simde_float64x2_private simde_float64x2_private
r_, r_,
a_ = simde_float64x2_to_private(a), a_ = simde_float64x2_to_private(a),
...@@ -194,6 +269,8 @@ simde_vmlaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) { ...@@ -194,6 +269,8 @@ simde_vmlaq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) {
#if defined(SIMDE_X86_FMA_NATIVE) #if defined(SIMDE_X86_FMA_NATIVE)
r_.m128d = _mm_fmadd_pd(b_.m128d, c_.m128d, a_.m128d); r_.m128d = _mm_fmadd_pd(b_.m128d, c_.m128d, a_.m128d);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfmacc_vv_f64m1(a_.sv128 , b_.sv128 , c_.sv128 , 2);
#endif #endif
return simde_float64x2_from_private(r_); return simde_float64x2_from_private(r_);
...@@ -211,6 +288,15 @@ simde_int8x16_t ...@@ -211,6 +288,15 @@ simde_int8x16_t
simde_vmlaq_s8(simde_int8x16_t a, simde_int8x16_t b, simde_int8x16_t c) { simde_vmlaq_s8(simde_int8x16_t a, simde_int8x16_t b, simde_int8x16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_s8(a, b, c); return vmlaq_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int8x16_private
r_,
a_ = simde_int8x16_to_private(a),
b_ = simde_int8x16_to_private(b),
c_ = simde_int8x16_to_private(c);
r_.sv128 = __riscv_vmacc_vv_i8m1(a_.sv128 , b_.sv128 , c_.sv128 , 16);
return simde_int8x16_from_private(r_);
#else #else
return simde_vaddq_s8(simde_vmulq_s8(b, c), a); return simde_vaddq_s8(simde_vmulq_s8(b, c), a);
#endif #endif
...@@ -225,6 +311,15 @@ simde_int16x8_t ...@@ -225,6 +311,15 @@ simde_int16x8_t
simde_vmlaq_s16(simde_int16x8_t a, simde_int16x8_t b, simde_int16x8_t c) { simde_vmlaq_s16(simde_int16x8_t a, simde_int16x8_t b, simde_int16x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_s16(a, b, c); return vmlaq_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private
r_,
a_ = simde_int16x8_to_private(a),
b_ = simde_int16x8_to_private(b),
c_ = simde_int16x8_to_private(c);
r_.sv128 = __riscv_vmacc_vv_i16m1(a_.sv128 , b_.sv128 , c_.sv128 , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vaddq_s16(simde_vmulq_s16(b, c), a); return simde_vaddq_s16(simde_vmulq_s16(b, c), a);
#endif #endif
...@@ -239,6 +334,15 @@ simde_int32x4_t ...@@ -239,6 +334,15 @@ simde_int32x4_t
simde_vmlaq_s32(simde_int32x4_t a, simde_int32x4_t b, simde_int32x4_t c) { simde_vmlaq_s32(simde_int32x4_t a, simde_int32x4_t b, simde_int32x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_s32(a, b, c); return vmlaq_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private
r_,
a_ = simde_int32x4_to_private(a),
b_ = simde_int32x4_to_private(b),
c_ = simde_int32x4_to_private(c);
r_.sv128 = __riscv_vmacc_vv_i32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vaddq_s32(simde_vmulq_s32(b, c), a); return simde_vaddq_s32(simde_vmulq_s32(b, c), a);
#endif #endif
...@@ -253,6 +357,15 @@ simde_uint8x16_t ...@@ -253,6 +357,15 @@ simde_uint8x16_t
simde_vmlaq_u8(simde_uint8x16_t a, simde_uint8x16_t b, simde_uint8x16_t c) { simde_vmlaq_u8(simde_uint8x16_t a, simde_uint8x16_t b, simde_uint8x16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_u8(a, b, c); return vmlaq_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint8x16_private
r_,
a_ = simde_uint8x16_to_private(a),
b_ = simde_uint8x16_to_private(b),
c_ = simde_uint8x16_to_private(c);
r_.sv128 = __riscv_vmacc_vv_u8m1(a_.sv128 , b_.sv128 , c_.sv128 , 16);
return simde_uint8x16_from_private(r_);
#else #else
return simde_vaddq_u8(simde_vmulq_u8(b, c), a); return simde_vaddq_u8(simde_vmulq_u8(b, c), a);
#endif #endif
...@@ -267,6 +380,15 @@ simde_uint16x8_t ...@@ -267,6 +380,15 @@ simde_uint16x8_t
simde_vmlaq_u16(simde_uint16x8_t a, simde_uint16x8_t b, simde_uint16x8_t c) { simde_vmlaq_u16(simde_uint16x8_t a, simde_uint16x8_t b, simde_uint16x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_u16(a, b, c); return vmlaq_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private
r_,
a_ = simde_uint16x8_to_private(a),
b_ = simde_uint16x8_to_private(b),
c_ = simde_uint16x8_to_private(c);
r_.sv128 = __riscv_vmacc_vv_u16m1(a_.sv128 , b_.sv128 , c_.sv128 , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vaddq_u16(simde_vmulq_u16(b, c), a); return simde_vaddq_u16(simde_vmulq_u16(b, c), a);
#endif #endif
...@@ -281,6 +403,15 @@ simde_uint32x4_t ...@@ -281,6 +403,15 @@ simde_uint32x4_t
simde_vmlaq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c) { simde_vmlaq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_u32(a, b, c); return vmlaq_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private
r_,
a_ = simde_uint32x4_to_private(a),
b_ = simde_uint32x4_to_private(b),
c_ = simde_uint32x4_to_private(c);
r_.sv128 = __riscv_vmacc_vv_u32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vaddq_u32(simde_vmulq_u32(b, c), a); return simde_vaddq_u32(simde_vmulq_u32(b, c), a);
#endif #endif
......
arm/neon/mla_n.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLA_N_H) #if !defined(SIMDE_ARM_NEON_MLA_N_H)
...@@ -48,7 +49,9 @@ simde_vmla_n_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32 c) { ...@@ -48,7 +49,9 @@ simde_vmla_n_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32 c) {
a_ = simde_float32x2_to_private(a), a_ = simde_float32x2_to_private(a),
b_ = simde_float32x2_to_private(b); b_ = simde_float32x2_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vfmacc_vf_f32m1(a_.sv64 , c , b_.sv64 , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -76,7 +79,9 @@ simde_vmla_n_s16(simde_int16x4_t a, simde_int16x4_t b, int16_t c) { ...@@ -76,7 +79,9 @@ simde_vmla_n_s16(simde_int16x4_t a, simde_int16x4_t b, int16_t c) {
a_ = simde_int16x4_to_private(a), a_ = simde_int16x4_to_private(a),
b_ = simde_int16x4_to_private(b); b_ = simde_int16x4_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784) && !defined(SIMDE_BUG_GCC_100762) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmacc_vx_i16m1(a_.sv64 , c , b_.sv64 , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784) && !defined(SIMDE_BUG_GCC_100762)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -104,7 +109,9 @@ simde_vmla_n_s32(simde_int32x2_t a, simde_int32x2_t b, int32_t c) { ...@@ -104,7 +109,9 @@ simde_vmla_n_s32(simde_int32x2_t a, simde_int32x2_t b, int32_t c) {
a_ = simde_int32x2_to_private(a), a_ = simde_int32x2_to_private(a),
b_ = simde_int32x2_to_private(b); b_ = simde_int32x2_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmacc_vx_i32m1(a_.sv64 , c , b_.sv64 , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -132,7 +139,9 @@ simde_vmla_n_u16(simde_uint16x4_t a, simde_uint16x4_t b, uint16_t c) { ...@@ -132,7 +139,9 @@ simde_vmla_n_u16(simde_uint16x4_t a, simde_uint16x4_t b, uint16_t c) {
a_ = simde_uint16x4_to_private(a), a_ = simde_uint16x4_to_private(a),
b_ = simde_uint16x4_to_private(b); b_ = simde_uint16x4_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmacc_vx_u16m1(a_.sv64 , c , b_.sv64 , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -160,7 +169,9 @@ simde_vmla_n_u32(simde_uint32x2_t a, simde_uint32x2_t b, uint32_t c) { ...@@ -160,7 +169,9 @@ simde_vmla_n_u32(simde_uint32x2_t a, simde_uint32x2_t b, uint32_t c) {
a_ = simde_uint32x2_to_private(a), a_ = simde_uint32x2_to_private(a),
b_ = simde_uint32x2_to_private(b); b_ = simde_uint32x2_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vmacc_vx_u32m1(a_.sv64 , c , b_.sv64 , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_100762)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -182,7 +193,7 @@ simde_float32x4_t ...@@ -182,7 +193,7 @@ simde_float32x4_t
simde_vmlaq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32 c) { simde_vmlaq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32 c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_n_f32(a, b, c); return vmlaq_n_f32(a, b, c);
#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddq_f32(simde_vmulq_n_f32(b, c), a); return simde_vaddq_f32(simde_vmulq_n_f32(b, c), a);
#else #else
simde_float32x4_private simde_float32x4_private
...@@ -190,7 +201,9 @@ simde_vmlaq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32 c) { ...@@ -190,7 +201,9 @@ simde_vmlaq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32 c) {
a_ = simde_float32x4_to_private(a), a_ = simde_float32x4_to_private(a),
b_ = simde_float32x4_to_private(b); b_ = simde_float32x4_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfmacc_vf_f32m1(a_.sv128 , c , b_.sv128 , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -212,7 +225,7 @@ simde_int16x8_t ...@@ -212,7 +225,7 @@ simde_int16x8_t
simde_vmlaq_n_s16(simde_int16x8_t a, simde_int16x8_t b, int16_t c) { simde_vmlaq_n_s16(simde_int16x8_t a, simde_int16x8_t b, int16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_n_s16(a, b, c); return vmlaq_n_s16(a, b, c);
#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddq_s16(simde_vmulq_n_s16(b, c), a); return simde_vaddq_s16(simde_vmulq_n_s16(b, c), a);
#else #else
simde_int16x8_private simde_int16x8_private
...@@ -220,7 +233,9 @@ simde_vmlaq_n_s16(simde_int16x8_t a, simde_int16x8_t b, int16_t c) { ...@@ -220,7 +233,9 @@ simde_vmlaq_n_s16(simde_int16x8_t a, simde_int16x8_t b, int16_t c) {
a_ = simde_int16x8_to_private(a), a_ = simde_int16x8_to_private(a),
b_ = simde_int16x8_to_private(b); b_ = simde_int16x8_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmacc_vx_i16m1(a_.sv128 , c , b_.sv128 , 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_53784)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -242,7 +257,7 @@ simde_int32x4_t ...@@ -242,7 +257,7 @@ simde_int32x4_t
simde_vmlaq_n_s32(simde_int32x4_t a, simde_int32x4_t b, int32_t c) { simde_vmlaq_n_s32(simde_int32x4_t a, simde_int32x4_t b, int32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_n_s32(a, b, c); return vmlaq_n_s32(a, b, c);
#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddq_s32(simde_vmulq_n_s32(b, c), a); return simde_vaddq_s32(simde_vmulq_n_s32(b, c), a);
#else #else
simde_int32x4_private simde_int32x4_private
...@@ -250,7 +265,9 @@ simde_vmlaq_n_s32(simde_int32x4_t a, simde_int32x4_t b, int32_t c) { ...@@ -250,7 +265,9 @@ simde_vmlaq_n_s32(simde_int32x4_t a, simde_int32x4_t b, int32_t c) {
a_ = simde_int32x4_to_private(a), a_ = simde_int32x4_to_private(a),
b_ = simde_int32x4_to_private(b); b_ = simde_int32x4_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmacc_vx_i32m1(a_.sv128 , c , b_.sv128 , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -272,7 +289,7 @@ simde_uint16x8_t ...@@ -272,7 +289,7 @@ simde_uint16x8_t
simde_vmlaq_n_u16(simde_uint16x8_t a, simde_uint16x8_t b, uint16_t c) { simde_vmlaq_n_u16(simde_uint16x8_t a, simde_uint16x8_t b, uint16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlaq_n_u16(a, b, c); return vmlaq_n_u16(a, b, c);
#elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) #elif SIMDE_NATURAL_VECTOR_SIZE_LE(128) && !defined(SIMDE_RISCV_V_NATIVE)
return simde_vaddq_u16(simde_vmulq_n_u16(b, c), a); return simde_vaddq_u16(simde_vmulq_n_u16(b, c), a);
#else #else
simde_uint16x8_private simde_uint16x8_private
...@@ -280,7 +297,9 @@ simde_vmlaq_n_u16(simde_uint16x8_t a, simde_uint16x8_t b, uint16_t c) { ...@@ -280,7 +297,9 @@ simde_vmlaq_n_u16(simde_uint16x8_t a, simde_uint16x8_t b, uint16_t c) {
a_ = simde_uint16x8_to_private(a), a_ = simde_uint16x8_to_private(a),
b_ = simde_uint16x8_to_private(b); b_ = simde_uint16x8_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmacc_vx_u16m1(a_.sv128 , c , b_.sv128 , 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -310,7 +329,9 @@ simde_vmlaq_n_u32(simde_uint32x4_t a, simde_uint32x4_t b, uint32_t c) { ...@@ -310,7 +329,9 @@ simde_vmlaq_n_u32(simde_uint32x4_t a, simde_uint32x4_t b, uint32_t c) {
a_ = simde_uint32x4_to_private(a), a_ = simde_uint32x4_to_private(a),
b_ = simde_uint32x4_to_private(b); b_ = simde_uint32x4_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vmacc_vx_u32m1(a_.sv128 , c , b_.sv128 , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = (b_.values * c) + a_.values; r_.values = (b_.values * c) + a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
......
arm/neon/mlal.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLAL_H) #if !defined(SIMDE_ARM_NEON_MLAL_H)
...@@ -41,6 +42,15 @@ simde_int16x8_t ...@@ -41,6 +42,15 @@ simde_int16x8_t
simde_vmlal_s8(simde_int16x8_t a, simde_int8x8_t b, simde_int8x8_t c) { simde_vmlal_s8(simde_int16x8_t a, simde_int8x8_t b, simde_int8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_s8(a, b, c); return vmlal_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private r_;
simde_int16x8_private a_ = simde_int16x8_to_private(a);
simde_int8x8_private b_ = simde_int8x8_to_private(b);
simde_int8x8_private c_ = simde_int8x8_to_private(c);
vint8mf2_t vb = __riscv_vlmul_trunc_v_i8m1_i8mf2 (b_.sv64);
vint8mf2_t vc = __riscv_vlmul_trunc_v_i8m1_i8mf2 (c_.sv64);
r_.sv128 = __riscv_vwmacc_vv_i16m1(a_.sv128 , vb , vc , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vmlaq_s16(a, simde_vmovl_s8(b), simde_vmovl_s8(c)); return simde_vmlaq_s16(a, simde_vmovl_s8(b), simde_vmovl_s8(c));
#endif #endif
...@@ -55,6 +65,15 @@ simde_int32x4_t ...@@ -55,6 +65,15 @@ simde_int32x4_t
simde_vmlal_s16(simde_int32x4_t a, simde_int16x4_t b, simde_int16x4_t c) { simde_vmlal_s16(simde_int32x4_t a, simde_int16x4_t b, simde_int16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_s16(a, b, c); return vmlal_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x4_private b_ = simde_int16x4_to_private(b);
simde_int16x4_private c_ = simde_int16x4_to_private(c);
vint16mf2_t vb = __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv64);
vint16mf2_t vc = __riscv_vlmul_trunc_v_i16m1_i16mf2 (c_.sv64);
r_.sv128 = __riscv_vwmacc_vv_i32m1(a_.sv128 , vb , vc , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vmlaq_s32(a, simde_vmovl_s16(b), simde_vmovl_s16(c)); return simde_vmlaq_s32(a, simde_vmovl_s16(b), simde_vmovl_s16(c));
#endif #endif
...@@ -69,6 +88,15 @@ simde_int64x2_t ...@@ -69,6 +88,15 @@ simde_int64x2_t
simde_vmlal_s32(simde_int64x2_t a, simde_int32x2_t b, simde_int32x2_t c) { simde_vmlal_s32(simde_int64x2_t a, simde_int32x2_t b, simde_int32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_s32(a, b, c); return vmlal_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x2_private b_ = simde_int32x2_to_private(b);
simde_int32x2_private c_ = simde_int32x2_to_private(c);
vint32mf2_t vb = __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv64);
vint32mf2_t vc = __riscv_vlmul_trunc_v_i32m1_i32mf2 (c_.sv64);
r_.sv128 = __riscv_vwmacc_vv_i64m1(a_.sv128 , vb , vc , 2);
return simde_int64x2_from_private(r_);
#else #else
simde_int64x2_private simde_int64x2_private
r_, r_,
...@@ -98,6 +126,15 @@ simde_uint16x8_t ...@@ -98,6 +126,15 @@ simde_uint16x8_t
simde_vmlal_u8(simde_uint16x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) { simde_vmlal_u8(simde_uint16x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_u8(a, b, c); return vmlal_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private r_;
simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
simde_uint8x8_private b_ = simde_uint8x8_to_private(b);
simde_uint8x8_private c_ = simde_uint8x8_to_private(c);
vuint8mf2_t vb = __riscv_vlmul_trunc_v_u8m1_u8mf2 (b_.sv64);
vuint8mf2_t vc = __riscv_vlmul_trunc_v_u8m1_u8mf2 (c_.sv64);
r_.sv128 = __riscv_vwmaccu_vv_u16m1(a_.sv128 , vb , vc , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vmlaq_u16(a, simde_vmovl_u8(b), simde_vmovl_u8(c)); return simde_vmlaq_u16(a, simde_vmovl_u8(b), simde_vmovl_u8(c));
#endif #endif
...@@ -112,6 +149,15 @@ simde_uint32x4_t ...@@ -112,6 +149,15 @@ simde_uint32x4_t
simde_vmlal_u16(simde_uint32x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) { simde_vmlal_u16(simde_uint32x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_u16(a, b, c); return vmlal_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x4_private b_ = simde_uint16x4_to_private(b);
simde_uint16x4_private c_ = simde_uint16x4_to_private(c);
vuint16mf2_t vb = __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv64);
vuint16mf2_t vc = __riscv_vlmul_trunc_v_u16m1_u16mf2 (c_.sv64);
r_.sv128 = __riscv_vwmaccu_vv_u32m1(a_.sv128 , vb , vc , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vmlaq_u32(a, simde_vmovl_u16(b), simde_vmovl_u16(c)); return simde_vmlaq_u32(a, simde_vmovl_u16(b), simde_vmovl_u16(c));
#endif #endif
...@@ -126,6 +172,15 @@ simde_uint64x2_t ...@@ -126,6 +172,15 @@ simde_uint64x2_t
simde_vmlal_u32(simde_uint64x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) { simde_vmlal_u32(simde_uint64x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_u32(a, b, c); return vmlal_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x2_private b_ = simde_uint32x2_to_private(b);
simde_uint32x2_private c_ = simde_uint32x2_to_private(c);
vuint32mf2_t vb = __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv64);
vuint32mf2_t vc = __riscv_vlmul_trunc_v_u32m1_u32mf2 (c_.sv64);
r_.sv128 = __riscv_vwmaccu_vv_u64m1(a_.sv128 , vb , vc , 2);
return simde_uint64x2_from_private(r_);
#else #else
simde_uint64x2_private simde_uint64x2_private
r_, r_,
......
arm/neon/mlal_high.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLAL_HIGH_H) #if !defined(SIMDE_ARM_NEON_MLAL_HIGH_H)
...@@ -41,6 +42,15 @@ simde_int16x8_t ...@@ -41,6 +42,15 @@ simde_int16x8_t
simde_vmlal_high_s8(simde_int16x8_t a, simde_int8x16_t b, simde_int8x16_t c) { simde_vmlal_high_s8(simde_int16x8_t a, simde_int8x16_t b, simde_int8x16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_s8(a, b, c); return vmlal_high_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private r_;
simde_int16x8_private a_ = simde_int16x8_to_private(a);
simde_int8x16_private b_ = simde_int8x16_to_private(b);
simde_int8x16_private c_ = simde_int8x16_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_i8m1(b_.sv128 , 8 , 16);
c_.sv128 = __riscv_vslidedown_vx_i8m1(c_.sv128 , 8 , 16);
r_.sv128 = __riscv_vwmacc_vv_i16m1(a_.sv128 , __riscv_vlmul_trunc_v_i8m1_i8mf2 (b_.sv128) , __riscv_vlmul_trunc_v_i8m1_i8mf2 (c_.sv128) , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vmlaq_s16(a, simde_vmovl_high_s8(b), simde_vmovl_high_s8(c)); return simde_vmlaq_s16(a, simde_vmovl_high_s8(b), simde_vmovl_high_s8(c));
#endif #endif
...@@ -55,6 +65,15 @@ simde_int32x4_t ...@@ -55,6 +65,15 @@ simde_int32x4_t
simde_vmlal_high_s16(simde_int32x4_t a, simde_int16x8_t b, simde_int16x8_t c) { simde_vmlal_high_s16(simde_int32x4_t a, simde_int16x8_t b, simde_int16x8_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_s16(a, b, c); return vmlal_high_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x8_private b_ = simde_int16x8_to_private(b);
simde_int16x8_private c_ = simde_int16x8_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_i16m1(b_.sv128 , 4 , 8);
c_.sv128 = __riscv_vslidedown_vx_i16m1(c_.sv128 , 4 , 8);
r_.sv128 = __riscv_vwmacc_vv_i32m1(a_.sv128 , __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv128) , __riscv_vlmul_trunc_v_i16m1_i16mf2 (c_.sv128) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vmlaq_s32(a, simde_vmovl_high_s16(b), simde_vmovl_high_s16(c)); return simde_vmlaq_s32(a, simde_vmovl_high_s16(b), simde_vmovl_high_s16(c));
#endif #endif
...@@ -69,6 +88,15 @@ simde_int64x2_t ...@@ -69,6 +88,15 @@ simde_int64x2_t
simde_vmlal_high_s32(simde_int64x2_t a, simde_int32x4_t b, simde_int32x4_t c) { simde_vmlal_high_s32(simde_int64x2_t a, simde_int32x4_t b, simde_int32x4_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_s32(a, b, c); return vmlal_high_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x4_private b_ = simde_int32x4_to_private(b);
simde_int32x4_private c_ = simde_int32x4_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_i32m1(b_.sv128 , 2, 4);
c_.sv128 = __riscv_vslidedown_vx_i32m1(c_.sv128 , 2, 4);
r_.sv128 = __riscv_vwmacc_vv_i64m1(a_.sv128 , __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv128) , __riscv_vlmul_trunc_v_i32m1_i32mf2 (c_.sv128) , 2);
return simde_int64x2_from_private(r_);
#else #else
simde_int64x2_private simde_int64x2_private
r_, r_,
...@@ -98,6 +126,15 @@ simde_uint16x8_t ...@@ -98,6 +126,15 @@ simde_uint16x8_t
simde_vmlal_high_u8(simde_uint16x8_t a, simde_uint8x16_t b, simde_uint8x16_t c) { simde_vmlal_high_u8(simde_uint16x8_t a, simde_uint8x16_t b, simde_uint8x16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_u8(a, b, c); return vmlal_high_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private r_;
simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
simde_uint8x16_private b_ = simde_uint8x16_to_private(b);
simde_uint8x16_private c_ = simde_uint8x16_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_u8m1(b_.sv128 , 8 , 16);
c_.sv128 = __riscv_vslidedown_vx_u8m1(c_.sv128 , 8 , 16);
r_.sv128 = __riscv_vwmaccu_vv_u16m1(a_.sv128 , __riscv_vlmul_trunc_v_u8m1_u8mf2 (b_.sv128) , __riscv_vlmul_trunc_v_u8m1_u8mf2 (c_.sv128) , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vmlaq_u16(a, simde_vmovl_high_u8(b), simde_vmovl_high_u8(c)); return simde_vmlaq_u16(a, simde_vmovl_high_u8(b), simde_vmovl_high_u8(c));
#endif #endif
...@@ -112,6 +149,15 @@ simde_uint32x4_t ...@@ -112,6 +149,15 @@ simde_uint32x4_t
simde_vmlal_high_u16(simde_uint32x4_t a, simde_uint16x8_t b, simde_uint16x8_t c) { simde_vmlal_high_u16(simde_uint32x4_t a, simde_uint16x8_t b, simde_uint16x8_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_u16(a, b, c); return vmlal_high_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x8_private b_ = simde_uint16x8_to_private(b);
simde_uint16x8_private c_ = simde_uint16x8_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_u16m1(b_.sv128 , 4 , 8);
c_.sv128 = __riscv_vslidedown_vx_u16m1(c_.sv128 , 4 , 8);
r_.sv128 = __riscv_vwmaccu_vv_u32m1(a_.sv128 , __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv128) , __riscv_vlmul_trunc_v_u16m1_u16mf2 (c_.sv128) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vmlaq_u32(a, simde_vmovl_high_u16(b), simde_vmovl_high_u16(c)); return simde_vmlaq_u32(a, simde_vmovl_high_u16(b), simde_vmovl_high_u16(c));
#endif #endif
...@@ -126,6 +172,15 @@ simde_uint64x2_t ...@@ -126,6 +172,15 @@ simde_uint64x2_t
simde_vmlal_high_u32(simde_uint64x2_t a, simde_uint32x4_t b, simde_uint32x4_t c) { simde_vmlal_high_u32(simde_uint64x2_t a, simde_uint32x4_t b, simde_uint32x4_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_u32(a, b, c); return vmlal_high_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x4_private b_ = simde_uint32x4_to_private(b);
simde_uint32x4_private c_ = simde_uint32x4_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_u32m1(b_.sv128 , 2, 4);
c_.sv128 = __riscv_vslidedown_vx_u32m1(c_.sv128 , 2, 4);
r_.sv128 = __riscv_vwmaccu_vv_u64m1(a_.sv128 , __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv128) , __riscv_vlmul_trunc_v_u32m1_u32mf2 (c_.sv128) , 2);
return simde_uint64x2_from_private(r_);
#else #else
simde_uint64x2_private simde_uint64x2_private
r_, r_,
......
arm/neon/mlal_high_n.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2021 Décio Luiz Gazzoni Filho <decio@decpp.net> * 2021 Décio Luiz Gazzoni Filho <decio@decpp.net>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLAL_HIGH_N_H) #if !defined(SIMDE_ARM_NEON_MLAL_HIGH_N_H)
...@@ -41,6 +42,13 @@ simde_int32x4_t ...@@ -41,6 +42,13 @@ simde_int32x4_t
simde_vmlal_high_n_s16(simde_int32x4_t a, simde_int16x8_t b, int16_t c) { simde_vmlal_high_n_s16(simde_int32x4_t a, simde_int16x8_t b, int16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_n_s16(a, b, c); return vmlal_high_n_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x8_private b_ = simde_int16x8_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_i16m1(b_.sv128 , 4 , 8);
r_.sv128 = __riscv_vwmacc_vx_i32m1(a_.sv128 , c , __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv128) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vmlaq_s32(a, simde_vmovl_high_s16(b), simde_vdupq_n_s32(c)); return simde_vmlaq_s32(a, simde_vmovl_high_s16(b), simde_vdupq_n_s32(c));
#endif #endif
...@@ -55,6 +63,13 @@ simde_int64x2_t ...@@ -55,6 +63,13 @@ simde_int64x2_t
simde_vmlal_high_n_s32(simde_int64x2_t a, simde_int32x4_t b, int32_t c) { simde_vmlal_high_n_s32(simde_int64x2_t a, simde_int32x4_t b, int32_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_n_s32(a, b, c); return vmlal_high_n_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x4_private b_ = simde_int32x4_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_i32m1(b_.sv128 , 2, 4);
r_.sv128 = __riscv_vwmacc_vx_i64m1(a_.sv128 , c , __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv128) , 2);
return simde_int64x2_from_private(r_);
#else #else
simde_int64x2_private simde_int64x2_private
r_, r_,
...@@ -84,6 +99,13 @@ simde_uint32x4_t ...@@ -84,6 +99,13 @@ simde_uint32x4_t
simde_vmlal_high_n_u16(simde_uint32x4_t a, simde_uint16x8_t b, uint16_t c) { simde_vmlal_high_n_u16(simde_uint32x4_t a, simde_uint16x8_t b, uint16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_n_u16(a, b, c); return vmlal_high_n_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x8_private b_ = simde_uint16x8_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_u16m1(b_.sv128 , 4 , 8);
r_.sv128 = __riscv_vwmaccu_vx_u32m1(a_.sv128 , c , __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv128) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vmlaq_u32(a, simde_vmovl_high_u16(b), simde_vdupq_n_u32(c)); return simde_vmlaq_u32(a, simde_vmovl_high_u16(b), simde_vdupq_n_u32(c));
#endif #endif
...@@ -98,6 +120,13 @@ simde_uint64x2_t ...@@ -98,6 +120,13 @@ simde_uint64x2_t
simde_vmlal_high_n_u32(simde_uint64x2_t a, simde_uint32x4_t b, uint32_t c) { simde_vmlal_high_n_u32(simde_uint64x2_t a, simde_uint32x4_t b, uint32_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlal_high_n_u32(a, b, c); return vmlal_high_n_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x4_private b_ = simde_uint32x4_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_u32m1(b_.sv128 , 2, 4);
r_.sv128 = __riscv_vwmaccu_vx_u64m1(a_.sv128 , c , __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv128) , 2);
return simde_uint64x2_from_private(r_);
#else #else
simde_uint64x2_private simde_uint64x2_private
r_, r_,
......
arm/neon/mlal_n.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLAL_N_H) #if !defined(SIMDE_ARM_NEON_MLAL_N_H)
...@@ -41,6 +42,13 @@ simde_int32x4_t ...@@ -41,6 +42,13 @@ simde_int32x4_t
simde_vmlal_n_s16(simde_int32x4_t a, simde_int16x4_t b, int16_t c) { simde_vmlal_n_s16(simde_int32x4_t a, simde_int16x4_t b, int16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_n_s16(a, b, c); return vmlal_n_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x4_private b_ = simde_int16x4_to_private(b);
vint16mf2_t vb = __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv64);
r_.sv128 = __riscv_vwmacc_vx_i32m1(a_.sv128 , c , vb , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vmlaq_s32(a, simde_vmovl_s16(b), simde_vdupq_n_s32(c)); return simde_vmlaq_s32(a, simde_vmovl_s16(b), simde_vdupq_n_s32(c));
#endif #endif
...@@ -55,13 +63,19 @@ simde_int64x2_t ...@@ -55,13 +63,19 @@ simde_int64x2_t
simde_vmlal_n_s32(simde_int64x2_t a, simde_int32x2_t b, int32_t c) { simde_vmlal_n_s32(simde_int64x2_t a, simde_int32x2_t b, int32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_n_s32(a, b, c); return vmlal_n_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x2_private b_ = simde_int32x2_to_private(b);
vint32mf2_t vb = __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv64);
r_.sv128 = __riscv_vwmacc_vx_i64m1(a_.sv128 , c , vb , 2);
return simde_int64x2_from_private(r_);
#else #else
simde_int64x2_private simde_int64x2_private
r_, r_,
a_ = simde_int64x2_to_private(a), a_ = simde_int64x2_to_private(a),
b_ = simde_int64x2_to_private(simde_vmovl_s32(b)), b_ = simde_int64x2_to_private(simde_vmovl_s32(b)),
c_ = simde_int64x2_to_private(simde_vdupq_n_s64(c)); c_ = simde_int64x2_to_private(simde_vdupq_n_s64(c));
#if defined(SIMDE_VECTOR_SUBSCRIPT_OPS) #if defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
r_.values = (b_.values * c_.values) + a_.values; r_.values = (b_.values * c_.values) + a_.values;
#else #else
...@@ -84,6 +98,13 @@ simde_uint32x4_t ...@@ -84,6 +98,13 @@ simde_uint32x4_t
simde_vmlal_n_u16(simde_uint32x4_t a, simde_uint16x4_t b, uint16_t c) { simde_vmlal_n_u16(simde_uint32x4_t a, simde_uint16x4_t b, uint16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_n_u16(a, b, c); return vmlal_n_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x4_private b_ = simde_uint16x4_to_private(b);
vuint16mf2_t vb = __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv64);
r_.sv128 = __riscv_vwmaccu_vx_u32m1(a_.sv128 , c , vb , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vmlaq_u32(a, simde_vmovl_u16(b), simde_vdupq_n_u32(c)); return simde_vmlaq_u32(a, simde_vmovl_u16(b), simde_vdupq_n_u32(c));
#endif #endif
...@@ -98,6 +119,13 @@ simde_uint64x2_t ...@@ -98,6 +119,13 @@ simde_uint64x2_t
simde_vmlal_n_u32(simde_uint64x2_t a, simde_uint32x2_t b, uint32_t c) { simde_vmlal_n_u32(simde_uint64x2_t a, simde_uint32x2_t b, uint32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlal_n_u32(a, b, c); return vmlal_n_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x2_private b_ = simde_uint32x2_to_private(b);
vuint32mf2_t vb = __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv64);
r_.sv128 = __riscv_vwmaccu_vx_u64m1(a_.sv128 , c , vb , 2);
return simde_uint64x2_from_private(r_);
#else #else
simde_uint64x2_private simde_uint64x2_private
r_, r_,
......
arm/neon/mls.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLS_H) #if !defined(SIMDE_ARM_NEON_MLS_H)
...@@ -39,6 +40,14 @@ simde_float32x2_t ...@@ -39,6 +40,14 @@ simde_float32x2_t
simde_vmls_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) { simde_vmls_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_f32(a, b, c); return vmls_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x2_private
r_,
a_ = simde_float32x2_to_private(a),
b_ = simde_float32x2_to_private(b),
c_ = simde_float32x2_to_private(c);
r_.sv64 = __riscv_vfnmsac_vv_f32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_float32x2_from_private(r_);
#else #else
return simde_vsub_f32(a, simde_vmul_f32(b, c)); return simde_vsub_f32(a, simde_vmul_f32(b, c));
#endif #endif
...@@ -53,6 +62,14 @@ simde_float64x1_t ...@@ -53,6 +62,14 @@ simde_float64x1_t
simde_vmls_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) { simde_vmls_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64x1_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmls_f64(a, b, c); return vmls_f64(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float64x1_private
r_,
a_ = simde_float64x1_to_private(a),
b_ = simde_float64x1_to_private(b),
c_ = simde_float64x1_to_private(c);
r_.sv64 = __riscv_vfnmsac_vv_f64m1(a_.sv64 , b_.sv64 , c_.sv64 , 1);
return simde_float64x1_from_private(r_);
#else #else
return simde_vsub_f64(a, simde_vmul_f64(b, c)); return simde_vsub_f64(a, simde_vmul_f64(b, c));
#endif #endif
...@@ -67,6 +84,14 @@ simde_int8x8_t ...@@ -67,6 +84,14 @@ simde_int8x8_t
simde_vmls_s8(simde_int8x8_t a, simde_int8x8_t b, simde_int8x8_t c) { simde_vmls_s8(simde_int8x8_t a, simde_int8x8_t b, simde_int8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_s8(a, b, c); return vmls_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int8x8_private
r_,
a_ = simde_int8x8_to_private(a),
b_ = simde_int8x8_to_private(b),
c_ = simde_int8x8_to_private(c);
r_.sv64 = __riscv_vnmsac_vv_i8m1(a_.sv64 , b_.sv64 , c_.sv64 , 8);
return simde_int8x8_from_private(r_);
#else #else
return simde_vsub_s8(a, simde_vmul_s8(b, c)); return simde_vsub_s8(a, simde_vmul_s8(b, c));
#endif #endif
...@@ -81,6 +106,14 @@ simde_int16x4_t ...@@ -81,6 +106,14 @@ simde_int16x4_t
simde_vmls_s16(simde_int16x4_t a, simde_int16x4_t b, simde_int16x4_t c) { simde_vmls_s16(simde_int16x4_t a, simde_int16x4_t b, simde_int16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_s16(a, b, c); return vmls_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x4_private
r_,
a_ = simde_int16x4_to_private(a),
b_ = simde_int16x4_to_private(b),
c_ = simde_int16x4_to_private(c);
r_.sv64 = __riscv_vnmsac_vv_i16m1(a_.sv64 , b_.sv64 , c_.sv64 , 4);
return simde_int16x4_from_private(r_);
#else #else
return simde_vsub_s16(a, simde_vmul_s16(b, c)); return simde_vsub_s16(a, simde_vmul_s16(b, c));
#endif #endif
...@@ -95,6 +128,14 @@ simde_int32x2_t ...@@ -95,6 +128,14 @@ simde_int32x2_t
simde_vmls_s32(simde_int32x2_t a, simde_int32x2_t b, simde_int32x2_t c) { simde_vmls_s32(simde_int32x2_t a, simde_int32x2_t b, simde_int32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_s32(a, b, c); return vmls_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x2_private
r_,
a_ = simde_int32x2_to_private(a),
b_ = simde_int32x2_to_private(b),
c_ = simde_int32x2_to_private(c);
r_.sv64 = __riscv_vnmsac_vv_i32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_int32x2_from_private(r_);
#else #else
return simde_vsub_s32(a, simde_vmul_s32(b, c)); return simde_vsub_s32(a, simde_vmul_s32(b, c));
#endif #endif
...@@ -109,6 +150,14 @@ simde_uint8x8_t ...@@ -109,6 +150,14 @@ simde_uint8x8_t
simde_vmls_u8(simde_uint8x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) { simde_vmls_u8(simde_uint8x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_u8(a, b, c); return vmls_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint8x8_private
r_,
a_ = simde_uint8x8_to_private(a),
b_ = simde_uint8x8_to_private(b),
c_ = simde_uint8x8_to_private(c);
r_.sv64 = __riscv_vnmsac_vv_u8m1(a_.sv64 , b_.sv64 , c_.sv64 , 8);
return simde_uint8x8_from_private(r_);
#else #else
return simde_vsub_u8(a, simde_vmul_u8(b, c)); return simde_vsub_u8(a, simde_vmul_u8(b, c));
#endif #endif
...@@ -123,6 +172,14 @@ simde_uint16x4_t ...@@ -123,6 +172,14 @@ simde_uint16x4_t
simde_vmls_u16(simde_uint16x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) { simde_vmls_u16(simde_uint16x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_u16(a, b, c); return vmls_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x4_private
r_,
a_ = simde_uint16x4_to_private(a),
b_ = simde_uint16x4_to_private(b),
c_ = simde_uint16x4_to_private(c);
r_.sv64 = __riscv_vnmsac_vv_u16m1(a_.sv64 , b_.sv64 , c_.sv64 , 4);
return simde_uint16x4_from_private(r_);
#else #else
return simde_vsub_u16(a, simde_vmul_u16(b, c)); return simde_vsub_u16(a, simde_vmul_u16(b, c));
#endif #endif
...@@ -137,6 +194,14 @@ simde_uint32x2_t ...@@ -137,6 +194,14 @@ simde_uint32x2_t
simde_vmls_u32(simde_uint32x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) { simde_vmls_u32(simde_uint32x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_u32(a, b, c); return vmls_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x2_private
r_,
a_ = simde_uint32x2_to_private(a),
b_ = simde_uint32x2_to_private(b),
c_ = simde_uint32x2_to_private(c);
r_.sv64 = __riscv_vnmsac_vv_u32m1(a_.sv64 , b_.sv64 , c_.sv64 , 2);
return simde_uint32x2_from_private(r_);
#else #else
return simde_vsub_u32(a, simde_vmul_u32(b, c)); return simde_vsub_u32(a, simde_vmul_u32(b, c));
#endif #endif
...@@ -151,13 +216,19 @@ simde_float32x4_t ...@@ -151,13 +216,19 @@ simde_float32x4_t
simde_vmlsq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) { simde_vmlsq_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_f32(a, b, c); return vmlsq_f32(a, b, c);
#elif defined(SIMDE_X86_FMA_NATIVE) #elif defined(SIMDE_X86_FMA_NATIVE) || defined(SIMDE_RISCV_V_NATIVE)
simde_float32x4_private simde_float32x4_private
r_, r_,
a_ = simde_float32x4_to_private(a), a_ = simde_float32x4_to_private(a),
b_ = simde_float32x4_to_private(b), b_ = simde_float32x4_to_private(b),
c_ = simde_float32x4_to_private(c); c_ = simde_float32x4_to_private(c);
#if defined(SIMDE_X86_FMA_NATIVE)
r_.m128 = _mm_fnmadd_ps(b_.m128, c_.m128, a_.m128); r_.m128 = _mm_fnmadd_ps(b_.m128, c_.m128, a_.m128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfnmsac_vv_f32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
#endif
return simde_float32x4_from_private(r_); return simde_float32x4_from_private(r_);
#else #else
return simde_vsubq_f32(a, simde_vmulq_f32(b, c)); return simde_vsubq_f32(a, simde_vmulq_f32(b, c));
...@@ -173,13 +244,19 @@ simde_float64x2_t ...@@ -173,13 +244,19 @@ simde_float64x2_t
simde_vmlsq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) { simde_vmlsq_f64(simde_float64x2_t a, simde_float64x2_t b, simde_float64x2_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsq_f64(a, b, c); return vmlsq_f64(a, b, c);
#elif defined(SIMDE_X86_FMA_NATIVE) #elif defined(SIMDE_X86_FMA_NATIVE) || defined(SIMDE_X86_FMA_NATIVE)
simde_float64x2_private simde_float64x2_private
r_, r_,
a_ = simde_float64x2_to_private(a), a_ = simde_float64x2_to_private(a),
b_ = simde_float64x2_to_private(b), b_ = simde_float64x2_to_private(b),
c_ = simde_float64x2_to_private(c); c_ = simde_float64x2_to_private(c);
#if defined(SIMDE_X86_FMA_NATIVE)
r_.m128d = _mm_fnmadd_pd(b_.m128d, c_.m128d, a_.m128d); r_.m128d = _mm_fnmadd_pd(b_.m128d, c_.m128d, a_.m128d);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfnmsac_vv_f64m1(a_.sv128 , b_.sv128 , c_.sv128 , 2);
#endif
return simde_float64x2_from_private(r_); return simde_float64x2_from_private(r_);
#else #else
return simde_vsubq_f64(a, simde_vmulq_f64(b, c)); return simde_vsubq_f64(a, simde_vmulq_f64(b, c));
...@@ -195,6 +272,14 @@ simde_int8x16_t ...@@ -195,6 +272,14 @@ simde_int8x16_t
simde_vmlsq_s8(simde_int8x16_t a, simde_int8x16_t b, simde_int8x16_t c) { simde_vmlsq_s8(simde_int8x16_t a, simde_int8x16_t b, simde_int8x16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_s8(a, b, c); return vmlsq_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int8x16_private
r_,
a_ = simde_int8x16_to_private(a),
b_ = simde_int8x16_to_private(b),
c_ = simde_int8x16_to_private(c);
r_.sv128 = __riscv_vnmsac_vv_i8m1(a_.sv128 , b_.sv128 , c_.sv128 , 16);
return simde_int8x16_from_private(r_);
#else #else
return simde_vsubq_s8(a, simde_vmulq_s8(b, c)); return simde_vsubq_s8(a, simde_vmulq_s8(b, c));
#endif #endif
...@@ -209,6 +294,14 @@ simde_int16x8_t ...@@ -209,6 +294,14 @@ simde_int16x8_t
simde_vmlsq_s16(simde_int16x8_t a, simde_int16x8_t b, simde_int16x8_t c) { simde_vmlsq_s16(simde_int16x8_t a, simde_int16x8_t b, simde_int16x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_s16(a, b, c); return vmlsq_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private
r_,
a_ = simde_int16x8_to_private(a),
b_ = simde_int16x8_to_private(b),
c_ = simde_int16x8_to_private(c);
r_.sv128 = __riscv_vnmsac_vv_i16m1(a_.sv128 , b_.sv128 , c_.sv128 , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vsubq_s16(a, simde_vmulq_s16(b, c)); return simde_vsubq_s16(a, simde_vmulq_s16(b, c));
#endif #endif
...@@ -223,6 +316,14 @@ simde_int32x4_t ...@@ -223,6 +316,14 @@ simde_int32x4_t
simde_vmlsq_s32(simde_int32x4_t a, simde_int32x4_t b, simde_int32x4_t c) { simde_vmlsq_s32(simde_int32x4_t a, simde_int32x4_t b, simde_int32x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_s32(a, b, c); return vmlsq_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private
r_,
a_ = simde_int32x4_to_private(a),
b_ = simde_int32x4_to_private(b),
c_ = simde_int32x4_to_private(c);
r_.sv128 = __riscv_vnmsac_vv_i32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vsubq_s32(a, simde_vmulq_s32(b, c)); return simde_vsubq_s32(a, simde_vmulq_s32(b, c));
#endif #endif
...@@ -237,6 +338,14 @@ simde_uint8x16_t ...@@ -237,6 +338,14 @@ simde_uint8x16_t
simde_vmlsq_u8(simde_uint8x16_t a, simde_uint8x16_t b, simde_uint8x16_t c) { simde_vmlsq_u8(simde_uint8x16_t a, simde_uint8x16_t b, simde_uint8x16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_u8(a, b, c); return vmlsq_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint8x16_private
r_,
a_ = simde_uint8x16_to_private(a),
b_ = simde_uint8x16_to_private(b),
c_ = simde_uint8x16_to_private(c);
r_.sv128 = __riscv_vnmsac_vv_u8m1(a_.sv128 , b_.sv128 , c_.sv128 , 16);
return simde_uint8x16_from_private(r_);
#else #else
return simde_vsubq_u8(a, simde_vmulq_u8(b, c)); return simde_vsubq_u8(a, simde_vmulq_u8(b, c));
#endif #endif
...@@ -251,6 +360,14 @@ simde_uint16x8_t ...@@ -251,6 +360,14 @@ simde_uint16x8_t
simde_vmlsq_u16(simde_uint16x8_t a, simde_uint16x8_t b, simde_uint16x8_t c) { simde_vmlsq_u16(simde_uint16x8_t a, simde_uint16x8_t b, simde_uint16x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_u16(a, b, c); return vmlsq_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private
r_,
a_ = simde_uint16x8_to_private(a),
b_ = simde_uint16x8_to_private(b),
c_ = simde_uint16x8_to_private(c);
r_.sv128 = __riscv_vnmsac_vv_u16m1(a_.sv128 , b_.sv128 , c_.sv128 , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vsubq_u16(a, simde_vmulq_u16(b, c)); return simde_vsubq_u16(a, simde_vmulq_u16(b, c));
#endif #endif
...@@ -265,6 +382,14 @@ simde_uint32x4_t ...@@ -265,6 +382,14 @@ simde_uint32x4_t
simde_vmlsq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c) { simde_vmlsq_u32(simde_uint32x4_t a, simde_uint32x4_t b, simde_uint32x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_u32(a, b, c); return vmlsq_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private
r_,
a_ = simde_uint32x4_to_private(a),
b_ = simde_uint32x4_to_private(b),
c_ = simde_uint32x4_to_private(c);
r_.sv128 = __riscv_vnmsac_vv_u32m1(a_.sv128 , b_.sv128 , c_.sv128 , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vsubq_u32(a, simde_vmulq_u32(b, c)); return simde_vsubq_u32(a, simde_vmulq_u32(b, c));
#endif #endif
......
arm/neon/mls_n.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLS_N_H) #if !defined(SIMDE_ARM_NEON_MLS_N_H)
...@@ -40,6 +41,13 @@ simde_float32x2_t ...@@ -40,6 +41,13 @@ simde_float32x2_t
simde_vmls_n_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32 c) { simde_vmls_n_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32 c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_n_f32(a, b, c); return vmls_n_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_float32x2_private
r_,
a_ = simde_float32x2_to_private(a),
b_ = simde_float32x2_to_private(b);
r_.sv64 = __riscv_vfnmsac_vf_f32m1(a_.sv64 , c , b_.sv64 , 2);
return simde_float32x2_from_private(r_);
#else #else
return simde_vmls_f32(a, b, simde_vdup_n_f32(c)); return simde_vmls_f32(a, b, simde_vdup_n_f32(c));
#endif #endif
...@@ -54,6 +62,13 @@ simde_int16x4_t ...@@ -54,6 +62,13 @@ simde_int16x4_t
simde_vmls_n_s16(simde_int16x4_t a, simde_int16x4_t b, int16_t c) { simde_vmls_n_s16(simde_int16x4_t a, simde_int16x4_t b, int16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_n_s16(a, b, c); return vmls_n_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x4_private
r_,
a_ = simde_int16x4_to_private(a),
b_ = simde_int16x4_to_private(b);
r_.sv64 = __riscv_vnmsac_vx_i16m1(a_.sv64 , c , b_.sv64 , 4);
return simde_int16x4_from_private(r_);
#else #else
return simde_vmls_s16(a, b, simde_vdup_n_s16(c)); return simde_vmls_s16(a, b, simde_vdup_n_s16(c));
#endif #endif
...@@ -68,6 +83,13 @@ simde_int32x2_t ...@@ -68,6 +83,13 @@ simde_int32x2_t
simde_vmls_n_s32(simde_int32x2_t a, simde_int32x2_t b, int32_t c) { simde_vmls_n_s32(simde_int32x2_t a, simde_int32x2_t b, int32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_n_s32(a, b, c); return vmls_n_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x2_private
r_,
a_ = simde_int32x2_to_private(a),
b_ = simde_int32x2_to_private(b);
r_.sv64 = __riscv_vnmsac_vx_i32m1(a_.sv64 , c , b_.sv64 , 2);
return simde_int32x2_from_private(r_);
#else #else
return simde_vmls_s32(a, b, simde_vdup_n_s32(c)); return simde_vmls_s32(a, b, simde_vdup_n_s32(c));
#endif #endif
...@@ -82,6 +104,13 @@ simde_uint16x4_t ...@@ -82,6 +104,13 @@ simde_uint16x4_t
simde_vmls_n_u16(simde_uint16x4_t a, simde_uint16x4_t b, uint16_t c) { simde_vmls_n_u16(simde_uint16x4_t a, simde_uint16x4_t b, uint16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_n_u16(a, b, c); return vmls_n_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_uint16x4_private
r_,
a_ = simde_uint16x4_to_private(a),
b_ = simde_uint16x4_to_private(b);
r_.sv64 = __riscv_vnmsac_vx_u16m1(a_.sv64 , c , b_.sv64 , 4);
return simde_uint16x4_from_private(r_);
#else #else
return simde_vmls_u16(a, b, simde_vdup_n_u16(c)); return simde_vmls_u16(a, b, simde_vdup_n_u16(c));
#endif #endif
...@@ -96,6 +125,13 @@ simde_uint32x2_t ...@@ -96,6 +125,13 @@ simde_uint32x2_t
simde_vmls_n_u32(simde_uint32x2_t a, simde_uint32x2_t b, uint32_t c) { simde_vmls_n_u32(simde_uint32x2_t a, simde_uint32x2_t b, uint32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmls_n_u32(a, b, c); return vmls_n_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_uint32x2_private
r_,
a_ = simde_uint32x2_to_private(a),
b_ = simde_uint32x2_to_private(b);
r_.sv64 = __riscv_vnmsac_vx_u32m1(a_.sv64 , c , b_.sv64 , 2);
return simde_uint32x2_from_private(r_);
#else #else
return simde_vmls_u32(a, b, simde_vdup_n_u32(c)); return simde_vmls_u32(a, b, simde_vdup_n_u32(c));
#endif #endif
...@@ -110,6 +146,13 @@ simde_float32x4_t ...@@ -110,6 +146,13 @@ simde_float32x4_t
simde_vmlsq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32 c) { simde_vmlsq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32 c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_n_f32(a, b, c); return vmlsq_n_f32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_float32x4_private
r_,
a_ = simde_float32x4_to_private(a),
b_ = simde_float32x4_to_private(b);
r_.sv128 = __riscv_vfnmsac_vf_f32m1(a_.sv128 , c , b_.sv128 , 4);
return simde_float32x4_from_private(r_);
#else #else
return simde_vmlsq_f32(a, b, simde_vdupq_n_f32(c)); return simde_vmlsq_f32(a, b, simde_vdupq_n_f32(c));
#endif #endif
...@@ -124,6 +167,13 @@ simde_int16x8_t ...@@ -124,6 +167,13 @@ simde_int16x8_t
simde_vmlsq_n_s16(simde_int16x8_t a, simde_int16x8_t b, int16_t c) { simde_vmlsq_n_s16(simde_int16x8_t a, simde_int16x8_t b, int16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_n_s16(a, b, c); return vmlsq_n_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private
r_,
a_ = simde_int16x8_to_private(a),
b_ = simde_int16x8_to_private(b);
r_.sv128 = __riscv_vnmsac_vx_i16m1(a_.sv128 , c , b_.sv128 , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vmlsq_s16(a, b, simde_vdupq_n_s16(c)); return simde_vmlsq_s16(a, b, simde_vdupq_n_s16(c));
#endif #endif
...@@ -138,6 +188,13 @@ simde_int32x4_t ...@@ -138,6 +188,13 @@ simde_int32x4_t
simde_vmlsq_n_s32(simde_int32x4_t a, simde_int32x4_t b, int32_t c) { simde_vmlsq_n_s32(simde_int32x4_t a, simde_int32x4_t b, int32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_n_s32(a, b, c); return vmlsq_n_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private
r_,
a_ = simde_int32x4_to_private(a),
b_ = simde_int32x4_to_private(b);
r_.sv128 = __riscv_vnmsac_vx_i32m1(a_.sv128 , c , b_.sv128 , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vmlsq_s32(a, b, simde_vdupq_n_s32(c)); return simde_vmlsq_s32(a, b, simde_vdupq_n_s32(c));
#endif #endif
...@@ -152,6 +209,13 @@ simde_uint16x8_t ...@@ -152,6 +209,13 @@ simde_uint16x8_t
simde_vmlsq_n_u16(simde_uint16x8_t a, simde_uint16x8_t b, uint16_t c) { simde_vmlsq_n_u16(simde_uint16x8_t a, simde_uint16x8_t b, uint16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_n_u16(a, b, c); return vmlsq_n_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private
r_,
a_ = simde_uint16x8_to_private(a),
b_ = simde_uint16x8_to_private(b);
r_.sv128 = __riscv_vnmsac_vx_u16m1(a_.sv128 , c , b_.sv128 , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vmlsq_u16(a, b, simde_vdupq_n_u16(c)); return simde_vmlsq_u16(a, b, simde_vdupq_n_u16(c));
#endif #endif
...@@ -166,6 +230,13 @@ simde_uint32x4_t ...@@ -166,6 +230,13 @@ simde_uint32x4_t
simde_vmlsq_n_u32(simde_uint32x4_t a, simde_uint32x4_t b, uint32_t c) { simde_vmlsq_n_u32(simde_uint32x4_t a, simde_uint32x4_t b, uint32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsq_n_u32(a, b, c); return vmlsq_n_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private
r_,
a_ = simde_uint32x4_to_private(a),
b_ = simde_uint32x4_to_private(b);
r_.sv128 = __riscv_vnmsac_vx_u32m1(a_.sv128 , c , b_.sv128 , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vmlsq_u32(a, b, simde_vdupq_n_u32(c)); return simde_vmlsq_u32(a, b, simde_vdupq_n_u32(c));
#endif #endif
......
arm/neon/mlsl.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLSL_H) #if !defined(SIMDE_ARM_NEON_MLSL_H)
...@@ -39,6 +40,15 @@ simde_int16x8_t ...@@ -39,6 +40,15 @@ simde_int16x8_t
simde_vmlsl_s8(simde_int16x8_t a, simde_int8x8_t b, simde_int8x8_t c) { simde_vmlsl_s8(simde_int16x8_t a, simde_int8x8_t b, simde_int8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_s8(a, b, c); return vmlsl_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_int16x8_private r_;
simde_int16x8_private a_ = simde_int16x8_to_private(a);
simde_int8x8_private b_ = simde_int8x8_to_private(b);
simde_int8x8_private c_ = simde_int8x8_to_private(c);
vint8mf2_t vb = __riscv_vlmul_trunc_v_i8m1_i8mf2 (b_.sv64);
vint8mf2_t vc = __riscv_vlmul_trunc_v_i8m1_i8mf2 (c_.sv64);
r_.sv128 = __riscv_vsub_vv_i16m1(a_.sv128 , __riscv_vwmul_vv_i16m1(vb , vc , 8) , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vsubq_s16(a, simde_vmull_s8(b, c)); return simde_vsubq_s16(a, simde_vmull_s8(b, c));
#endif #endif
...@@ -53,6 +63,15 @@ simde_int32x4_t ...@@ -53,6 +63,15 @@ simde_int32x4_t
simde_vmlsl_s16(simde_int32x4_t a, simde_int16x4_t b, simde_int16x4_t c) { simde_vmlsl_s16(simde_int32x4_t a, simde_int16x4_t b, simde_int16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_s16(a, b, c); return vmlsl_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x4_private b_ = simde_int16x4_to_private(b);
simde_int16x4_private c_ = simde_int16x4_to_private(c);
vint16mf2_t vb = __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv64);
vint16mf2_t vc = __riscv_vlmul_trunc_v_i16m1_i16mf2 (c_.sv64);
r_.sv128 = __riscv_vsub_vv_i32m1(a_.sv128 , __riscv_vwmul_vv_i32m1(vb , vc , 4) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vsubq_s32(a, simde_vmull_s16(b, c)); return simde_vsubq_s32(a, simde_vmull_s16(b, c));
#endif #endif
...@@ -67,6 +86,15 @@ simde_int64x2_t ...@@ -67,6 +86,15 @@ simde_int64x2_t
simde_vmlsl_s32(simde_int64x2_t a, simde_int32x2_t b, simde_int32x2_t c) { simde_vmlsl_s32(simde_int64x2_t a, simde_int32x2_t b, simde_int32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_s32(a, b, c); return vmlsl_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x2_private b_ = simde_int32x2_to_private(b);
simde_int32x2_private c_ = simde_int32x2_to_private(c);
vint32mf2_t vb = __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv64);
vint32mf2_t vc = __riscv_vlmul_trunc_v_i32m1_i32mf2 (c_.sv64);
r_.sv128 = __riscv_vsub_vv_i64m1(a_.sv128 , __riscv_vwmul_vv_i64m1(vb , vc , 2) , 2);
return simde_int64x2_from_private(r_);
#else #else
return simde_vsubq_s64(a, simde_vmull_s32(b, c)); return simde_vsubq_s64(a, simde_vmull_s32(b, c));
#endif #endif
...@@ -81,6 +109,15 @@ simde_uint16x8_t ...@@ -81,6 +109,15 @@ simde_uint16x8_t
simde_vmlsl_u8(simde_uint16x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) { simde_vmlsl_u8(simde_uint16x8_t a, simde_uint8x8_t b, simde_uint8x8_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_u8(a, b, c); return vmlsl_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_uint16x8_private r_;
simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
simde_uint8x8_private b_ = simde_uint8x8_to_private(b);
simde_uint8x8_private c_ = simde_uint8x8_to_private(c);
vuint8mf2_t vb = __riscv_vlmul_trunc_v_u8m1_u8mf2 (b_.sv64);
vuint8mf2_t vc = __riscv_vlmul_trunc_v_u8m1_u8mf2 (c_.sv64);
r_.sv128 = __riscv_vsub_vv_u16m1(a_.sv128 , __riscv_vwmulu_vv_u16m1(vb , vc , 8) , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vsubq_u16(a, simde_vmull_u8(b, c)); return simde_vsubq_u16(a, simde_vmull_u8(b, c));
#endif #endif
...@@ -95,6 +132,15 @@ simde_uint32x4_t ...@@ -95,6 +132,15 @@ simde_uint32x4_t
simde_vmlsl_u16(simde_uint32x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) { simde_vmlsl_u16(simde_uint32x4_t a, simde_uint16x4_t b, simde_uint16x4_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_u16(a, b, c); return vmlsl_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x4_private b_ = simde_uint16x4_to_private(b);
simde_uint16x4_private c_ = simde_uint16x4_to_private(c);
vuint16mf2_t vb = __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv64);
vuint16mf2_t vc = __riscv_vlmul_trunc_v_u16m1_u16mf2 (c_.sv64);
r_.sv128 = __riscv_vsub_vv_u32m1(a_.sv128 , __riscv_vwmulu_vv_u32m1(vb , vc , 4) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vsubq_u32(a, simde_vmull_u16(b, c)); return simde_vsubq_u32(a, simde_vmull_u16(b, c));
#endif #endif
...@@ -109,6 +155,15 @@ simde_uint64x2_t ...@@ -109,6 +155,15 @@ simde_uint64x2_t
simde_vmlsl_u32(simde_uint64x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) { simde_vmlsl_u32(simde_uint64x2_t a, simde_uint32x2_t b, simde_uint32x2_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_u32(a, b, c); return vmlsl_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE) && (SIMDE_NATURAL_VECTOR_SIZE == 128)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x2_private b_ = simde_uint32x2_to_private(b);
simde_uint32x2_private c_ = simde_uint32x2_to_private(c);
vuint32mf2_t vb = __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv64);
vuint32mf2_t vc = __riscv_vlmul_trunc_v_u32m1_u32mf2 (c_.sv64);
r_.sv128 = __riscv_vsub_vv_u64m1(a_.sv128 , __riscv_vwmulu_vv_u64m1(vb , vc , 2) , 2);
return simde_uint64x2_from_private(r_);
#else #else
return simde_vsubq_u64(a, simde_vmull_u32(b, c)); return simde_vsubq_u64(a, simde_vmull_u32(b, c));
#endif #endif
......
arm/neon/mlsl_high.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLSL_HIGH_H) #if !defined(SIMDE_ARM_NEON_MLSL_HIGH_H)
...@@ -39,6 +40,17 @@ simde_int16x8_t ...@@ -39,6 +40,17 @@ simde_int16x8_t
simde_vmlsl_high_s8(simde_int16x8_t a, simde_int8x16_t b, simde_int8x16_t c) { simde_vmlsl_high_s8(simde_int16x8_t a, simde_int8x16_t b, simde_int8x16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_s8(a, b, c); return vmlsl_high_s8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private r_;
simde_int16x8_private a_ = simde_int16x8_to_private(a);
simde_int8x16_private b_ = simde_int8x16_to_private(b);
simde_int8x16_private c_ = simde_int8x16_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_i8m1(b_.sv128 , 8 , 16);
c_.sv128 = __riscv_vslidedown_vx_i8m1(c_.sv128 , 8 , 16);
vint8mf2_t vb = __riscv_vlmul_trunc_v_i8m1_i8mf2 (b_.sv128);
vint8mf2_t vc = __riscv_vlmul_trunc_v_i8m1_i8mf2 (c_.sv128);
r_.sv128 = __riscv_vsub_vv_i16m1(a_.sv128 , __riscv_vwmul_vv_i16m1(vb , vc , 8) , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vsubq_s16(a, simde_vmull_high_s8(b, c)); return simde_vsubq_s16(a, simde_vmull_high_s8(b, c));
#endif #endif
...@@ -53,6 +65,17 @@ simde_int32x4_t ...@@ -53,6 +65,17 @@ simde_int32x4_t
simde_vmlsl_high_s16(simde_int32x4_t a, simde_int16x8_t b, simde_int16x8_t c) { simde_vmlsl_high_s16(simde_int32x4_t a, simde_int16x8_t b, simde_int16x8_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_s16(a, b, c); return vmlsl_high_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x8_private b_ = simde_int16x8_to_private(b);
simde_int16x8_private c_ = simde_int16x8_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_i16m1(b_.sv128 , 4 , 8);
c_.sv128 = __riscv_vslidedown_vx_i16m1(c_.sv128 , 4 , 8);
vint16mf2_t vb = __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv128);
vint16mf2_t vc = __riscv_vlmul_trunc_v_i16m1_i16mf2 (c_.sv128);
r_.sv128 = __riscv_vsub_vv_i32m1(a_.sv128 , __riscv_vwmul_vv_i32m1(vb , vc , 4) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vsubq_s32(a, simde_vmull_high_s16(b, c)); return simde_vsubq_s32(a, simde_vmull_high_s16(b, c));
#endif #endif
...@@ -67,6 +90,17 @@ simde_int64x2_t ...@@ -67,6 +90,17 @@ simde_int64x2_t
simde_vmlsl_high_s32(simde_int64x2_t a, simde_int32x4_t b, simde_int32x4_t c) { simde_vmlsl_high_s32(simde_int64x2_t a, simde_int32x4_t b, simde_int32x4_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_s32(a, b, c); return vmlsl_high_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x4_private b_ = simde_int32x4_to_private(b);
simde_int32x4_private c_ = simde_int32x4_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_i32m1(b_.sv128 , 2, 4);
c_.sv128 = __riscv_vslidedown_vx_i32m1(c_.sv128 , 2, 4);
vint32mf2_t vb = __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv128);
vint32mf2_t vc = __riscv_vlmul_trunc_v_i32m1_i32mf2 (c_.sv128);
r_.sv128 = __riscv_vsub_vv_i64m1(a_.sv128 , __riscv_vwmul_vv_i64m1(vb , vc , 2) , 2);
return simde_int64x2_from_private(r_);
#else #else
return simde_vsubq_s64(a, simde_vmull_high_s32(b, c)); return simde_vsubq_s64(a, simde_vmull_high_s32(b, c));
#endif #endif
...@@ -81,6 +115,17 @@ simde_uint16x8_t ...@@ -81,6 +115,17 @@ simde_uint16x8_t
simde_vmlsl_high_u8(simde_uint16x8_t a, simde_uint8x16_t b, simde_uint8x16_t c) { simde_vmlsl_high_u8(simde_uint16x8_t a, simde_uint8x16_t b, simde_uint8x16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_u8(a, b, c); return vmlsl_high_u8(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private r_;
simde_uint16x8_private a_ = simde_uint16x8_to_private(a);
simde_uint8x16_private b_ = simde_uint8x16_to_private(b);
simde_uint8x16_private c_ = simde_uint8x16_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_u8m1(b_.sv128 , 8 , 16);
c_.sv128 = __riscv_vslidedown_vx_u8m1(c_.sv128 , 8 , 16);
vuint8mf2_t vb = __riscv_vlmul_trunc_v_u8m1_u8mf2 (b_.sv128);
vuint8mf2_t vc = __riscv_vlmul_trunc_v_u8m1_u8mf2 (c_.sv128);
r_.sv128 = __riscv_vsub_vv_u16m1(a_.sv128 , __riscv_vwmulu_vv_u16m1(vb , vc , 8) , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vsubq_u16(a, simde_vmull_high_u8(b, c)); return simde_vsubq_u16(a, simde_vmull_high_u8(b, c));
#endif #endif
...@@ -95,6 +140,17 @@ simde_uint32x4_t ...@@ -95,6 +140,17 @@ simde_uint32x4_t
simde_vmlsl_high_u16(simde_uint32x4_t a, simde_uint16x8_t b, simde_uint16x8_t c) { simde_vmlsl_high_u16(simde_uint32x4_t a, simde_uint16x8_t b, simde_uint16x8_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_u16(a, b, c); return vmlsl_high_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x8_private b_ = simde_uint16x8_to_private(b);
simde_uint16x8_private c_ = simde_uint16x8_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_u16m1(b_.sv128 , 4 , 8);
c_.sv128 = __riscv_vslidedown_vx_u16m1(c_.sv128 , 4 , 8);
vuint16mf2_t vb = __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv128);
vuint16mf2_t vc = __riscv_vlmul_trunc_v_u16m1_u16mf2 (c_.sv128);
r_.sv128 = __riscv_vsub_vv_u32m1(a_.sv128 , __riscv_vwmulu_vv_u32m1(vb , vc , 4) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vsubq_u32(a, simde_vmull_high_u16(b, c)); return simde_vsubq_u32(a, simde_vmull_high_u16(b, c));
#endif #endif
...@@ -109,6 +165,17 @@ simde_uint64x2_t ...@@ -109,6 +165,17 @@ simde_uint64x2_t
simde_vmlsl_high_u32(simde_uint64x2_t a, simde_uint32x4_t b, simde_uint32x4_t c) { simde_vmlsl_high_u32(simde_uint64x2_t a, simde_uint32x4_t b, simde_uint32x4_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_u32(a, b, c); return vmlsl_high_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x4_private b_ = simde_uint32x4_to_private(b);
simde_uint32x4_private c_ = simde_uint32x4_to_private(c);
b_.sv128 = __riscv_vslidedown_vx_u32m1(b_.sv128 , 2, 4);
c_.sv128 = __riscv_vslidedown_vx_u32m1(c_.sv128 , 2, 4);
vuint32mf2_t vb = __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv128);
vuint32mf2_t vc = __riscv_vlmul_trunc_v_u32m1_u32mf2 (c_.sv128);
r_.sv128 = __riscv_vsub_vv_u64m1(a_.sv128 , __riscv_vwmulu_vv_u64m1(vb , vc , 2) , 2);
return simde_uint64x2_from_private(r_);
#else #else
return simde_vsubq_u64(a, simde_vmull_high_u32(b, c)); return simde_vsubq_u64(a, simde_vmull_high_u32(b, c));
#endif #endif
......
arm/neon/mlsl_high_n.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2021 Décio Luiz Gazzoni Filho <decio@decpp.net> * 2021 Décio Luiz Gazzoni Filho <decio@decpp.net>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLSL_HIGH_N_H) #if !defined(SIMDE_ARM_NEON_MLSL_HIGH_N_H)
...@@ -41,6 +42,14 @@ simde_int32x4_t ...@@ -41,6 +42,14 @@ simde_int32x4_t
simde_vmlsl_high_n_s16(simde_int32x4_t a, simde_int16x8_t b, int16_t c) { simde_vmlsl_high_n_s16(simde_int32x4_t a, simde_int16x8_t b, int16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_n_s16(a, b, c); return vmlsl_high_n_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x8_private b_ = simde_int16x8_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_i16m1(b_.sv128 , 4 , 8);
vint16mf2_t vb = __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv128);
r_.sv128 = __riscv_vsub_vv_i32m1(a_.sv128 , __riscv_vwmul_vx_i32m1(vb , c , 4) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vmlsq_s32(a, simde_vmovl_high_s16(b), simde_vdupq_n_s32(c)); return simde_vmlsq_s32(a, simde_vmovl_high_s16(b), simde_vdupq_n_s32(c));
#endif #endif
...@@ -55,6 +64,14 @@ simde_int64x2_t ...@@ -55,6 +64,14 @@ simde_int64x2_t
simde_vmlsl_high_n_s32(simde_int64x2_t a, simde_int32x4_t b, int32_t c) { simde_vmlsl_high_n_s32(simde_int64x2_t a, simde_int32x4_t b, int32_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_n_s32(a, b, c); return vmlsl_high_n_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x4_private b_ = simde_int32x4_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_i32m1(b_.sv128 , 2, 4);
vint32mf2_t vb = __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv128);
r_.sv128 = __riscv_vsub_vv_i64m1(a_.sv128 , __riscv_vwmul_vx_i64m1(vb , c , 2) , 2);
return simde_int64x2_from_private(r_);
#else #else
simde_int64x2_private simde_int64x2_private
r_, r_,
...@@ -84,6 +101,14 @@ simde_uint32x4_t ...@@ -84,6 +101,14 @@ simde_uint32x4_t
simde_vmlsl_high_n_u16(simde_uint32x4_t a, simde_uint16x8_t b, uint16_t c) { simde_vmlsl_high_n_u16(simde_uint32x4_t a, simde_uint16x8_t b, uint16_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_n_u16(a, b, c); return vmlsl_high_n_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x8_private b_ = simde_uint16x8_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_u16m1(b_.sv128 , 4 , 8);
vuint16mf2_t vb = __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv128);
r_.sv128 = __riscv_vsub_vv_u32m1(a_.sv128 , __riscv_vwmulu_vx_u32m1(vb , c , 4) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vmlsq_u32(a, simde_vmovl_high_u16(b), simde_vdupq_n_u32(c)); return simde_vmlsq_u32(a, simde_vmovl_high_u16(b), simde_vdupq_n_u32(c));
#endif #endif
...@@ -98,6 +123,14 @@ simde_uint64x2_t ...@@ -98,6 +123,14 @@ simde_uint64x2_t
simde_vmlsl_high_n_u32(simde_uint64x2_t a, simde_uint32x4_t b, uint32_t c) { simde_vmlsl_high_n_u32(simde_uint64x2_t a, simde_uint32x4_t b, uint32_t c) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE) #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
return vmlsl_high_n_u32(a, b, c); return vmlsl_high_n_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x4_private b_ = simde_uint32x4_to_private(b);
b_.sv128 = __riscv_vslidedown_vx_u32m1(b_.sv128 , 2, 4);
vuint32mf2_t vb = __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv128);
r_.sv128 = __riscv_vsub_vv_u64m1(a_.sv128 , __riscv_vwmulu_vx_u64m1(vb , c , 2) , 2);
return simde_uint64x2_from_private(r_);
#else #else
simde_uint64x2_private simde_uint64x2_private
r_, r_,
......
arm/neon/mlsl_n.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_MLSL_N_H) #if !defined(SIMDE_ARM_NEON_MLSL_N_H)
...@@ -39,6 +40,13 @@ simde_int32x4_t ...@@ -39,6 +40,13 @@ simde_int32x4_t
simde_vmlsl_n_s16(simde_int32x4_t a, simde_int16x4_t b, int16_t c) { simde_vmlsl_n_s16(simde_int32x4_t a, simde_int16x4_t b, int16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_n_s16(a, b, c); return vmlsl_n_s16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int32x4_private a_ = simde_int32x4_to_private(a);
simde_int16x4_private b_ = simde_int16x4_to_private(b);
vint16mf2_t vb = __riscv_vlmul_trunc_v_i16m1_i16mf2 (b_.sv64);
r_.sv128 = __riscv_vsub_vv_i32m1(a_.sv128 , __riscv_vwmul_vx_i32m1(vb , c , 4) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vsubq_s32(a, simde_vmull_n_s16(b, c)); return simde_vsubq_s32(a, simde_vmull_n_s16(b, c));
#endif #endif
...@@ -53,6 +61,13 @@ simde_int64x2_t ...@@ -53,6 +61,13 @@ simde_int64x2_t
simde_vmlsl_n_s32(simde_int64x2_t a, simde_int32x2_t b, int32_t c) { simde_vmlsl_n_s32(simde_int64x2_t a, simde_int32x2_t b, int32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_n_s32(a, b, c); return vmlsl_n_s32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int64x2_private a_ = simde_int64x2_to_private(a);
simde_int32x2_private b_ = simde_int32x2_to_private(b);
vint32mf2_t vb = __riscv_vlmul_trunc_v_i32m1_i32mf2 (b_.sv64);
r_.sv128 = __riscv_vsub_vv_i64m1(a_.sv128 , __riscv_vwmul_vx_i64m1(vb , c , 2) , 2);
return simde_int64x2_from_private(r_);
#else #else
return simde_vsubq_s64(a, simde_vmull_n_s32(b, c)); return simde_vsubq_s64(a, simde_vmull_n_s32(b, c));
#endif #endif
...@@ -67,6 +82,13 @@ simde_uint32x4_t ...@@ -67,6 +82,13 @@ simde_uint32x4_t
simde_vmlsl_n_u16(simde_uint32x4_t a, simde_uint16x4_t b, uint16_t c) { simde_vmlsl_n_u16(simde_uint32x4_t a, simde_uint16x4_t b, uint16_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_n_u16(a, b, c); return vmlsl_n_u16(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint32x4_private a_ = simde_uint32x4_to_private(a);
simde_uint16x4_private b_ = simde_uint16x4_to_private(b);
vuint16mf2_t vb = __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv64);
r_.sv128 = __riscv_vsub_vv_u32m1(a_.sv128 , __riscv_vwmulu_vx_u32m1(vb , c , 4) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vsubq_u32(a, simde_vmull_n_u16(b, c)); return simde_vsubq_u32(a, simde_vmull_n_u16(b, c));
#endif #endif
...@@ -81,6 +103,13 @@ simde_uint64x2_t ...@@ -81,6 +103,13 @@ simde_uint64x2_t
simde_vmlsl_n_u32(simde_uint64x2_t a, simde_uint32x2_t b, uint32_t c) { simde_vmlsl_n_u32(simde_uint64x2_t a, simde_uint32x2_t b, uint32_t c) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vmlsl_n_u32(a, b, c); return vmlsl_n_u32(a, b, c);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint64x2_private a_ = simde_uint64x2_to_private(a);
simde_uint32x2_private b_ = simde_uint32x2_to_private(b);
vuint32mf2_t vb = __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv64);
r_.sv128 = __riscv_vsub_vv_u64m1(a_.sv128 , __riscv_vwmulu_vx_u64m1(vb , c , 2) , 2);
return simde_uint64x2_from_private(r_);
#else #else
return simde_vsubq_u64(a, simde_vmull_n_u32(b, c)); return simde_vsubq_u64(a, simde_vmull_n_u32(b, c));
#endif #endif
......
arm/neon/qsub.h
View file @ 408d06a3
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
* *
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_QSUB_H) #if !defined(SIMDE_ARM_NEON_QSUB_H)
...@@ -134,6 +135,8 @@ simde_vqsub_s8(simde_int8x8_t a, simde_int8x8_t b) { ...@@ -134,6 +135,8 @@ simde_vqsub_s8(simde_int8x8_t a, simde_int8x8_t b) {
#if defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_subs_pi8(a_.m64, b_.m64); r_.m64 = _mm_subs_pi8(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssub_vv_i8m1(a_.sv64, b_.sv64, 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT8_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT8_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
...@@ -168,6 +171,8 @@ simde_vqsub_s16(simde_int16x4_t a, simde_int16x4_t b) { ...@@ -168,6 +171,8 @@ simde_vqsub_s16(simde_int16x4_t a, simde_int16x4_t b) {
#if defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_subs_pi16(a_.m64, b_.m64); r_.m64 = _mm_subs_pi16(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssub_vv_i16m1(a_.sv64, b_.sv64, 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT16_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT16_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
...@@ -200,7 +205,9 @@ simde_vqsub_s32(simde_int32x2_t a, simde_int32x2_t b) { ...@@ -200,7 +205,9 @@ simde_vqsub_s32(simde_int32x2_t a, simde_int32x2_t b) {
a_ = simde_int32x2_to_private(a), a_ = simde_int32x2_to_private(a),
b_ = simde_int32x2_to_private(b); b_ = simde_int32x2_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssub_vv_i32m1(a_.sv64, b_.sv64, 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT32_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT32_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
const __typeof__(r_.values) saturate = diff_sat ^ diff; const __typeof__(r_.values) saturate = diff_sat ^ diff;
...@@ -232,7 +239,9 @@ simde_vqsub_s64(simde_int64x1_t a, simde_int64x1_t b) { ...@@ -232,7 +239,9 @@ simde_vqsub_s64(simde_int64x1_t a, simde_int64x1_t b) {
a_ = simde_int64x1_to_private(a), a_ = simde_int64x1_to_private(a),
b_ = simde_int64x1_to_private(b); b_ = simde_int64x1_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssub_vv_i64m1(a_.sv64, b_.sv64, 1);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT64_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT64_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
const __typeof__(r_.values) saturate = diff_sat ^ diff; const __typeof__(r_.values) saturate = diff_sat ^ diff;
...@@ -266,6 +275,8 @@ simde_vqsub_u8(simde_uint8x8_t a, simde_uint8x8_t b) { ...@@ -266,6 +275,8 @@ simde_vqsub_u8(simde_uint8x8_t a, simde_uint8x8_t b) {
#if defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_subs_pu8(a_.m64, b_.m64); r_.m64 = _mm_subs_pu8(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssubu_vv_u8m1(a_.sv64, b_.sv64, 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values)); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values));
...@@ -297,6 +308,8 @@ simde_vqsub_u16(simde_uint16x4_t a, simde_uint16x4_t b) { ...@@ -297,6 +308,8 @@ simde_vqsub_u16(simde_uint16x4_t a, simde_uint16x4_t b) {
#if defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_subs_pu16(a_.m64, b_.m64); r_.m64 = _mm_subs_pu16(a_.m64, b_.m64);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssubu_vv_u16m1(a_.sv64, b_.sv64, 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values)); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values));
...@@ -326,7 +339,9 @@ simde_vqsub_u32(simde_uint32x2_t a, simde_uint32x2_t b) { ...@@ -326,7 +339,9 @@ simde_vqsub_u32(simde_uint32x2_t a, simde_uint32x2_t b) {
a_ = simde_uint32x2_to_private(a), a_ = simde_uint32x2_to_private(a),
b_ = simde_uint32x2_to_private(b); b_ = simde_uint32x2_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssubu_vv_u32m1(a_.sv64, b_.sv64, 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values)); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values));
#else #else
...@@ -355,7 +370,9 @@ simde_vqsub_u64(simde_uint64x1_t a, simde_uint64x1_t b) { ...@@ -355,7 +370,9 @@ simde_vqsub_u64(simde_uint64x1_t a, simde_uint64x1_t b) {
a_ = simde_uint64x1_to_private(a), a_ = simde_uint64x1_to_private(a),
b_ = simde_uint64x1_to_private(b); b_ = simde_uint64x1_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vssubu_vv_u64m1(a_.sv64, b_.sv64, 1);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values)); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values));
#else #else
...@@ -390,6 +407,8 @@ simde_vqsubq_s8(simde_int8x16_t a, simde_int8x16_t b) { ...@@ -390,6 +407,8 @@ simde_vqsubq_s8(simde_int8x16_t a, simde_int8x16_t b) {
r_.v128 = wasm_i8x16_sub_sat(a_.v128, b_.v128); r_.v128 = wasm_i8x16_sub_sat(a_.v128, b_.v128);
#elif defined(SIMDE_X86_SSE2_NATIVE) #elif defined(SIMDE_X86_SSE2_NATIVE)
r_.m128i = _mm_subs_epi8(a_.m128i, b_.m128i); r_.m128i = _mm_subs_epi8(a_.m128i, b_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssub_vv_i8m1(a_.sv128 , b_.sv128 , 16);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT8_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT8_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
...@@ -428,6 +447,8 @@ simde_vqsubq_s16(simde_int16x8_t a, simde_int16x8_t b) { ...@@ -428,6 +447,8 @@ simde_vqsubq_s16(simde_int16x8_t a, simde_int16x8_t b) {
r_.v128 = wasm_i16x8_sub_sat(a_.v128, b_.v128); r_.v128 = wasm_i16x8_sub_sat(a_.v128, b_.v128);
#elif defined(SIMDE_X86_SSE2_NATIVE) #elif defined(SIMDE_X86_SSE2_NATIVE)
r_.m128i = _mm_subs_epi16(a_.m128i, b_.m128i); r_.m128i = _mm_subs_epi16(a_.m128i, b_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssub_vv_i16m1(a_.sv128 , b_.sv128 , 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT16_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT16_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
...@@ -479,6 +500,8 @@ simde_vqsubq_s32(simde_int32x4_t a, simde_int32x4_t b) { ...@@ -479,6 +500,8 @@ simde_vqsubq_s32(simde_int32x4_t a, simde_int32x4_t b) {
#else #else
r_.m128i = _mm_xor_si128(diff, _mm_and_si128(t, _mm_srai_epi32(t, 31))); r_.m128i = _mm_xor_si128(diff, _mm_and_si128(t, _mm_srai_epi32(t, 31)));
#endif #endif
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssub_vv_i32m1(a_.sv128 , b_.sv128 , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT32_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT32_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
...@@ -511,7 +534,9 @@ simde_vqsubq_s64(simde_int64x2_t a, simde_int64x2_t b) { ...@@ -511,7 +534,9 @@ simde_vqsubq_s64(simde_int64x2_t a, simde_int64x2_t b) {
a_ = simde_int64x2_to_private(a), a_ = simde_int64x2_to_private(a),
b_ = simde_int64x2_to_private(b); b_ = simde_int64x2_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssub_vv_i64m1(a_.sv128 , b_.sv128 , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT64_MAX); const __typeof__(r_.values) diff_sat = HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (b_.values > a_.values) ^ INT64_MAX);
const __typeof__(r_.values) diff = a_.values - b_.values; const __typeof__(r_.values) diff = a_.values - b_.values;
const __typeof__(r_.values) saturate = diff_sat ^ diff; const __typeof__(r_.values) saturate = diff_sat ^ diff;
...@@ -549,6 +574,8 @@ simde_vqsubq_u8(simde_uint8x16_t a, simde_uint8x16_t b) { ...@@ -549,6 +574,8 @@ simde_vqsubq_u8(simde_uint8x16_t a, simde_uint8x16_t b) {
r_.v128 = wasm_u8x16_sub_sat(a_.v128, b_.v128); r_.v128 = wasm_u8x16_sub_sat(a_.v128, b_.v128);
#elif defined(SIMDE_X86_SSE2_NATIVE) #elif defined(SIMDE_X86_SSE2_NATIVE)
r_.m128i = _mm_subs_epu8(a_.m128i, b_.m128i); r_.m128i = _mm_subs_epu8(a_.m128i, b_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssubu_vv_u8m1(a_.sv128 , b_.sv128 , 16);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values <= a_.values); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values <= a_.values);
...@@ -584,6 +611,8 @@ simde_vqsubq_u16(simde_uint16x8_t a, simde_uint16x8_t b) { ...@@ -584,6 +611,8 @@ simde_vqsubq_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
r_.v128 = wasm_u16x8_sub_sat(a_.v128, b_.v128); r_.v128 = wasm_u16x8_sub_sat(a_.v128, b_.v128);
#elif defined(SIMDE_X86_SSE2_NATIVE) #elif defined(SIMDE_X86_SSE2_NATIVE)
r_.m128i = _mm_subs_epu16(a_.m128i, b_.m128i); r_.m128i = _mm_subs_epu16(a_.m128i, b_.m128i);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssubu_vv_u16m1(a_.sv128 , b_.sv128 , 8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values <= a_.values); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), r_.values <= a_.values);
...@@ -629,6 +658,8 @@ simde_vqsubq_u32(simde_uint32x4_t a, simde_uint32x4_t b) { ...@@ -629,6 +658,8 @@ simde_vqsubq_u32(simde_uint32x4_t a, simde_uint32x4_t b) {
_mm_set1_epi32(~INT32_C(0)) _mm_set1_epi32(~INT32_C(0))
) )
); );
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssubu_vv_u32m1(a_.sv128 , b_.sv128 , 4);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values)); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values));
...@@ -661,7 +692,9 @@ simde_vqsubq_u64(simde_uint64x2_t a, simde_uint64x2_t b) { ...@@ -661,7 +692,9 @@ simde_vqsubq_u64(simde_uint64x2_t a, simde_uint64x2_t b) {
a_ = simde_uint64x2_to_private(a), a_ = simde_uint64x2_to_private(a),
b_ = simde_uint64x2_to_private(b); b_ = simde_uint64x2_to_private(b);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vssubu_vv_u64m1(a_.sv128 , b_.sv128 , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = a_.values - b_.values; r_.values = a_.values - b_.values;
r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values)); r_.values &= HEDLEY_REINTERPRET_CAST(__typeof__(r_.values), (r_.values <= a_.values));
#else #else
......
arm/neon/qtbl.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Christopher Moore <moore@free.fr> * 2020 Christopher Moore <moore@free.fr>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_QTBL_H) #if !defined(SIMDE_ARM_NEON_QTBL_H)
...@@ -55,6 +56,10 @@ simde_vqtbl1_u8(simde_uint8x16_t t, simde_uint8x8_t idx) { ...@@ -55,6 +56,10 @@ simde_vqtbl1_u8(simde_uint8x16_t t, simde_uint8x8_t idx) {
__m128i idx128 = _mm_set1_epi64(idx_.m64); __m128i idx128 = _mm_set1_epi64(idx_.m64);
__m128i r128 = _mm_shuffle_epi8(t_.m128i, _mm_or_si128(idx128, _mm_cmpgt_epi8(idx128, _mm_set1_epi8(15)))); __m128i r128 = _mm_shuffle_epi8(t_.m128i, _mm_or_si128(idx128, _mm_cmpgt_epi8(idx128, _mm_set1_epi8(15))));
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vbool8_t mask = __riscv_vmsgeu_vx_u8m1_b8 (idx_.sv64, 16, 8);
r_.sv64 = __riscv_vrgather_vv_u8m1(t_.sv128 , idx_.sv64 , 8);
r_.sv64 = __riscv_vmerge_vxm_u8m1(r_.sv64, 0, mask, 8);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -108,6 +113,14 @@ simde_vqtbl2_u8(simde_uint8x16x2_t t, simde_uint8x8_t idx) { ...@@ -108,6 +113,14 @@ simde_vqtbl2_u8(simde_uint8x16x2_t t, simde_uint8x8_t idx) {
__m128i r128_1 = _mm_shuffle_epi8(t_[1].m128i, idx128); __m128i r128_1 = _mm_shuffle_epi8(t_[1].m128i, idx128);
__m128i r128 = _mm_blendv_epi8(r128_0, r128_1, _mm_slli_epi32(idx128, 3)); __m128i r128 = _mm_blendv_epi8(r128_0, r128_1, _mm_slli_epi32(idx128, 3));
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m2_t t1 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[0].sv128);
vuint8m2_t t2 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[1].sv128);
vuint8m2_t t_combine = __riscv_vslideup_vx_u8m2(t1 , t2 , 16 , 32);
vuint8m2_t idxm2 = __riscv_vlmul_ext_v_u8m1_u8m2(idx_.sv64);
vbool4_t mask = __riscv_vmsgeu_vx_u8m2_b4 (idxm2, 32, 8);
vuint8m2_t r_tmp = __riscv_vrgather_vv_u8m2(t_combine , idxm2 , 8);
r_.sv64 = __riscv_vlmul_trunc_v_u8m2_u8m1(__riscv_vmerge_vxm_u8m2(r_tmp, 0, mask, 8));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -169,6 +182,16 @@ simde_vqtbl3_u8(simde_uint8x16x3_t t, simde_uint8x8_t idx) { ...@@ -169,6 +182,16 @@ simde_vqtbl3_u8(simde_uint8x16x3_t t, simde_uint8x8_t idx) {
__m128i r128_2 = _mm_shuffle_epi8(t_[2].m128i, idx128); __m128i r128_2 = _mm_shuffle_epi8(t_[2].m128i, idx128);
__m128i r128 = _mm_blendv_epi8(r128_01, r128_2, _mm_slli_epi32(idx128, 2)); __m128i r128 = _mm_blendv_epi8(r128_01, r128_2, _mm_slli_epi32(idx128, 2));
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t2 , t3 , 16 , 48);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 48);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv64);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 48, 8);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 8);
r_.sv64 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vxm_u8m4(r_tmp, 0, mask, 8));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -233,6 +256,18 @@ simde_vqtbl4_u8(simde_uint8x16x4_t t, simde_uint8x8_t idx) { ...@@ -233,6 +256,18 @@ simde_vqtbl4_u8(simde_uint8x16x4_t t, simde_uint8x8_t idx) {
__m128i r128_23 = _mm_blendv_epi8(r128_2, r128_3, idx128_shl3); __m128i r128_23 = _mm_blendv_epi8(r128_2, r128_3, idx128_shl3);
__m128i r128 = _mm_blendv_epi8(r128_01, r128_23, _mm_slli_epi32(idx128, 2)); __m128i r128 = _mm_blendv_epi8(r128_01, r128_23, _mm_slli_epi32(idx128, 2));
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t t4 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[3].sv128);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t3 , t4 , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t2 , t_combine , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 64);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv64);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 64, 8);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 8);
r_.sv64 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vxm_u8m4(r_tmp, 0, mask, 8));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -289,6 +324,10 @@ simde_vqtbl1q_u8(simde_uint8x16_t t, simde_uint8x16_t idx) { ...@@ -289,6 +324,10 @@ simde_vqtbl1q_u8(simde_uint8x16_t t, simde_uint8x16_t idx) {
r_.m128i = _mm_shuffle_epi8(t_.m128i, _mm_or_si128(idx_.m128i, _mm_cmpgt_epi8(idx_.m128i, _mm_set1_epi8(15)))); r_.m128i = _mm_shuffle_epi8(t_.m128i, _mm_or_si128(idx_.m128i, _mm_cmpgt_epi8(idx_.m128i, _mm_set1_epi8(15))));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i8x16_swizzle(t_.v128, idx_.v128); r_.v128 = wasm_i8x16_swizzle(t_.v128, idx_.v128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vbool8_t mask = __riscv_vmsgeu_vx_u8m1_b8 (idx_.sv128, 16, 16);
r_.sv128 = __riscv_vrgather_vv_u8m1(t_.sv128 , idx_.sv128 , 16);
r_.sv128 = __riscv_vmerge_vxm_u8m1(r_.sv128, 0, mask, 16);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -348,6 +387,14 @@ simde_vqtbl2q_u8(simde_uint8x16x2_t t, simde_uint8x16_t idx) { ...@@ -348,6 +387,14 @@ simde_vqtbl2q_u8(simde_uint8x16x2_t t, simde_uint8x16_t idx) {
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_or(wasm_i8x16_swizzle(t_[0].v128, idx_.v128), r_.v128 = wasm_v128_or(wasm_i8x16_swizzle(t_[0].v128, idx_.v128),
wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))); wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16))));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m2_t t1 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[0].sv128);
vuint8m2_t t2 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[1].sv128);
vuint8m2_t t_combine = __riscv_vslideup_vx_u8m2(t1 , t2 , 16 , 32);
vuint8m2_t idxm2 = __riscv_vlmul_ext_v_u8m1_u8m2(idx_.sv128);
vbool4_t mask = __riscv_vmsgeu_vx_u8m2_b4 (idxm2, 32, 16);
vuint8m2_t r_tmp = __riscv_vrgather_vv_u8m2(t_combine , idxm2 , 16);
r_.sv128 = __riscv_vlmul_trunc_v_u8m2_u8m1(__riscv_vmerge_vxm_u8m2(r_tmp, 0, mask, 16));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -418,6 +465,16 @@ simde_vqtbl3q_u8(simde_uint8x16x3_t t, simde_uint8x16_t idx) { ...@@ -418,6 +465,16 @@ simde_vqtbl3q_u8(simde_uint8x16x3_t t, simde_uint8x16_t idx) {
r_.v128 = wasm_v128_or(wasm_v128_or(wasm_i8x16_swizzle(t_[0].v128, idx_.v128), r_.v128 = wasm_v128_or(wasm_v128_or(wasm_i8x16_swizzle(t_[0].v128, idx_.v128),
wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))), wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))),
wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32)))); wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32))));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t2 , t3 , 16 , 48);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 48);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv128);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 48, 16);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 16);
r_.sv128 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vxm_u8m4(r_tmp, 0, mask, 16));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -492,6 +549,18 @@ simde_vqtbl4q_u8(simde_uint8x16x4_t t, simde_uint8x16_t idx) { ...@@ -492,6 +549,18 @@ simde_vqtbl4q_u8(simde_uint8x16x4_t t, simde_uint8x16_t idx) {
wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))), wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))),
wasm_v128_or(wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32))), wasm_v128_or(wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32))),
wasm_i8x16_swizzle(t_[3].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(48))))); wasm_i8x16_swizzle(t_[3].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(48)))));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t t4 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[3].sv128);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t3 , t4 , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t2 , t_combine , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 64);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv128);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 64, 16);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 16);
r_.sv128 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vxm_u8m4(r_tmp, 0, mask, 16));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
......
arm/neon/qtbx.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Christopher Moore <moore@free.fr> * 2020 Christopher Moore <moore@free.fr>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_QTBX_H) #if !defined(SIMDE_ARM_NEON_QTBX_H)
...@@ -58,6 +59,10 @@ simde_vqtbx1_u8(simde_uint8x8_t a, simde_uint8x16_t t, simde_uint8x8_t idx) { ...@@ -58,6 +59,10 @@ simde_vqtbx1_u8(simde_uint8x8_t a, simde_uint8x16_t t, simde_uint8x8_t idx) {
__m128i r128 = _mm_shuffle_epi8(t_.m128i, idx128); __m128i r128 = _mm_shuffle_epi8(t_.m128i, idx128);
r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128); r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128);
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vbool8_t mask = __riscv_vmsgeu_vx_u8m1_b8 (idx_.sv64, 16, 8);
r_.sv64 = __riscv_vrgather_vv_u8m1(t_.sv128 , idx_.sv64 , 8);
r_.sv64 = __riscv_vmerge_vvm_u8m1(r_.sv64, a_.sv64, mask, 8);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -113,6 +118,15 @@ simde_vqtbx2_u8(simde_uint8x8_t a, simde_uint8x16x2_t t, simde_uint8x8_t idx) { ...@@ -113,6 +118,15 @@ simde_vqtbx2_u8(simde_uint8x8_t a, simde_uint8x16x2_t t, simde_uint8x8_t idx) {
__m128i r128 = _mm_blendv_epi8(r128_0, r128_1, _mm_slli_epi32(idx128, 3)); __m128i r128 = _mm_blendv_epi8(r128_0, r128_1, _mm_slli_epi32(idx128, 3));
r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128); r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128);
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m2_t t1 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[0].sv128);
vuint8m2_t t2 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[1].sv128);
vuint8m2_t am2 = __riscv_vlmul_ext_v_u8m1_u8m2(a_.sv64);
vuint8m2_t t_combine = __riscv_vslideup_vx_u8m2(t1 , t2 , 16 , 32);
vuint8m2_t idxm2 = __riscv_vlmul_ext_v_u8m1_u8m2(idx_.sv64);
vbool4_t mask = __riscv_vmsgeu_vx_u8m2_b4 (idxm2, 32, 8);
vuint8m2_t r_tmp = __riscv_vrgather_vv_u8m2(t_combine , idxm2 , 8);
r_.sv64 = __riscv_vlmul_trunc_v_u8m2_u8m1(__riscv_vmerge_vvm_u8m2(r_tmp, am2, mask, 8));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -174,6 +188,17 @@ simde_vqtbx3_u8(simde_uint8x8_t a, simde_uint8x16x3_t t, simde_uint8x8_t idx) { ...@@ -174,6 +188,17 @@ simde_vqtbx3_u8(simde_uint8x8_t a, simde_uint8x16x3_t t, simde_uint8x8_t idx) {
__m128i r128 = _mm_blendv_epi8(r128_01, r128_2, _mm_slli_epi32(idx128, 2)); __m128i r128 = _mm_blendv_epi8(r128_01, r128_2, _mm_slli_epi32(idx128, 2));
r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128); r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128);
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t am4 = __riscv_vlmul_ext_v_u8m1_u8m4 (a_.sv64);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t2 , t3 , 16 , 48);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 48);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv64);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 48, 8);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 8);
r_.sv64 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vvm_u8m4(r_tmp, am4, mask, 8));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -238,6 +263,19 @@ simde_vqtbx4_u8(simde_uint8x8_t a, simde_uint8x16x4_t t, simde_uint8x8_t idx) { ...@@ -238,6 +263,19 @@ simde_vqtbx4_u8(simde_uint8x8_t a, simde_uint8x16x4_t t, simde_uint8x8_t idx) {
__m128i r128 = _mm_blendv_epi8(r128_01, r128_23, _mm_slli_epi32(idx128, 2)); __m128i r128 = _mm_blendv_epi8(r128_01, r128_23, _mm_slli_epi32(idx128, 2));
r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128); r128 = _mm_blendv_epi8(r128, _mm_set1_epi64(a_.m64), idx128);
r_.m64 = _mm_movepi64_pi64(r128); r_.m64 = _mm_movepi64_pi64(r128);
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t t4 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[3].sv128);
vuint8m4_t am4 = __riscv_vlmul_ext_v_u8m1_u8m4 (a_.sv64);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t3 , t4 , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t2 , t_combine , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 64);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv64);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 64, 8);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 8);
r_.sv64 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vvm_u8m4(r_tmp, am4, mask, 8));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -299,6 +337,10 @@ simde_vqtbx1q_u8(simde_uint8x16_t a, simde_uint8x16_t t, simde_uint8x16_t idx) { ...@@ -299,6 +337,10 @@ simde_vqtbx1q_u8(simde_uint8x16_t a, simde_uint8x16_t t, simde_uint8x16_t idx) {
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_v128_or(wasm_i8x16_swizzle(t_.v128, idx_.v128), r_.v128 = wasm_v128_or(wasm_i8x16_swizzle(t_.v128, idx_.v128),
wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(15)))); wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(15))));
#elif defined(SIMDE_RISCV_V_NATIVE)
vbool8_t mask = __riscv_vmsgeu_vx_u8m1_b8 (idx_.sv128, 16, 16);
r_.sv128 = __riscv_vrgather_vv_u8m1(t_.sv128 , idx_.sv128 , 16);
r_.sv128 = __riscv_vmerge_vvm_u8m1(r_.sv128, a_.sv128, mask, 16);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -361,6 +403,15 @@ simde_vqtbx2q_u8(simde_uint8x16_t a, simde_uint8x16x2_t t, simde_uint8x16_t idx) ...@@ -361,6 +403,15 @@ simde_vqtbx2q_u8(simde_uint8x16_t a, simde_uint8x16x2_t t, simde_uint8x16_t idx)
r_.v128 = wasm_v128_or(wasm_v128_or(wasm_i8x16_swizzle(t_[0].v128, idx_.v128), r_.v128 = wasm_v128_or(wasm_v128_or(wasm_i8x16_swizzle(t_[0].v128, idx_.v128),
wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))), wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))),
wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(31)))); wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(31))));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m2_t t1 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[0].sv128);
vuint8m2_t t2 = __riscv_vlmul_ext_v_u8m1_u8m2 (t_[1].sv128);
vuint8m2_t am2 = __riscv_vlmul_ext_v_u8m1_u8m2 (a_.sv128);
vuint8m2_t t_combine = __riscv_vslideup_vx_u8m2(t1 , t2 , 16 , 32);
vuint8m2_t idxm2 = __riscv_vlmul_ext_v_u8m1_u8m2(idx_.sv128);
vbool4_t mask = __riscv_vmsgeu_vx_u8m2_b4 (idxm2, 32, 16);
vuint8m2_t r_tmp = __riscv_vrgather_vv_u8m2(t_combine , idxm2 , 16);
r_.sv128 = __riscv_vlmul_trunc_v_u8m2_u8m1(__riscv_vmerge_vvm_u8m2(r_tmp, am2, mask, 16));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -434,6 +485,17 @@ simde_vqtbx3q_u8(simde_uint8x16_t a, simde_uint8x16x3_t t, simde_uint8x16_t idx) ...@@ -434,6 +485,17 @@ simde_vqtbx3q_u8(simde_uint8x16_t a, simde_uint8x16x3_t t, simde_uint8x16_t idx)
wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))), wasm_i8x16_swizzle(t_[1].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(16)))),
wasm_v128_or(wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32))) , wasm_v128_or(wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32))) ,
wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(47))))); wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(47)))));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t am4 = __riscv_vlmul_ext_v_u8m1_u8m4 (a_.sv128);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t2 , t3 , 16 , 48);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 48);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv128);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 48, 16);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 16);
r_.sv128 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vvm_u8m4(r_tmp, am4, mask, 16));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -511,6 +573,19 @@ simde_vqtbx4q_u8(simde_uint8x16_t a, simde_uint8x16x4_t t, simde_uint8x16_t idx) ...@@ -511,6 +573,19 @@ simde_vqtbx4q_u8(simde_uint8x16_t a, simde_uint8x16x4_t t, simde_uint8x16_t idx)
wasm_v128_or(wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32))), wasm_v128_or(wasm_i8x16_swizzle(t_[2].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(32))),
wasm_i8x16_swizzle(t_[3].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(48))))), wasm_i8x16_swizzle(t_[3].v128, wasm_i8x16_sub(idx_.v128, wasm_i8x16_splat(48))))),
wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(63)))); wasm_v128_and(a_.v128, wasm_u8x16_gt(idx_.v128, wasm_i8x16_splat(63))));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m4_t t1 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[0].sv128);
vuint8m4_t t2 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[1].sv128);
vuint8m4_t t3 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[2].sv128);
vuint8m4_t t4 = __riscv_vlmul_ext_v_u8m1_u8m4 (t_[3].sv128);
vuint8m4_t am4 = __riscv_vlmul_ext_v_u8m1_u8m4 (a_.sv128);
vuint8m4_t t_combine = __riscv_vslideup_vx_u8m4(t3 , t4 , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t2 , t_combine , 16 , 64);
t_combine = __riscv_vslideup_vx_u8m4(t1 , t_combine , 16 , 64);
vuint8m4_t idxm4 = __riscv_vlmul_ext_v_u8m1_u8m4(idx_.sv128);
vbool2_t mask = __riscv_vmsgeu_vx_u8m4_b2 (idxm4, 64, 16);
vuint8m4_t r_tmp = __riscv_vrgather_vv_u8m4(t_combine , idxm4 , 16);
r_.sv128 = __riscv_vlmul_trunc_v_u8m4_u8m1(__riscv_vmerge_vvm_u8m4(r_tmp, am4, mask, 16));
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
......
arm/neon/rbit.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Christopher Moore <moore@free.fr> * 2020 Christopher Moore <moore@free.fr>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
/* The GFNI implementation is based on Wojciech Muła's work at /* The GFNI implementation is based on Wojciech Muła's work at
...@@ -62,6 +63,13 @@ simde_vrbit_u8(simde_uint8x8_t a) { ...@@ -62,6 +63,13 @@ simde_vrbit_u8(simde_uint8x8_t a) {
a_.m64 = _mm_or_si64(_mm_andnot_si64(mask, _mm_slli_pi16(a_.m64, 2)), _mm_and_si64(mask, _mm_srli_pi16(a_.m64, 2))); a_.m64 = _mm_or_si64(_mm_andnot_si64(mask, _mm_slli_pi16(a_.m64, 2)), _mm_and_si64(mask, _mm_srli_pi16(a_.m64, 2)));
mask = _mm_set1_pi8(0x0F); mask = _mm_set1_pi8(0x0F);
r_.m64 = _mm_or_si64(_mm_andnot_si64(mask, _mm_slli_pi16(a_.m64, 4)), _mm_and_si64(mask, _mm_srli_pi16(a_.m64, 4))); r_.m64 = _mm_or_si64(_mm_andnot_si64(mask, _mm_slli_pi16(a_.m64, 4)), _mm_and_si64(mask, _mm_srli_pi16(a_.m64, 4)));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m1_t mask;
mask = __riscv_vmv_v_x_u8m1(0x55 , 8);
a_.sv64 = __riscv_vor_vv_u8m1(__riscv_vand_vv_u8m1(mask , __riscv_vsrl_vx_u8m1(a_.sv64 , 1 , 8) , 8) , __riscv_vsll_vx_u8m1(__riscv_vand_vv_u8m1(mask , a_.sv64 , 8) , 1 , 8) , 8);
mask = __riscv_vmv_v_x_u8m1(0x33 , 8);
a_.sv64 = __riscv_vor_vv_u8m1(__riscv_vand_vv_u8m1(mask , __riscv_vsrl_vx_u8m1(a_.sv64 , 2 , 8) , 8) , __riscv_vsll_vx_u8m1(__riscv_vand_vv_u8m1(mask , a_.sv64 , 8) , 2 , 8) , 8);
r_.sv64 = __riscv_vor_vv_u8m1(__riscv_vsrl_vx_u8m1(a_.sv64 , 4 , 8) , __riscv_vsll_vx_u8m1(a_.sv64 , 4 , 8) , 8);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -127,6 +135,13 @@ simde_vrbitq_u8(simde_uint8x16_t a) { ...@@ -127,6 +135,13 @@ simde_vrbitq_u8(simde_uint8x16_t a) {
a_.v128 = wasm_v128_bitselect(wasm_u8x16_shr(a_.v128, 1), wasm_i8x16_shl(a_.v128, 1), wasm_i8x16_splat(0x55)); a_.v128 = wasm_v128_bitselect(wasm_u8x16_shr(a_.v128, 1), wasm_i8x16_shl(a_.v128, 1), wasm_i8x16_splat(0x55));
a_.v128 = wasm_v128_bitselect(wasm_u8x16_shr(a_.v128, 2), wasm_i8x16_shl(a_.v128, 2), wasm_i8x16_splat(0x33)); a_.v128 = wasm_v128_bitselect(wasm_u8x16_shr(a_.v128, 2), wasm_i8x16_shl(a_.v128, 2), wasm_i8x16_splat(0x33));
r_.v128 = wasm_v128_or(wasm_u8x16_shr(a_.v128, 4), wasm_i8x16_shl(a_.v128, 4)); r_.v128 = wasm_v128_or(wasm_u8x16_shr(a_.v128, 4), wasm_i8x16_shl(a_.v128, 4));
#elif defined(SIMDE_RISCV_V_NATIVE)
vuint8m1_t mask;
mask = __riscv_vmv_v_x_u8m1(0x55 , 16);
a_.sv128 = __riscv_vor_vv_u8m1(__riscv_vand_vv_u8m1(mask , __riscv_vsrl_vx_u8m1(a_.sv128 , 1 , 16) , 16) , __riscv_vsll_vx_u8m1(__riscv_vand_vv_u8m1(mask , a_.sv128 , 16) , 1 , 16) , 16);
mask = __riscv_vmv_v_x_u8m1(0x33 , 16);
a_.sv128 = __riscv_vor_vv_u8m1(__riscv_vand_vv_u8m1(mask , __riscv_vsrl_vx_u8m1(a_.sv128 , 2 , 16) , 16) , __riscv_vsll_vx_u8m1(__riscv_vand_vv_u8m1(mask , a_.sv128 , 16) , 2 , 16) , 16);
r_.sv128 = __riscv_vor_vv_u8m1(__riscv_vsrl_vx_u8m1(a_.sv128 , 4 , 16) , __riscv_vsll_vx_u8m1(a_.sv128 , 4 , 16) , 16);
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
......
arm/neon/recpe.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2021 Zhi An Ng <zhin@google.com> (Copyright owned by Google, LLC) * 2021 Zhi An Ng <zhin@google.com> (Copyright owned by Google, LLC)
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_RECPE_H) #if !defined(SIMDE_ARM_NEON_RECPE_H)
...@@ -90,10 +91,14 @@ simde_vrecpe_f16(simde_float16x4_t a) { ...@@ -90,10 +91,14 @@ simde_vrecpe_f16(simde_float16x4_t a) {
r_, r_,
a_ = simde_float16x4_to_private(a); a_ = simde_float16x4_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
r_.sv64 = __riscv_vfrec7_v_f16m1(a_.sv64 , 4);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_vrecpeh_f16(a_.values[i]); r_.values[i] = simde_vrecpeh_f16(a_.values[i]);
} }
#endif
return simde_float16x4_from_private(r_); return simde_float16x4_from_private(r_);
#endif #endif
...@@ -113,7 +118,9 @@ simde_vrecpe_f32(simde_float32x2_t a) { ...@@ -113,7 +118,9 @@ simde_vrecpe_f32(simde_float32x2_t a) {
r_, r_,
a_ = simde_float32x2_to_private(a); a_ = simde_float32x2_to_private(a);
#if defined(SIMDE_IEEE754_STORAGE) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vfrec7_v_f32m1(a_.sv64 , 2);
#elif defined(SIMDE_IEEE754_STORAGE)
/* https://stackoverflow.com/questions/12227126/division-as-multiply-and-lut-fast-float-division-reciprocal/12228234#12228234 */ /* https://stackoverflow.com/questions/12227126/division-as-multiply-and-lut-fast-float-division-reciprocal/12228234#12228234 */
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
...@@ -152,7 +159,9 @@ simde_vrecpe_f64(simde_float64x1_t a) { ...@@ -152,7 +159,9 @@ simde_vrecpe_f64(simde_float64x1_t a) {
r_, r_,
a_ = simde_float64x1_to_private(a); a_ = simde_float64x1_to_private(a);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv64 = __riscv_vfrec7_v_f64m1(a_.sv64 , 1);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = 1.0 / a_.values; r_.values = 1.0 / a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -179,7 +188,9 @@ simde_vrecpeq_f64(simde_float64x2_t a) { ...@@ -179,7 +188,9 @@ simde_vrecpeq_f64(simde_float64x2_t a) {
r_, r_,
a_ = simde_float64x2_to_private(a); a_ = simde_float64x2_to_private(a);
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) #if defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfrec7_v_f64m1(a_.sv128 , 2);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.values = 1.0 / a_.values; r_.values = 1.0 / a_.values;
#else #else
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -208,8 +219,11 @@ simde_vrecpeq_f32(simde_float32x4_t a) { ...@@ -208,8 +219,11 @@ simde_vrecpeq_f32(simde_float32x4_t a) {
r_, r_,
a_ = simde_float32x4_to_private(a); a_ = simde_float32x4_to_private(a);
#if defined(SIMDE_X86_SSE_NATIVE) #if defined(SIMDE_X86_SSE_NATIVE)
r_.m128 = _mm_rcp_ps(a_.m128); r_.m128 = _mm_rcp_ps(a_.m128);
#elif defined(SIMDE_RISCV_V_NATIVE)
r_.sv128 = __riscv_vfrec7_v_f32m1(a_.sv128 , 4);
#elif defined(SIMDE_IEEE754_STORAGE) #elif defined(SIMDE_IEEE754_STORAGE)
/* https://stackoverflow.com/questions/12227126/division-as-multiply-and-lut-fast-float-division-reciprocal/12228234#12228234 */ /* https://stackoverflow.com/questions/12227126/division-as-multiply-and-lut-fast-float-division-reciprocal/12228234#12228234 */
SIMDE_VECTORIZE SIMDE_VECTORIZE
...@@ -249,10 +263,14 @@ simde_vrecpeq_f16(simde_float16x8_t a) { ...@@ -249,10 +263,14 @@ simde_vrecpeq_f16(simde_float16x8_t a) {
r_, r_,
a_ = simde_float16x8_to_private(a); a_ = simde_float16x8_to_private(a);
#if defined(SIMDE_RISCV_V_NATIVE) && defined(SIMDE_ARCH_RISCV_ZVFH)
r_.sv128 = __riscv_vfrec7_v_f16m1(a_.sv128 , 8);
#else
SIMDE_VECTORIZE SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) { for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
r_.values[i] = simde_vrecpeh_f16(a_.values[i]); r_.values[i] = simde_vrecpeh_f16(a_.values[i]);
} }
#endif
return simde_float16x8_from_private(r_); return simde_float16x8_from_private(r_);
#endif #endif
......
arm/neon/rev16.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Christopher Moore <moore@free.fr> * 2020 Christopher Moore <moore@free.fr>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_REV16_H) #if !defined(SIMDE_ARM_NEON_REV16_H)
...@@ -48,6 +49,9 @@ simde_vrev16_s8(simde_int8x8_t a) { ...@@ -48,6 +49,9 @@ simde_vrev16_s8(simde_int8x8_t a) {
#if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_shuffle_pi8(a_.m64, _mm_set_pi8(6, 7, 4, 5, 2, 3, 0, 1)); r_.m64 = _mm_shuffle_pi8(a_.m64, _mm_set_pi8(6, 7, 4, 5, 2, 3, 0, 1));
#elif defined(SIMDE_RISCV_V_NATIVE)
uint8_t shuffle_idx[] = {1, 0, 3, 2, 5, 4, 7, 6};
r_.sv64 = __riscv_vrgather_vv_i8m1(a_.sv64, __riscv_vle8_v_u8m1(shuffle_idx, 8), 8);
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762) #elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762)
r_.values = SIMDE_SHUFFLE_VECTOR_(8, 8, a_.values, a_.values, 1, 0, 3, 2, 5, 4, 7, 6); r_.values = SIMDE_SHUFFLE_VECTOR_(8, 8, a_.values, a_.values, 1, 0, 3, 2, 5, 4, 7, 6);
#else #else
...@@ -99,6 +103,9 @@ simde_vrev16q_s8(simde_int8x16_t a) { ...@@ -99,6 +103,9 @@ simde_vrev16q_s8(simde_int8x16_t a) {
r_.m128i = _mm_shuffle_epi8(a_.m128i, _mm_set_epi8(14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1)); r_.m128i = _mm_shuffle_epi8(a_.m128i, _mm_set_epi8(14, 15, 12, 13, 10, 11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14); r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
#elif defined(SIMDE_RISCV_V_NATIVE)
uint8_t shuffle_idx[] = {1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14};
r_.sv128 = __riscv_vrgather_vv_i8m1(a_.sv128, __riscv_vle8_v_u8m1(shuffle_idx, 16), 16);
#elif defined(SIMDE_SHUFFLE_VECTOR_) #elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, a_.values, a_.values, 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14); r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, a_.values, a_.values, 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14);
#else #else
......
arm/neon/rev32.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Christopher Moore <moore@free.fr> * 2020 Christopher Moore <moore@free.fr>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_REV32_H) #if !defined(SIMDE_ARM_NEON_REV32_H)
...@@ -48,6 +49,9 @@ simde_vrev32_s8(simde_int8x8_t a) { ...@@ -48,6 +49,9 @@ simde_vrev32_s8(simde_int8x8_t a) {
#if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_shuffle_pi8(a_.m64, _mm_set_pi8(4, 5, 6, 7, 0, 1, 2, 3)); r_.m64 = _mm_shuffle_pi8(a_.m64, _mm_set_pi8(4, 5, 6, 7, 0, 1, 2, 3));
#elif defined(SIMDE_RISCV_V_NATIVE)
uint8_t shuffle_idx[] = {3, 2, 1, 0, 7, 6, 5, 4};
r_.sv64 = __riscv_vrgather_vv_i8m1(a_.sv64, __riscv_vle8_v_u8m1(shuffle_idx, 8), 8);
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762) #elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762)
r_.values = SIMDE_SHUFFLE_VECTOR_(8, 8, a_.values, a_.values, 3, 2, 1, 0, 7, 6, 5, 4); r_.values = SIMDE_SHUFFLE_VECTOR_(8, 8, a_.values, a_.values, 3, 2, 1, 0, 7, 6, 5, 4);
#else #else
...@@ -77,6 +81,9 @@ simde_vrev32_s16(simde_int16x4_t a) { ...@@ -77,6 +81,9 @@ simde_vrev32_s16(simde_int16x4_t a) {
#if defined(SIMDE_X86_SSE_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_shuffle_pi16(a_.m64, (2 << 6) | (3 << 4) | (0 << 2) | (1 << 0)); r_.m64 = _mm_shuffle_pi16(a_.m64, (2 << 6) | (3 << 4) | (0 << 2) | (1 << 0));
#elif defined(SIMDE_RISCV_V_NATIVE)
uint16_t shuffle_idx[] = {1, 0, 3, 2};
r_.sv64 = __riscv_vrgather_vv_i16m1(a_.sv64, __riscv_vle16_v_u16m1(shuffle_idx, 4), 4);
#elif defined(SIMDE_SHUFFLE_VECTOR_) #elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.values = SIMDE_SHUFFLE_VECTOR_(16, 8, a_.values, a_.values, 1, 0, 3, 2); r_.values = SIMDE_SHUFFLE_VECTOR_(16, 8, a_.values, a_.values, 1, 0, 3, 2);
#else #else
...@@ -143,6 +150,9 @@ simde_vrev32q_s8(simde_int8x16_t a) { ...@@ -143,6 +150,9 @@ simde_vrev32q_s8(simde_int8x16_t a) {
4, 5, 6, 7, 0, 1, 2, 3)); 4, 5, 6, 7, 0, 1, 2, 3));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12); r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
#elif defined(SIMDE_RISCV_V_NATIVE)
uint8_t shuffle_idx[] = {3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12};
r_.sv128 = __riscv_vrgather_vv_i8m1(a_.sv128, __riscv_vle8_v_u8m1(shuffle_idx, 16), 16);
#elif defined(SIMDE_SHUFFLE_VECTOR_) #elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, a_.values, a_.values, 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12); r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, a_.values, a_.values, 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12);
#else #else
...@@ -173,7 +183,10 @@ simde_vrev32q_s16(simde_int16x8_t a) { ...@@ -173,7 +183,10 @@ simde_vrev32q_s16(simde_int16x8_t a) {
r_, r_,
a_ = simde_int16x8_to_private(a); a_ = simde_int16x8_to_private(a);
#if defined(SIMDE_X86_SSSE3_NATIVE) #if defined(SIMDE_RISCV_V_NATIVE)
uint16_t shuffle_idx[] = {1, 0, 3, 2, 5, 4, 7, 6};
r_.sv128 = __riscv_vrgather_vv_i16m1(a_.sv128, __riscv_vle16_v_u16m1(shuffle_idx, 8), 8);
#elif defined(SIMDE_X86_SSSE3_NATIVE)
r_.m128i = _mm_shuffle_epi8(a_.m128i, _mm_set_epi8(13, 12, 15, 14, 9, 8, 11, 10, r_.m128i = _mm_shuffle_epi8(a_.m128i, _mm_set_epi8(13, 12, 15, 14, 9, 8, 11, 10,
5, 4, 7, 6, 1, 0, 3, 2)); 5, 4, 7, 6, 1, 0, 3, 2));
#elif defined(SIMDE_X86_SSE2_NATIVE) #elif defined(SIMDE_X86_SSE2_NATIVE)
......
arm/neon/rev64.h
View file @ 408d06a3
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Christopher Moore <moore@free.fr> * 2020 Christopher Moore <moore@free.fr>
* 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology) * 2023 Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_REV64_H) #if !defined(SIMDE_ARM_NEON_REV64_H)
...@@ -48,6 +49,9 @@ simde_vrev64_s8(simde_int8x8_t a) { ...@@ -48,6 +49,9 @@ simde_vrev64_s8(simde_int8x8_t a) {
#if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSSE3_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_shuffle_pi8(a_.m64, _mm_set_pi8(0, 1, 2, 3, 4, 5, 6, 7)); r_.m64 = _mm_shuffle_pi8(a_.m64, _mm_set_pi8(0, 1, 2, 3, 4, 5, 6, 7));
#elif defined(SIMDE_RISCV_V_NATIVE)
uint8_t shuffle_idx[] = {7, 6, 5, 4, 3, 2, 1, 0};
r_.sv64 = __riscv_vrgather_vv_i8m1(a_.sv64, __riscv_vle8_v_u8m1(shuffle_idx, 8), 8);
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762) #elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762)
r_.values = SIMDE_SHUFFLE_VECTOR_(8, 8, a_.values, a_.values, 7, 6, 5, 4, 3, 2, 1, 0); r_.values = SIMDE_SHUFFLE_VECTOR_(8, 8, a_.values, a_.values, 7, 6, 5, 4, 3, 2, 1, 0);
#else #else
...@@ -77,6 +81,9 @@ simde_vrev64_s16(simde_int16x4_t a) { ...@@ -77,6 +81,9 @@ simde_vrev64_s16(simde_int16x4_t a) {
#if defined(SIMDE_X86_SSE_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_shuffle_pi16(a_.m64, (0 << 6) | (1 << 4) | (2 << 2) | (3 << 0)); r_.m64 = _mm_shuffle_pi16(a_.m64, (0 << 6) | (1 << 4) | (2 << 2) | (3 << 0));
#elif defined(SIMDE_RISCV_V_NATIVE)
uint16_t shuffle_idx[] = {3, 2, 1, 0};
r_.sv64 = __riscv_vrgather_vv_i16m1(a_.sv64, __riscv_vle16_v_u16m1(shuffle_idx, 4), 4);
#elif defined(SIMDE_SHUFFLE_VECTOR_) #elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.values = SIMDE_SHUFFLE_VECTOR_(16, 8, a_.values, a_.values, 3, 2, 1, 0); r_.values = SIMDE_SHUFFLE_VECTOR_(16, 8, a_.values, a_.values, 3, 2, 1, 0);
#else #else
...@@ -106,6 +113,9 @@ simde_vrev64_s32(simde_int32x2_t a) { ...@@ -106,6 +113,9 @@ simde_vrev64_s32(simde_int32x2_t a) {
#if defined(SIMDE_X86_SSE_NATIVE) && defined(SIMDE_X86_MMX_NATIVE) #if defined(SIMDE_X86_SSE_NATIVE) && defined(SIMDE_X86_MMX_NATIVE)
r_.m64 = _mm_shuffle_pi16(a_.m64, (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0)); r_.m64 = _mm_shuffle_pi16(a_.m64, (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0));
#elif defined(SIMDE_RISCV_V_NATIVE)
uint32_t shuffle_idx[] = {1, 0};
r_.sv64 = __riscv_vrgather_vv_i32m1(a_.sv64, __riscv_vle32_v_u32m1(shuffle_idx, 2), 2);
#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762) #elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_BUG_GCC_100762)
r_.values = SIMDE_SHUFFLE_VECTOR_(32, 8, a_.values, a_.values, 1, 0); r_.values = SIMDE_SHUFFLE_VECTOR_(32, 8, a_.values, a_.values, 1, 0);
#else #else
...@@ -214,6 +224,9 @@ simde_vrev64q_s8(simde_int8x16_t a) { ...@@ -214,6 +224,9 @@ simde_vrev64q_s8(simde_int8x16_t a) {
0, 1, 2, 3, 4, 5, 6, 7)); 0, 1, 2, 3, 4, 5, 6, 7));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8); r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
#elif defined(SIMDE_RISCV_V_NATIVE)
uint8_t shuffle_idx[] = {7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8};
r_.sv128 = __riscv_vrgather_vv_i8m1(a_.sv128, __riscv_vle8_v_u8m1(shuffle_idx, 16), 16);
#elif defined(SIMDE_SHUFFLE_VECTOR_) #elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, a_.values, a_.values, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8); r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, a_.values, a_.values, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8);
#else #else
...@@ -253,6 +266,9 @@ simde_vrev64q_s16(simde_int16x8_t a) { ...@@ -253,6 +266,9 @@ simde_vrev64q_s16(simde_int16x8_t a) {
(0 << 6) | (1 << 4) | (2 << 2) | (3 << 0)); (0 << 6) | (1 << 4) | (2 << 2) | (3 << 0));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8, 9); r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 6, 7, 4, 5, 2, 3, 0, 1, 14, 15, 12, 13, 10, 11, 8, 9);
#elif defined(SIMDE_RISCV_V_NATIVE)
uint16_t shuffle_idx[] = {3, 2, 1, 0, 7, 6, 5, 4};
r_.sv128 = __riscv_vrgather_vv_i16m1(a_.sv128, __riscv_vle16_v_u16m1(shuffle_idx, 8), 8);
#elif defined(SIMDE_SHUFFLE_VECTOR_) #elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.values = SIMDE_SHUFFLE_VECTOR_(16, 16, a_.values, a_.values, 3, 2, 1, 0, 7, 6, 5, 4); r_.values = SIMDE_SHUFFLE_VECTOR_(16, 16, a_.values, a_.values, 3, 2, 1, 0, 7, 6, 5, 4);
#else #else
...@@ -287,6 +303,9 @@ simde_vrev64q_s32(simde_int32x4_t a) { ...@@ -287,6 +303,9 @@ simde_vrev64q_s32(simde_int32x4_t a) {
r_.m128i = _mm_shuffle_epi32(a_.m128i, (2 << 6) | (3 << 4) | (0 << 2) | (1 << 0)); r_.m128i = _mm_shuffle_epi32(a_.m128i, (2 << 6) | (3 << 4) | (0 << 2) | (1 << 0));
#elif defined(SIMDE_WASM_SIMD128_NATIVE) #elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11); r_.v128 = wasm_i8x16_shuffle(a_.v128, a_.v128, 4, 5, 6, 7, 0, 1, 2, 3, 12, 13, 14, 15, 8, 9, 10, 11);
#elif defined(SIMDE_RISCV_V_NATIVE)
uint32_t shuffle_idx[] = {1, 0, 3, 2};
r_.sv128 = __riscv_vrgather_vv_i32m1(a_.sv128, __riscv_vle32_v_u32m1(shuffle_idx, 4), 4);
#elif defined(SIMDE_SHUFFLE_VECTOR_) #elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.values, a_.values, 1, 0, 3, 2); r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.values, a_.values, 1, 0, 3, 2);
#else #else
......
arm/neon/subl.h
View file @ 408d06a3
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
* Copyright: * Copyright:
* 2020 Evan Nemerson <evan@nemerson.com> * 2020 Evan Nemerson <evan@nemerson.com>
* 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC) * 2020 Sean Maher <seanptmaher@gmail.com> (Copyright owned by Google, LLC)
* 2023 Ju-Hung Li <jhlee@pllab.cs.nthu.edu.tw> (Copyright owned by NTHU pllab)
*/ */
#if !defined(SIMDE_ARM_NEON_SUBL_H) #if !defined(SIMDE_ARM_NEON_SUBL_H)
...@@ -42,6 +43,12 @@ simde_int16x8_t ...@@ -42,6 +43,12 @@ simde_int16x8_t
simde_vsubl_s8(simde_int8x8_t a, simde_int8x8_t b) { simde_vsubl_s8(simde_int8x8_t a, simde_int8x8_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vsubl_s8(a, b); return vsubl_s8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int16x8_private r_;
simde_int8x8_private a_ = simde_int8x8_to_private(a);
simde_int8x8_private b_ = simde_int8x8_to_private(b);
r_.sv128 = __riscv_vwsub_vv_i16m1(__riscv_vlmul_trunc_v_i8m1_i8mf2(a_.sv64) , __riscv_vlmul_trunc_v_i8m1_i8mf2(b_.sv64) , 8);
return simde_int16x8_from_private(r_);
#else #else
return simde_vsubq_s16(simde_vmovl_s8(a), simde_vmovl_s8(b)); return simde_vsubq_s16(simde_vmovl_s8(a), simde_vmovl_s8(b));
#endif #endif
...@@ -56,6 +63,12 @@ simde_int32x4_t ...@@ -56,6 +63,12 @@ simde_int32x4_t
simde_vsubl_s16(simde_int16x4_t a, simde_int16x4_t b) { simde_vsubl_s16(simde_int16x4_t a, simde_int16x4_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vsubl_s16(a, b); return vsubl_s16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int32x4_private r_;
simde_int16x4_private a_ = simde_int16x4_to_private(a);
simde_int16x4_private b_ = simde_int16x4_to_private(b);
r_.sv128 = __riscv_vwsub_vv_i32m1(__riscv_vlmul_trunc_v_i16m1_i16mf2(a_.sv64) , __riscv_vlmul_trunc_v_i16m1_i16mf2(b_.sv64) , 4);
return simde_int32x4_from_private(r_);
#else #else
return simde_vsubq_s32(simde_vmovl_s16(a), simde_vmovl_s16(b)); return simde_vsubq_s32(simde_vmovl_s16(a), simde_vmovl_s16(b));
#endif #endif
...@@ -70,6 +83,12 @@ simde_int64x2_t ...@@ -70,6 +83,12 @@ simde_int64x2_t
simde_vsubl_s32(simde_int32x2_t a, simde_int32x2_t b) { simde_vsubl_s32(simde_int32x2_t a, simde_int32x2_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vsubl_s32(a, b); return vsubl_s32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_int64x2_private r_;
simde_int32x2_private a_ = simde_int32x2_to_private(a);
simde_int32x2_private b_ = simde_int32x2_to_private(b);
r_.sv128 = __riscv_vwsub_vv_i64m1(__riscv_vlmul_trunc_v_i32m1_i32mf2(a_.sv64) , __riscv_vlmul_trunc_v_i32m1_i32mf2(b_.sv64) , 2);
return simde_int64x2_from_private(r_);
#else #else
return simde_vsubq_s64(simde_vmovl_s32(a), simde_vmovl_s32(b)); return simde_vsubq_s64(simde_vmovl_s32(a), simde_vmovl_s32(b));
#endif #endif
...@@ -84,6 +103,12 @@ simde_uint16x8_t ...@@ -84,6 +103,12 @@ simde_uint16x8_t
simde_vsubl_u8(simde_uint8x8_t a, simde_uint8x8_t b) { simde_vsubl_u8(simde_uint8x8_t a, simde_uint8x8_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vsubl_u8(a, b); return vsubl_u8(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint16x8_private r_;
simde_uint8x8_private a_ = simde_uint8x8_to_private(a);
simde_uint8x8_private b_ = simde_uint8x8_to_private(b);
r_.sv128 = __riscv_vwsubu_vv_u16m1(__riscv_vlmul_trunc_v_u8m1_u8mf2 (a_.sv64) , __riscv_vlmul_trunc_v_u8m1_u8mf2 (b_.sv64) , 8);
return simde_uint16x8_from_private(r_);
#else #else
return simde_vsubq_u16(simde_vmovl_u8(a), simde_vmovl_u8(b)); return simde_vsubq_u16(simde_vmovl_u8(a), simde_vmovl_u8(b));
#endif #endif
...@@ -98,6 +123,12 @@ simde_uint32x4_t ...@@ -98,6 +123,12 @@ simde_uint32x4_t
simde_vsubl_u16(simde_uint16x4_t a, simde_uint16x4_t b) { simde_vsubl_u16(simde_uint16x4_t a, simde_uint16x4_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vsubl_u16(a, b); return vsubl_u16(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint32x4_private r_;
simde_uint16x4_private a_ = simde_uint16x4_to_private(a);
simde_uint16x4_private b_ = simde_uint16x4_to_private(b);
r_.sv128 = __riscv_vwsubu_vv_u32m1(__riscv_vlmul_trunc_v_u16m1_u16mf2 (a_.sv64) , __riscv_vlmul_trunc_v_u16m1_u16mf2 (b_.sv64) , 4);
return simde_uint32x4_from_private(r_);
#else #else
return simde_vsubq_u32(simde_vmovl_u16(a), simde_vmovl_u16(b)); return simde_vsubq_u32(simde_vmovl_u16(a), simde_vmovl_u16(b));
#endif #endif
...@@ -112,6 +143,12 @@ simde_uint64x2_t ...@@ -112,6 +143,12 @@ simde_uint64x2_t
simde_vsubl_u32(simde_uint32x2_t a, simde_uint32x2_t b) { simde_vsubl_u32(simde_uint32x2_t a, simde_uint32x2_t b) {
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE) #if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
return vsubl_u32(a, b); return vsubl_u32(a, b);
#elif defined(SIMDE_RISCV_V_NATIVE)
simde_uint64x2_private r_;
simde_uint32x2_private a_ = simde_uint32x2_to_private(a);
simde_uint32x2_private b_ = simde_uint32x2_to_private(b);
r_.sv128 = __riscv_vwsubu_vv_u64m1(__riscv_vlmul_trunc_v_u32m1_u32mf2 (a_.sv64) , __riscv_vlmul_trunc_v_u32m1_u32mf2 (b_.sv64) , 4);
return simde_uint64x2_from_private(r_);
#else #else
return simde_vsubq_u64(simde_vmovl_u32(a), simde_vmovl_u32(b)); return simde_vsubq_u64(simde_vmovl_u32(a), simde_vmovl_u32(b));
#endif #endif
......
arm/neon/subl_high.h
View file @ 408d06a3
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arm/neon/subw.h
View file @ 408d06a3
This diff is collapsed.
arm/neon/subw_high.h
View file @ 408d06a3
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arm/neon/tbl.h
View file @ 408d06a3
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arm/neon/tbx.h
View file @ 408d06a3
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