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Commit a8ae10d9 authored by jinbo's avatar jinbo Committed by Michael R. Crusoe
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x86 sse2,avx2 loongarch impl: let compiler to generate instructions based on imm8 

On loongarch, for example simde_mm_srai_epi16, GCC will generate
a vsrai.h instruction for '>>' operator if the imm8 is a real
immediate const value, otherwise it will generate two instructions
vsral.h and vreplgr2vr.h. But for clang it always generates two
instructions. So don't use intrinsics directly, instead let the
compiler itself to generate instructions based on imm8, which will
save one instruction for GCC at least.

Same for below:
simde_mm_srai_epi32
simde_mm_slli_epi[16/32/64]
simde_mm_srli_epi[16/32/64]
simde_mm256_slli_epi[16/32/64]
simde_mm256_srai_epi[16/32]
simde_mm256_srli_epi[16/32/64]
parent bb0282e3
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Showing with 16 additions and 16 deletions
x86/avx2.h
View file @ a8ae10d9
......@@ -4574,7 +4574,7 @@ simde_mm256_slli_epi16 (simde__m256i a, const int imm8)
r_.altivec_i16[i] = vec_sl(a_.altivec_i16[i], sv);
}
#elif defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = imm8 > 15 ? __lasx_xvreplgr2vr_h(0) : __lasx_xvsll_h(a_.i256, __lasx_xvreplgr2vr_h(imm8));
r_.i256 = (simde__m256i)((v16i16)a_.i256 << imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i16 = a_.i16 << HEDLEY_STATIC_CAST(int16_t, imm8);
#else
......@@ -4613,7 +4613,7 @@ simde_mm256_slli_epi32 (simde__m256i a, const int imm8)
r_.altivec_i32[i] = vec_sl(a_.altivec_i32[i], sv);
}
#elif defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = imm8 > 31 ? __lasx_xvreplgr2vr_w(0) : __lasx_xvsll_w(a_.i256, __lasx_xvreplgr2vr_w(imm8));
r_.i256 = (simde__m256i)((v8i32)a_.i256 << imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i32 = a_.i32 << HEDLEY_STATIC_CAST(int32_t, imm8);
#else
......@@ -4647,7 +4647,7 @@ simde_mm256_slli_epi64 (simde__m256i a, const int imm8)
a_ = simde__m256i_to_private(a);
#if defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = imm8 > 63 ? __lasx_xvreplgr2vr_d(0) : __lasx_xvsll_d(a_.i256, __lasx_xvreplgr2vr_d(imm8));
r_.i256 = (simde__m256i)((v4i64)a_.i256 << imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i64 = a_.i64 << HEDLEY_STATIC_CAST(int64_t, imm8);
#else
......@@ -4935,7 +4935,7 @@ simde_mm256_srai_epi16 (simde__m256i a, const int imm8)
if (shift > 15) shift = 15;
#if defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = __lasx_xvsra_h(a_.i256, __lasx_xvreplgr2vr_h(shift));
r_.i256 = (simde__m256i)((v16i16)a_.i256 >> shift);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i16 = a_.i16 >> HEDLEY_STATIC_CAST(int16_t, shift);
#else
......@@ -4972,7 +4972,7 @@ simde_mm256_srai_epi32 (simde__m256i a, const int imm8)
if (shift > 31) shift = 31;
#if defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = __lasx_xvsra_w(a_.i256, __lasx_xvreplgr2vr_w(shift));
r_.i256 = (simde__m256i)((v8i32)a_.i256 >> shift);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i32 = a_.i32 >> HEDLEY_STATIC_CAST(int16_t, shift);
#else
......@@ -5196,7 +5196,7 @@ simde_mm256_srli_epi16 (simde__m256i a, const int imm8)
r_.altivec_u16[i] = vec_sr(a_.altivec_u16[i], sv);
}
#elif defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = __lasx_xvsrl_h(a_.i256, __lasx_xvreplgr2vr_h(imm8));
r_.i256 = (simde__m256i)((v16u16)a_.i256 >> imm8);
#else
if (HEDLEY_STATIC_CAST(unsigned int, imm8) > 15) {
simde_memset(&r_, 0, sizeof(r_));
......@@ -5241,7 +5241,7 @@ simde_mm256_srli_epi32 (simde__m256i a, const int imm8)
r_.altivec_u32[i] = vec_sr(a_.altivec_u32[i], sv);
}
#elif defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = imm8 > 31 ? __lasx_xvreplgr2vr_w(0) : __lasx_xvsrl_w(a_.i256, __lasx_xvreplgr2vr_w(imm8));
r_.i256 = (simde__m256i)((v8u32)a_.i256 >> imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.u32 = a_.u32 >> SIMDE_CAST_VECTOR_SHIFT_COUNT(16, imm8);
#else
......@@ -5275,7 +5275,7 @@ simde_mm256_srli_epi64 (simde__m256i a, const int imm8)
a_ = simde__m256i_to_private(a);
#if defined(SIMDE_LOONGARCH_LASX_NATIVE)
r_.i256 = imm8 > 63 ? __lasx_xvreplgr2vr_d(0) : __lasx_xvsrl_d(a_.i256, __lasx_xvreplgr2vr_d(imm8));
r_.i256 = (simde__m256i)((v4u64)a_.i256 >> imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.u64 = a_.u64 >> SIMDE_CAST_VECTOR_SHIFT_COUNT(32, imm8);
#else
......
x86/sse2.h
View file @ a8ae10d9
......@@ -6458,7 +6458,7 @@ simde_mm_srai_epi16 (simde__m128i a, const int imm8)
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i16x8_shr(a_.wasm_v128, HEDLEY_STATIC_CAST(uint32_t, cnt));
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsra_h(a_.lsx_i64, __lsx_vreplgr2vr_h(cnt));
r_.lsx_i64 = (simde__m128i)((v8i16)a_.lsx_i64 >> cnt);
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_) / sizeof(r_.i16[0])) ; i++) {
......@@ -6491,7 +6491,7 @@ simde_mm_srai_epi32 (simde__m128i a, const int imm8)
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i32x4_shr(a_.wasm_v128, HEDLEY_STATIC_CAST(uint32_t, cnt));
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsra_w(a_.lsx_i64, __lsx_vreplgr2vr_w(cnt));
r_.lsx_i64 = (simde__m128i)((v4i32)a_.lsx_i64 >> cnt);
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_) / sizeof(r_.i32[0])) ; i++) {
......@@ -6587,7 +6587,7 @@ simde_mm_slli_epi16 (simde__m128i a, const int imm8)
a_ = simde__m128i_to_private(a);
#if defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsll_h(a_.lsx_i64, __lsx_vreplgr2vr_h(imm8));
r_.lsx_i64 = (simde__m128i)((v8i16)a_.lsx_i64 << imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i16 = a_.i16 << SIMDE_CAST_VECTOR_SHIFT_COUNT(8, imm8 & 0xff);
#else
......@@ -6633,7 +6633,7 @@ simde_mm_slli_epi32 (simde__m128i a, const int imm8)
a_ = simde__m128i_to_private(a);
#if defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsll_w(a_.lsx_i64, __lsx_vreplgr2vr_w(imm8));
r_.lsx_i64 = (simde__m128i)((v4i32)a_.lsx_i64 << imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i32 = a_.i32 << imm8;
#else
......@@ -6690,7 +6690,7 @@ simde_mm_slli_epi64 (simde__m128i a, const int imm8)
a_ = simde__m128i_to_private(a);
#if defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsll_d(a_.lsx_i64, __lsx_vreplgr2vr_d(imm8));
r_.lsx_i64 = (simde__m128i)((v2i64)a_.lsx_i64 << imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.i64 = a_.i64 << imm8;
#else
......@@ -6732,7 +6732,7 @@ simde_mm_srli_epi16 (simde__m128i a, const int imm8)
a_ = simde__m128i_to_private(a);
#if defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsrl_h(a_.lsx_i64, __lsx_vreplgr2vr_h(imm8));
r_.lsx_i64 = (simde__m128i)((v8u16)a_.lsx_i64 >> imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.u16 = a_.u16 >> SIMDE_CAST_VECTOR_SHIFT_COUNT(8, imm8);
#else
......@@ -6777,7 +6777,7 @@ simde_mm_srli_epi32 (simde__m128i a, const int imm8)
a_ = simde__m128i_to_private(a);
#if defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsrl_w(a_.lsx_i64, __lsx_vreplgr2vr_w(imm8));
r_.lsx_i64 = (simde__m128i)((v4u32)a_.lsx_i64 >> imm8);
#elif defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR)
r_.u32 = a_.u32 >> SIMDE_CAST_VECTOR_SHIFT_COUNT(8, imm8 & 0xff);
#else
......@@ -6836,7 +6836,7 @@ simde_mm_srli_epi64 (simde__m128i a, const int imm8)
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
r_.neon_u64 = vshlq_u64(a_.neon_u64, vdupq_n_s64(-imm8));
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vsrl_d(a_.lsx_i64, __lsx_vreplgr2vr_d(imm8));
r_.lsx_i64 = (simde__m128i)((v2u64)a_.lsx_i64 >> imm8);
#else
#if defined(SIMDE_VECTOR_SUBSCRIPT_SCALAR) && !defined(SIMDE_BUG_GCC_94488)
r_.u64 = a_.u64 >> SIMDE_CAST_VECTOR_SHIFT_COUNT(8, imm8);
......
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