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Commit cf8e6a73 authored by Ruhung's avatar Ruhung Committed by GitHub
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riscv64: Enable V feature when both zve64d and zvl128b are present (#1284) 

Co-authored-by: default avatarJuhung Li <jhlee755@andestech.com>
parent c7f26b73
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simde-arch.h
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...@@ -541,7 +541,7 @@ ...@@ -541,7 +541,7 @@
#if defined(__riscv_zve64d) #if defined(__riscv_zve64d)
# define SIMDE_ARCH_RISCV_ZVE64D 1 # define SIMDE_ARCH_RISCV_ZVE64D 1
#endif #endif
#if defined(__riscv_v) #if defined(__riscv_v) || (defined(__riscv_zve64d) && defined(__riscv_zvl128b))
# define SIMDE_ARCH_RISCV_V 1 # define SIMDE_ARCH_RISCV_V 1
#endif #endif
#if defined(__riscv_zvfh) #if defined(__riscv_zvfh)
......
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