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Commit ffe050ce authored by Michael R. Crusoe's avatar Michael R. Crusoe Committed by Michael R. Crusoe
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wasm relaxed: updated names; reordered FMA operations 

all functions now have "_relaxed" in their names
fma→madd
fms→nmadd
parent 762d7ad2
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Showing with 81 additions and 71 deletions
mips/msa/madd.h
View file @ ffe050ce
......@@ -56,7 +56,7 @@ simde_msa_fmadd_w(simde_v4f32 a, simde_v4f32 b, simde_v4f32 c) {
#elif defined(SIMDE_X86_SSE_NATIVE)
r_.m128 = _mm_add_ps(a_.m128, _mm_mul_ps(b_.m128, c_.m128));
#elif defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_f32x4_fma(a_.v128, b_.v128, c_.v128);
r_.v128 = wasm_f32x4_relaxed_madd(b_.v128, c_.v128, a_.v128);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_f32x4_add(a_.v128, wasm_f32x4_mul(b_.v128, c_.v128));
#elif defined(SIMDE_VECTOR_SUBSCRIPT)
......@@ -97,7 +97,7 @@ simde_msa_fmadd_d(simde_v2f64 a, simde_v2f64 b, simde_v2f64 c) {
#elif defined(SIMDE_X86_SSE2_NATIVE)
r_.m128d = _mm_add_pd(a_.m128d, _mm_mul_pd(b_.m128d, c_.m128d));
#elif defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
r_.v128 = wasm_f64x2_fma(a_.v128, b_.v128, c_.v128);
r_.v128 = wasm_f64x2_relaxed_madd(b_.v128, c_.v128, a_.v128);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.v128 = wasm_f64x2_add(a_.v128, wasm_f64x2_mul(b_.v128, c_.v128));
#elif defined(SIMDE_VECTOR_SUBSCRIPT_OPS)
......
wasm/relaxed-simd.h
View file @ ffe050ce
......@@ -37,8 +37,10 @@ SIMDE_BEGIN_DECLS_
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_i8x16_swizzle_relaxed (simde_v128_t a, simde_v128_t b) {
#if defined(SIMDE_WASM_SIMD128_NATIVE)
simde_wasm_i8x16_relaxed_swizzle(simde_v128_t a, simde_v128_t b) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_i8x16_relaxed_swizzle(a, b);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_i8x16_swizzle(a, b);
#else
simde_v128_private
......@@ -71,15 +73,17 @@ simde_wasm_i8x16_swizzle_relaxed (simde_v128_t a, simde_v128_t b) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_i8x16_swizzle_relaxed(a, b) simde_wasm_i8x16_swizzle_relaxed((a), (b))
#define wasm_i8x16_relaxed_swizzle(a, b) simde_wasm_i8x16_relaxed_swizzle((a), (b))
#endif
/* Conversions */
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_i32x4_trunc_f32x4 (simde_v128_t a) {
#if defined(SIMDE_WASM_SIMD128_NATIVE)
simde_wasm_i32x4_relaxed_trunc_f32x4 (simde_v128_t a) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_i32x4_relaxed_trunc_f32x4(a);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_i32x4_trunc_sat_f32x4(a);
#else
simde_v128_private
......@@ -107,13 +111,15 @@ simde_wasm_i32x4_trunc_f32x4 (simde_v128_t a) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_i32x4_trunc_f32x4(a) simde_wasm_i32x4_trunc_f32x4((a))
#define wasm_i32x4_relaxed_trunc_f32x4(a) simde_wasm_i32x4_relaxed_trunc_f32x4((a))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_u32x4_trunc_f32x4 (simde_v128_t a) {
#if defined(SIMDE_WASM_SIMD128_NATIVE)
simde_wasm_u32x4_relaxed_trunc_f32x4 (simde_v128_t a) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_u32x4_relaxed_trunc_f32x4(a);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_u32x4_trunc_sat_f32x4(a);
#else
simde_v128_private
......@@ -152,13 +158,15 @@ simde_wasm_u32x4_trunc_f32x4 (simde_v128_t a) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_u32x4_trunc_f32x4(a) simde_wasm_u32x4_trunc_f32x4((a))
#define wasm_u32x4_relaxed_trunc_f32x4(a) simde_wasm_u32x4_relaxed_trunc_f32x4((a))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_i32x4_trunc_f64x2_zero (simde_v128_t a) {
#if defined(SIMDE_WASM_SIMD128_NATIVE)
simde_wasm_i32x4_relaxed_trunc_f64x2_zero (simde_v128_t a) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_i32x4_relaxed_trunc_f64x2_zero(a);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_i32x4_trunc_sat_f64x2_zero(a);
#else
simde_v128_private
......@@ -209,13 +217,15 @@ simde_wasm_i32x4_trunc_f64x2_zero (simde_v128_t a) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_i32x4_trunc_f64x2_zero(a) simde_wasm_i32x4_trunc_f64x2_zero((a))
#define wasm_i32x4_relaxed_trunc_f64x2_zero(a) simde_wasm_i32x4_relaxed_trunc_f64x2_zero((a))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_u32x4_trunc_f64x2_zero (simde_v128_t a) {
#if defined(SIMDE_WASM_SIMD128_NATIVE)
simde_wasm_u32x4_relaxed_trunc_f64x2_zero (simde_v128_t a) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_u32x4_relaxed_trunc_f64x2_zero(a);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_u32x4_trunc_sat_f64x2_zero(a);
#else
simde_v128_private
......@@ -254,14 +264,14 @@ simde_wasm_u32x4_trunc_f64x2_zero (simde_v128_t a) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_u32x4_trunc_f64x2_zero(a) simde_wasm_u32x4_trunc_f64x2_zero((a))
#define wasm_u32x4_relaxed_trunc_f64x2_zero(a) simde_wasm_u32x4_relaxed_trunc_f64x2_zero((a))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_i8x16_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
simde_wasm_i8x16_relaxed_laneselect(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_i8x16_blend(a, b, mask);
return wasm_i8x16_relaxed_laneselect(a, b, mask);
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -276,15 +286,15 @@ simde_wasm_i8x16_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
return simde_wasm_v128_bitselect(a, b, mask);
#endif
}
#if defined(SIMDE_WASM_SIMD128_ENABLE_NATIVE_ALIASES)
#define wasm_i8x16_blend(a, b, c) simde_wasm_i8x16_blend((a), (b), (c))
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_i8x16_relaxed_laneselect(a, b, mask) simde_wasm_i8x16_relaxed_laneselect((a), (b), (mask))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_i16x8_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
simde_wasm_i16x8_relaxed_laneselect(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_i16x8_blend(a, b, mask);
return wasm_i16x8_relaxed_laneselect(a, b, mask);
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -299,15 +309,15 @@ simde_wasm_i16x8_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
return simde_wasm_v128_bitselect(a, b, mask);
#endif
}
#if defined(SIMDE_WASM_SIMD128_ENABLE_NATIVE_ALIASES)
#define wasm_i16x8_blend(a, b, c) simde_wasm_i16x8_blend((a), (b), (c))
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_i16x8_relaxed_laneselect(a, b, mask) simde_wasm_i16x8_relaxed_laneselect((a), (b), (mask))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_i32x4_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
simde_wasm_i32x4_relaxed_laneselect(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_i32x4_blend(a, b, mask);
return wasm_i32x4_relaxed_laneselect(a, b, mask);
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -322,15 +332,15 @@ simde_wasm_i32x4_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
return simde_wasm_v128_bitselect(a, b, mask);
#endif
}
#if defined(SIMDE_WASM_SIMD128_ENABLE_NATIVE_ALIASES)
#define wasm_i32x4_blend(a, b, c) simde_wasm_i32x4_blend((a), (b), (c))
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_i32x4_relaxed_laneselect(a, b, c) simde_wasm_i32x4_relaxed_laneselect((a), (b), (c))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_i64x2_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
simde_wasm_i64x2_relaxed_laneselect(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_i64x2_blend(a, b, mask);
return wasm_i64x2_relaxed_laneselect(a, b, mask);
#elif defined(SIMDE_X86_SSE4_1_NATIVE)
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -345,19 +355,19 @@ simde_wasm_i64x2_blend(simde_v128_t a, simde_v128_t b, simde_v128_t mask) {
return simde_wasm_v128_bitselect(a, b, mask);
#endif
}
#if defined(SIMDE_WASM_SIMD128_ENABLE_NATIVE_ALIASES)
#define wasm_i64x2_blend(a, b, c) simde_wasm_i64x2_blend((a), (b), (c))
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_i64x2_relaxed_laneselect(a, b, mask) simde_wasm_i64x2_relaxed_laneselect((a), (b), (mask))
#endif
/* fma */
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_f32x4_fma (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
simde_wasm_f32x4_relaxed_madd (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_f32x4_fma(a, b, c);
return wasm_f32x4_relaxed_madd(a, b, c);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_f32x4_add(a, wasm_f32x4_mul(b, c));
return wasm_f32x4_add(wasm_f32x4_mul(a, b), c);
#else
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -366,19 +376,19 @@ simde_wasm_f32x4_fma (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
r_;
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
r_.altivec_f32 = vec_madd(c_.altivec_f32, b_.altivec_f32, a_.altivec_f32);
r_.altivec_f32 = vec_madd(a_.altivec_f32, b_.altivec_f32, c_.altivec_f32);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
r_.neon_f32 = vfmaq_f32(a_.neon_f32, c_.neon_f32, b_.neon_f32);
r_.neon_f32 = vfmaq_f32(a_.neon_f32, b_.neon_f32, c_.neon_f32);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
r_.neon_f32 = vmlaq_f32(a_.neon_f32, b_.neon_f32, c_.neon_f32);
r_.neon_f32 = vmlaq_f32(c_.neon_f32, a_.neon_f32, b_.neon_f32);
#elif defined(SIMDE_X86_FMA_NATIVE)
r_.sse_m128 = _mm_fmadd_ps(c_.sse_m128, b_.sse_m128, a_.sse_m128);
r_.sse_m128 = _mm_fmadd_ps(a_.sse_m128, b_.sse_m128, c_.sse_m128);
#elif defined(SIMDE_VECTOR_SUBSCRIPT)
r_.f32 = a_.f32 + (b_.f32 * c_.f32);
r_.f32 = (a_.f32 * b_.f32) + c_.f32;
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.f32) / sizeof(r_.f32[0])) ; i++) {
r_.f32[i] = simde_math_fmaf(c_.f32[i], b_.f32[i], a_.f32[i]);
r_.f32[i] = simde_math_fmaf(a_.f32[i], b_.f32[i], c_.f32[i]);
}
#endif
......@@ -386,16 +396,16 @@ simde_wasm_f32x4_fma (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_f32x4_fma(a, b) simde_wasm_f32x4_fma((a), (b))
#define wasm_f32x4_relaxed_madd(a, b, c) simde_wasm_f32x4_relaxed_madd((a), (b), (c))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_f64x2_fma (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
simde_wasm_f64x2_relaxed_madd (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_f64x2_fma(a, b, c);
return wasm_f64x2_relaxed_madd(a, b, c);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_f64x2_add(a, wasm_f64x2_mul(b, c));
return wasm_f64x2_add(wasm_f64x2_mul(a, b), c);
#else
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -404,17 +414,17 @@ simde_wasm_f64x2_fma (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
r_;
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE) || defined(SIMDE_ZARCH_ZVECTOR_13_NATIVE)
r_.altivec_f64 = vec_madd(c_.altivec_f64, b_.altivec_f64, a_.altivec_f64);
r_.altivec_f64 = vec_madd(a_.altivec_f64, b_.altivec_f64, c_.altivec_f64);
#elif defined(SIMDE_ARM_NEON_A64V8_NATIVE)
r_.neon_f64 = vfmaq_f64(a_.neon_f64, c_.neon_f64, b_.neon_f64);
r_.neon_f64 = vfmaq_f64(c_.neon_f64, a_.neon_f64, b_.neon_f64);
#elif defined(SIMDE_X86_FMA_NATIVE)
r_.sse_m128d = _mm_fmadd_pd(c_.sse_m128d, b_.sse_m128d, a_.sse_m128d);
r_.sse_m128d = _mm_fmadd_pd(a_.sse_m128d, b_.sse_m128d, c_.sse_m128d);
#elif defined(SIMDE_VECTOR_SUBSCRIPT)
r_.f64 = a_.f64 + (b_.f64 * c_.f64);
r_.f64 = (a_.f64 * b_.f64) + c_.f64;
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.f64) / sizeof(r_.f64[0])) ; i++) {
r_.f64[i] = simde_math_fma(c_.f64[i], b_.f64[i], a_.f64[i]);
r_.f64[i] = simde_math_fma(a_.f64[i], b_.f64[i], c_.f64[i]);
}
#endif
......@@ -422,18 +432,18 @@ simde_wasm_f64x2_fma (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_f64x2_fma(a, b) simde_wasm_f64x2_fma((a), (b))
#define wasm_f64x2_relaxed_madd(a, b, c) simde_wasm_f64x2_relaxed_madd((a), (b), (c))
#endif
/* fms */
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_f32x4_fms (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
simde_wasm_f32x4_relaxed_nmadd (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_f32x4_fms(a, b, c);
return wasm_f32x4_relaxed_nmadd(a, b, c);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_f32x4_sub(a, wasm_f32x4_mul(b, c));
return wasm_f32x4_sub(c, wasm_f32x4_mul(a, b));
#else
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -442,19 +452,19 @@ simde_wasm_f32x4_fms (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
r_;
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
r_.altivec_f32 = vec_nmsub(c_.altivec_f32, b_.altivec_f32, a_.altivec_f32);
r_.altivec_f32 = vec_nmsub(a_.altivec_f32, b_.altivec_f32, c_.altivec_f32);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA)
r_.neon_f32 = vfmsq_f32(a_.neon_f32, c_.neon_f32, b_.neon_f32);
r_.neon_f32 = vfmsq_f32(a_.neon_f32, b_.neon_f32, c_.neon_f32);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
r_.neon_f32 = vmlsq_f32(a_.neon_f32, b_.neon_f32, c_.neon_f32);
r_.neon_f32 = vmlsq_f32(c_.neon_f32, a_.neon_f32, b_.neon_f32);
#elif defined(SIMDE_X86_FMA_NATIVE)
r_.sse_m128 = _mm_fnmadd_ps(c_.sse_m128, b_.sse_m128, a_.sse_m128);
r_.sse_m128 = _mm_fnmadd_ps(a_.sse_m128, b_.sse_m128, c_.sse_m128);
#elif defined(SIMDE_VECTOR_SUBSCRIPT)
r_.f32 = a_.f32 - (b_.f32 * c_.f32);
r_.f32 = c_.f32 - (a_.f32 * b_.f32);
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.f32) / sizeof(r_.f32[0])) ; i++) {
r_.f32[i] = a_.f32[i] - (b_.f32[i] * c_.f32[i]);
r_.f32[i] = c_.f32[i] - (a_.f32[i] * b_.f32[i]);
}
#endif
......@@ -462,16 +472,16 @@ simde_wasm_f32x4_fms (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_f32x4_fms(a, b) simde_wasm_f32x4_fms((a), (b))
#define wasm_f32x4_relaxed_nmadd(a, b, c) simde_wasm_f32x4_relaxed_nmadd((a), (b), (c))
#endif
SIMDE_FUNCTION_ATTRIBUTES
simde_v128_t
simde_wasm_f64x2_fms (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
simde_wasm_f64x2_relaxed_nmadd (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#if defined(SIMDE_WASM_RELAXED_SIMD_NATIVE)
return wasm_f64x2_fms(a, b, c);
return wasm_f64x2_relaxed_nmadd(a, b, c);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
return wasm_f64x2_sub(a, wasm_f64x2_mul(b, c));
return wasm_f64x2_sub(c, wasm_f64x2_mul(a, b));
#else
simde_v128_private
a_ = simde_v128_to_private(a),
......@@ -480,17 +490,17 @@ simde_wasm_f64x2_fms (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
r_;
#if defined(SIMDE_POWER_ALTIVEC_P7_NATIVE)
r_.altivec_f64 = vec_nmsub(c_.altivec_f64, b_.altivec_f64, a_.altivec_f64);
r_.altivec_f64 = vec_nmsub(a_.altivec_f64, b_.altivec_f64, c_.altivec_f64);
#elif defined(SIMDE_ARM_NEON_A64V8_NATIVE)
r_.neon_f64 = vfmsq_f64(a_.neon_f64, c_.neon_f64, b_.neon_f64);
r_.neon_f64 = vfmsq_f64(a_.neon_f64, b_.neon_f64, c_.neon_f64);
#elif defined(SIMDE_X86_FMA_NATIVE)
r_.sse_m128d = _mm_fnmadd_pd(c_.sse_m128d, b_.sse_m128d, a_.sse_m128d);
r_.sse_m128d = _mm_fnmadd_pd(a_.sse_m128d, b_.sse_m128d, c_.sse_m128d);
#elif defined(SIMDE_VECTOR_SUBSCRIPT)
r_.f64 = a_.f64 - (b_.f64 * c_.f64);
r_.f64 = c_.f64 - (a_.f64 * b_.f64);
#else
SIMDE_VECTORIZE
for (size_t i = 0 ; i < (sizeof(r_.f64) / sizeof(r_.f64[0])) ; i++) {
r_.f64[i] = a_.f64[i] - (b_.f64[i] * c_.f64[i]);
r_.f64[i] = c_.f64[i] - (a_.f64[i] * b_.f64[i]);
}
#endif
......@@ -498,7 +508,7 @@ simde_wasm_f64x2_fms (simde_v128_t a, simde_v128_t b, simde_v128_t c) {
#endif
}
#if defined(SIMDE_WASM_RELAXED_SIMD_ENABLE_NATIVE_ALIASES)
#define wasm_f64x2_fms(a, b) simde_wasm_f64x2_fms((a), (b))
#define wasm_f64x2_relaxed_nmadd(a, b, c) simde_wasm_f64x2_relaxed_nmadd((a), (b), (c))
#endif
SIMDE_END_DECLS_
......
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