Commit b4398164 authored by francescomani's avatar francescomani

use frame structure parameter for slots per frame

parent ff58b5e1
...@@ -519,7 +519,7 @@ void config_frame_structure(int mu, ...@@ -519,7 +519,7 @@ void config_frame_structure(int mu,
} else { // FDD } else { // FDD
fs->is_tdd = false; fs->is_tdd = false;
fs->numb_period_frame = 1; fs->numb_period_frame = 1;
fs->numb_slots_period = nr_slots_per_frame[mu]; fs->numb_slots_period = fs->numb_slots_frame;
} }
AssertFatal(fs->numb_period_frame > 0, "Frame configuration cannot be configured!\n"); AssertFatal(fs->numb_period_frame > 0, "Frame configuration cannot be configured!\n");
} }
......
...@@ -64,10 +64,7 @@ void clear_nr_nfapi_information(gNB_MAC_INST *gNB, ...@@ -64,10 +64,7 @@ void clear_nr_nfapi_information(gNB_MAC_INST *gNB,
nfapi_nr_ul_dci_request_t *UL_dci_req) nfapi_nr_ul_dci_request_t *UL_dci_req)
{ {
/* called below and in simulators, so we assume a lock but don't require it */ /* called below and in simulators, so we assume a lock but don't require it */
const int num_slots = gNB->frame_structure.numb_slots_frame;
NR_ServingCellConfigCommon_t *scc = gNB->common_channels->ServingCellConfigCommon;
const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
UL_tti_req_ahead_initialization(gNB, num_slots, CC_idP, frameP, slotP); UL_tti_req_ahead_initialization(gNB, num_slots, CC_idP, frameP, slotP);
nfapi_nr_dl_tti_pdcch_pdu_rel15_t **pdcch = (nfapi_nr_dl_tti_pdcch_pdu_rel15_t **)gNB->pdcch_pdu_idx[CC_idP]; nfapi_nr_dl_tti_pdcch_pdu_rel15_t **pdcch = (nfapi_nr_dl_tti_pdcch_pdu_rel15_t **)gNB->pdcch_pdu_idx[CC_idP];
...@@ -103,14 +100,13 @@ void clear_nr_nfapi_information(gNB_MAC_INST *gNB, ...@@ -103,14 +100,13 @@ void clear_nr_nfapi_information(gNB_MAC_INST *gNB,
TX_req[CC_idP].Number_of_PDUs = 0; TX_req[CC_idP].Number_of_PDUs = 0;
} }
void clear_beam_information(NR_beam_info_t *beam_info, int frame, int slot, int mu) static void clear_beam_information(NR_beam_info_t *beam_info, int frame, int slot, int slots_per_frame)
{ {
// for now we use the same logic of UL_tti_req_ahead // for now we use the same logic of UL_tti_req_ahead
// reset after 1 frame with the exception of 15kHz // reset after 1 frame with the exception of 15kHz
if(!beam_info->beam_allocation) if(!beam_info->beam_allocation)
return; return;
// initialization done only once // initialization done only once
const int slots_per_frame = nr_slots_per_frame[mu];
AssertFatal(beam_info->beam_allocation_size >= 0, "Beam information not initialized\n"); AssertFatal(beam_info->beam_allocation_size >= 0, "Beam information not initialized\n");
int idx_to_clear = (frame * slots_per_frame + slot) / beam_info->beam_duration; int idx_to_clear = (frame * slots_per_frame + slot) / beam_info->beam_duration;
idx_to_clear = (idx_to_clear + beam_info->beam_allocation_size - 1) % beam_info->beam_allocation_size; idx_to_clear = (idx_to_clear + beam_info->beam_allocation_size - 1) % beam_info->beam_allocation_size;
...@@ -215,8 +211,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_ ...@@ -215,8 +211,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
NR_SCHED_LOCK(&gNB->sched_lock); NR_SCHED_LOCK(&gNB->sched_lock);
int slots_frame = gNB->frame_structure.numb_slots_frame;
clear_beam_information(&gNB->beam_info, frame, slot, *scc->ssbSubcarrierSpacing); clear_beam_information(&gNB->beam_info, frame, slot, slots_frame);
gNB->frame = frame; gNB->frame = frame;
start_meas(&gNB->eNB_scheduler); start_meas(&gNB->eNB_scheduler);
...@@ -240,9 +236,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_ ...@@ -240,9 +236,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
for (int i = 0; i < num_beams; i++) for (int i = 0; i < num_beams; i++)
memset(cc[CC_id].vrb_map[i], 0, sizeof(uint16_t) * MAX_BWP_SIZE); memset(cc[CC_id].vrb_map[i], 0, sizeof(uint16_t) * MAX_BWP_SIZE);
// clear last scheduled slot's content (only)! // clear last scheduled slot's content (only)!
const int num_slots = nr_slots_per_frame[*scc->ssbSubcarrierSpacing];
const int size = gNB->vrb_map_UL_size; const int size = gNB->vrb_map_UL_size;
const int prev_slot = frame * num_slots + slot + size - 1; const int prev_slot = frame * slots_frame + slot + size - 1;
for (int i = 0; i < num_beams; i++) { for (int i = 0; i < num_beams; i++) {
uint16_t *vrb_map_UL = cc[CC_id].vrb_map_UL[i]; uint16_t *vrb_map_UL = cc[CC_id].vrb_map_UL[i];
memcpy(&vrb_map_UL[prev_slot % size * MAX_BWP_SIZE], &gNB->ulprbbl, sizeof(uint16_t) * MAX_BWP_SIZE); memcpy(&vrb_map_UL[prev_slot % size * MAX_BWP_SIZE], &gNB->ulprbbl, sizeof(uint16_t) * MAX_BWP_SIZE);
...@@ -277,14 +272,14 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_ ...@@ -277,14 +272,14 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
slot, because otherwise we would allocate the current slot in slot, because otherwise we would allocate the current slot in
UL_tti_req_ahead), but be aware that, e.g., K2 is allowed to be larger UL_tti_req_ahead), but be aware that, e.g., K2 is allowed to be larger
(schedule_nr_prach will assert if resources are not free). */ (schedule_nr_prach will assert if resources are not free). */
const sub_frame_t n_slots_ahead = nr_slots_per_frame[*scc->ssbSubcarrierSpacing] - 1 + get_NTN_Koffset(scc); const sub_frame_t n_slots_ahead = slots_frame - 1 + get_NTN_Koffset(scc);
const frame_t f = (frame + (slot + n_slots_ahead) / nr_slots_per_frame[*scc->ssbSubcarrierSpacing]) % 1024; const frame_t f = (frame + (slot + n_slots_ahead) / slots_frame) % 1024;
const sub_frame_t s = (slot + n_slots_ahead) % nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const sub_frame_t s = (slot + n_slots_ahead) % slots_frame;
schedule_nr_prach(module_idP, f, s); schedule_nr_prach(module_idP, f, s);
} }
// Schedule CSI-RS transmission // Schedule CSI-RS transmission
nr_csirs_scheduling(module_idP, frame, slot, nr_slots_per_frame[*scc->ssbSubcarrierSpacing], &sched_info->DL_req); nr_csirs_scheduling(module_idP, frame, slot, &sched_info->DL_req);
// Schedule CSI measurement reporting // Schedule CSI measurement reporting
nr_csi_meas_reporting(module_idP, frame, slot); nr_csi_meas_reporting(module_idP, frame, slot);
...@@ -313,7 +308,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_ ...@@ -313,7 +308,7 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, frame_t frame, sub_frame_
* is more than 1 CC supported? * is more than 1 CC supported?
*/ */
AssertFatal(MAX_NUM_CCs == 1, "only 1 CC supported\n"); AssertFatal(MAX_NUM_CCs == 1, "only 1 CC supported\n");
const int current_index = ul_buffer_index(frame, slot, *scc->ssbSubcarrierSpacing, gNB->UL_tti_req_ahead_size); const int current_index = ul_buffer_index(frame, slot, slots_frame, gNB->UL_tti_req_ahead_size);
copy_ul_tti_req(&sched_info->UL_tti_req, &gNB->UL_tti_req_ahead[0][current_index]); copy_ul_tti_req(&sched_info->UL_tti_req, &gNB->UL_tti_req_ahead[0][current_index]);
stop_meas(&gNB->eNB_scheduler); stop_meas(&gNB->eNB_scheduler);
......
...@@ -125,7 +125,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -125,7 +125,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
NR_COMMON_channels_t *cc= &gNB->common_channels[CC_id]; NR_COMMON_channels_t *cc= &gNB->common_channels[CC_id];
const NR_MIB_t *mib = cc->mib->message.choice.mib; const NR_MIB_t *mib = cc->mib->message.choice.mib;
NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon;
const int slots_per_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const int slots_per_frame = gNB->frame_structure.numb_slots_frame;
dl_req = &DL_req->dl_tti_request_body; dl_req = &DL_req->dl_tti_request_body;
// get MIB every 8 frames // get MIB every 8 frames
...@@ -170,7 +170,6 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -170,7 +170,6 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
const BIT_STRING_t *mediumBitmap = &scc->ssb_PositionsInBurst->choice.mediumBitmap; const BIT_STRING_t *mediumBitmap = &scc->ssb_PositionsInBurst->choice.mediumBitmap;
const BIT_STRING_t *longBitmap = &scc->ssb_PositionsInBurst->choice.longBitmap; const BIT_STRING_t *longBitmap = &scc->ssb_PositionsInBurst->choice.longBitmap;
const int n_slots_frame = nr_slots_per_frame[scs];
switch (scc->ssb_PositionsInBurst->present) { switch (scc->ssb_PositionsInBurst->present) {
case 1: case 1:
// short bitmap (<3GHz) max 4 SSBs // short bitmap (<3GHz) max 4 SSBs
...@@ -180,7 +179,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -180,7 +179,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
// if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters // if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters
if ((ssb_start_symbol / 14) == rel_slot) { if ((ssb_start_symbol / 14) == rel_slot) {
int beam_index = get_fapi_beamforming_index(gNB, i_ssb); int beam_index = get_fapi_beamforming_index(gNB, i_ssb);
NR_beam_alloc_t beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, beam_index, n_slots_frame); NR_beam_alloc_t beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, beam_index, slots_per_frame);
AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb); AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> scs; const int prb_offset = offset_pointa >> scs;
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, beam_index, ssbSubcarrierOffset, offset_pointa, mib_pdu); schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, beam_index, ssbSubcarrierOffset, offset_pointa, mib_pdu);
...@@ -212,7 +211,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -212,7 +211,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
// if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters // if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters
if ((ssb_start_symbol / 14) == rel_slot) { if ((ssb_start_symbol / 14) == rel_slot) {
int beam_index = get_fapi_beamforming_index(gNB, i_ssb); int beam_index = get_fapi_beamforming_index(gNB, i_ssb);
NR_beam_alloc_t beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, beam_index, n_slots_frame); NR_beam_alloc_t beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, beam_index, slots_per_frame);
AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb); AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> scs; const int prb_offset = offset_pointa >> scs;
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, beam_index, ssbSubcarrierOffset, offset_pointa, mib_pdu); schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, beam_index, ssbSubcarrierOffset, offset_pointa, mib_pdu);
...@@ -244,7 +243,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP, ...@@ -244,7 +243,7 @@ void schedule_nr_mib(module_id_t module_idP, frame_t frameP, sub_frame_t slotP,
// if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters // if start symbol is in current slot, schedule current SSB, fill VRB map and call get_type0_PDCCH_CSS_config_parameters
if ((ssb_start_symbol / 14) == rel_slot) { if ((ssb_start_symbol / 14) == rel_slot) {
int beam_index = get_fapi_beamforming_index(gNB, i_ssb); int beam_index = get_fapi_beamforming_index(gNB, i_ssb);
NR_beam_alloc_t beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, beam_index, n_slots_frame); NR_beam_alloc_t beam = beam_allocation_procedure(&gNB->beam_info, frameP, slotP, beam_index, slots_per_frame);
AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb); AssertFatal(beam.idx >= 0, "Cannot allocate SSB %d in any available beam\n", i_ssb);
const int prb_offset = offset_pointa >> (scs-2); // reference 60kHz const int prb_offset = offset_pointa >> (scs-2); // reference 60kHz
schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, beam_index, ssbSubcarrierOffset, offset_pointa, mib_pdu); schedule_ssb(frameP, slotP, scc, dl_req, i_ssb, beam_index, ssbSubcarrierOffset, offset_pointa, mib_pdu);
...@@ -366,7 +365,7 @@ static uint32_t schedule_control_sib1(module_id_t module_id, ...@@ -366,7 +365,7 @@ static uint32_t schedule_control_sib1(module_id_t module_id,
gNB_mac->sched_ctrlCommon->search_space = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon->search_space)); gNB_mac->sched_ctrlCommon->search_space = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon->search_space));
gNB_mac->sched_ctrlCommon->coreset = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon->coreset)); gNB_mac->sched_ctrlCommon->coreset = calloc(1,sizeof(*gNB_mac->sched_ctrlCommon->coreset));
fill_searchSpaceZero(gNB_mac->sched_ctrlCommon->search_space, fill_searchSpaceZero(gNB_mac->sched_ctrlCommon->search_space,
nr_slots_per_frame[*scc->ssbSubcarrierSpacing], gNB_mac->frame_structure.numb_slots_frame,
type0_PDCCH_CSS_config); type0_PDCCH_CSS_config);
fill_coresetZero(gNB_mac->sched_ctrlCommon->coreset, type0_PDCCH_CSS_config); fill_coresetZero(gNB_mac->sched_ctrlCommon->coreset, type0_PDCCH_CSS_config);
gNB_mac->cset0_bwp_start = type0_PDCCH_CSS_config->cset_start_rb; gNB_mac->cset0_bwp_start = type0_PDCCH_CSS_config->cset_start_rb;
...@@ -698,7 +697,7 @@ void schedule_nr_sib1(module_id_t module_idP, ...@@ -698,7 +697,7 @@ void schedule_nr_sib1(module_id_t module_idP,
(type0_PDCCH_CSS_config->num_rbs > 0) && (type0_PDCCH_CSS_config->num_rbs > 0) &&
(type0_PDCCH_CSS_config->active == true)) { (type0_PDCCH_CSS_config->active == true)) {
const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const int n_slots_frame = gNB_mac->frame_structure.numb_slots_frame;
int beam_index = get_fapi_beamforming_index(gNB_mac, i); int beam_index = get_fapi_beamforming_index(gNB_mac, i);
NR_beam_alloc_t beam = beam_allocation_procedure(&gNB_mac->beam_info, frameP, slotP, beam_index, n_slots_frame); NR_beam_alloc_t beam = beam_allocation_procedure(&gNB_mac->beam_info, frameP, slotP, beam_index, n_slots_frame);
AssertFatal(beam.idx >= 0, "Cannot allocate SIB1 corresponding to SSB %d in any available beam\n", i); AssertFatal(beam.idx >= 0, "Cannot allocate SIB1 corresponding to SSB %d in any available beam\n", i);
...@@ -846,7 +845,7 @@ void schedule_nr_sib19(module_id_t module_idP, ...@@ -846,7 +845,7 @@ void schedule_nr_sib19(module_id_t module_idP,
(slotP == ((sib19_sched_info->si_WindowPosition_r17 % window_length) - 1)) && (slotP == ((sib19_sched_info->si_WindowPosition_r17 % window_length) - 1)) &&
(type0_PDCCH_CSS_config->num_rbs > 0)) { (type0_PDCCH_CSS_config->num_rbs > 0)) {
const int n_slots_frame = nr_slots_per_frame[*scc->ssbSubcarrierSpacing]; const int n_slots_frame = gNB_mac->frame_structure.numb_slots_frame;
int beam_index = get_fapi_beamforming_index(gNB_mac, i); int beam_index = get_fapi_beamforming_index(gNB_mac, i);
NR_beam_alloc_t beam = beam_allocation_procedure(&gNB_mac->beam_info, frameP, slotP, beam_index, n_slots_frame); NR_beam_alloc_t beam = beam_allocation_procedure(&gNB_mac->beam_info, frameP, slotP, beam_index, n_slots_frame);
AssertFatal(beam.idx >= 0, "Cannot allocate SIB19 corresponding to SSB %d in any available beam\n", i); AssertFatal(beam.idx >= 0, "Cannot allocate SIB19 corresponding to SSB %d in any available beam\n", i);
......
...@@ -614,6 +614,7 @@ static void pf_dl(module_id_t module_id, ...@@ -614,6 +614,7 @@ static void pf_dl(module_id_t module_id,
remainUEs[i] = max_num_ue; remainUEs[i] = max_num_ue;
int curUE = 0; int curUE = 0;
int CC_id = 0; int CC_id = 0;
int slots_per_frame = mac->frame_structure.numb_slots_frame;
/* Loop UE_info->list to check retransmission */ /* Loop UE_info->list to check retransmission */
UE_iterator(UE_list, UE) { UE_iterator(UE_list, UE) {
...@@ -643,18 +644,14 @@ static void pf_dl(module_id_t module_id, ...@@ -643,18 +644,14 @@ static void pf_dl(module_id_t module_id,
/* retransmission */ /* retransmission */
if (sched_pdsch->dl_harq_pid >= 0) { if (sched_pdsch->dl_harq_pid >= 0) {
NR_beam_alloc_t beam = beam_allocation_procedure(&mac->beam_info, NR_beam_alloc_t beam = beam_allocation_procedure(&mac->beam_info, frame, slot, UE->UE_beam_index, slots_per_frame);
frame,
slot,
UE->UE_beam_index,
nr_slots_per_frame[current_BWP->scs]);
bool sch_ret = beam.idx >= 0; bool sch_ret = beam.idx >= 0;
/* Allocate retransmission */ /* Allocate retransmission */
if (sch_ret) if (sch_ret)
sch_ret = allocate_dl_retransmission(module_id, frame, slot, &n_rb_sched[beam.idx], UE, beam.idx, sched_pdsch->dl_harq_pid); sch_ret = allocate_dl_retransmission(module_id, frame, slot, &n_rb_sched[beam.idx], UE, beam.idx, sched_pdsch->dl_harq_pid);
if (!sch_ret) { if (!sch_ret) {
LOG_D(NR_MAC, "[UE %04x][%4d.%2d] DL retransmission could not be allocated\n", UE->rnti, frame, slot); LOG_D(NR_MAC, "[UE %04x][%4d.%2d] DL retransmission could not be allocated\n", UE->rnti, frame, slot);
reset_beam_status(&mac->beam_info, frame, slot, UE->UE_beam_index, nr_slots_per_frame[current_BWP->scs], beam.new_beam); reset_beam_status(&mac->beam_info, frame, slot, UE->UE_beam_index, slots_per_frame, beam.new_beam);
continue; continue;
} }
/* reduce max_num_ue once we are sure UE can be allocated, i.e., has CCE */ /* reduce max_num_ue once we are sure UE can be allocated, i.e., has CCE */
...@@ -737,11 +734,7 @@ static void pf_dl(module_id_t module_id, ...@@ -737,11 +734,7 @@ static void pf_dl(module_id_t module_id,
continue; continue;
} }
NR_beam_alloc_t beam = beam_allocation_procedure(&mac->beam_info, NR_beam_alloc_t beam = beam_allocation_procedure(&mac->beam_info, frame, slot, iterator->UE->UE_beam_index, slots_per_frame);
frame,
slot,
iterator->UE->UE_beam_index,
nr_slots_per_frame[dl_bwp->scs]);
if (beam.idx < 0) { if (beam.idx < 0) {
// no available beam // no available beam
...@@ -749,12 +742,7 @@ static void pf_dl(module_id_t module_id, ...@@ -749,12 +742,7 @@ static void pf_dl(module_id_t module_id,
continue; continue;
} }
if (remainUEs[beam.idx] == 0 || n_rb_sched[beam.idx] < min_rbSize) { if (remainUEs[beam.idx] == 0 || n_rb_sched[beam.idx] < min_rbSize) {
reset_beam_status(&mac->beam_info, reset_beam_status(&mac->beam_info, frame, slot, iterator->UE->UE_beam_index, slots_per_frame, beam.new_beam);
frame,
slot,
iterator->UE->UE_beam_index,
nr_slots_per_frame[dl_bwp->scs],
beam.new_beam);
iterator++; iterator++;
continue; continue;
} }
...@@ -820,12 +808,7 @@ static void pf_dl(module_id_t module_id, ...@@ -820,12 +808,7 @@ static void pf_dl(module_id_t module_id,
false); false);
if (CCEIndex < 0) { if (CCEIndex < 0) {
LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find free CCE for DL DCI\n", rnti, frame, slot); LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find free CCE for DL DCI\n", rnti, frame, slot);
reset_beam_status(&mac->beam_info, reset_beam_status(&mac->beam_info, frame, slot, iterator->UE->UE_beam_index, slots_per_frame, beam.new_beam);
frame,
slot,
iterator->UE->UE_beam_index,
nr_slots_per_frame[dl_bwp->scs],
beam.new_beam);
iterator++; iterator++;
continue; continue;
} }
...@@ -839,12 +822,7 @@ static void pf_dl(module_id_t module_id, ...@@ -839,12 +822,7 @@ static void pf_dl(module_id_t module_id,
alloc = nr_acknack_scheduling(mac, iterator->UE, frame, slot, iterator->UE->UE_beam_index, r_pucch, 0); alloc = nr_acknack_scheduling(mac, iterator->UE, frame, slot, iterator->UE->UE_beam_index, r_pucch, 0);
if (alloc < 0) { if (alloc < 0) {
LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find PUCCH for DL DCI\n", rnti, frame, slot); LOG_D(NR_MAC, "[UE %04x][%4d.%2d] could not find PUCCH for DL DCI\n", rnti, frame, slot);
reset_beam_status(&mac->beam_info, reset_beam_status(&mac->beam_info, frame, slot, iterator->UE->UE_beam_index, slots_per_frame, beam.new_beam);
frame,
slot,
iterator->UE->UE_beam_index,
nr_slots_per_frame[dl_bwp->scs],
beam.new_beam);
iterator++; iterator++;
continue; continue;
} }
...@@ -1414,11 +1392,7 @@ void nr_schedule_ue_spec(module_id_t module_id, ...@@ -1414,11 +1392,7 @@ void nr_schedule_ue_spec(module_id_t module_id,
if (sched_ctrl->ta_apply) { if (sched_ctrl->ta_apply) {
sched_ctrl->ta_apply = false; sched_ctrl->ta_apply = false;
sched_ctrl->ta_frame = frame; sched_ctrl->ta_frame = frame;
LOG_D(NR_MAC, LOG_D(NR_MAC, "%d.%2d UE %04x TA scheduled, resetting TA frame\n", frame, slot, UE->rnti);
"%d.%2d UE %04x TA scheduled, resetting TA frame\n",
frame,
slot,
UE->rnti);
} }
T(T_GNB_MAC_DL_PDU_WITH_DATA, T_INT(module_id), T_INT(CC_id), T_INT(rnti), T(T_GNB_MAC_DL_PDU_WITH_DATA, T_INT(module_id), T_INT(CC_id), T_INT(rnti),
......
...@@ -233,7 +233,6 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ ...@@ -233,7 +233,6 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP;
const int mu = ul_bwp->scs;
/* return if all UL HARQ processes wait for feedback */ /* return if all UL HARQ processes wait for feedback */
if (sched_ctrl->retrans_ul_harq.head == -1 && sched_ctrl->available_ul_harq.head == -1) { if (sched_ctrl->retrans_ul_harq.head == -1 && sched_ctrl->available_ul_harq.head == -1) {
...@@ -248,13 +247,12 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ ...@@ -248,13 +247,12 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
const int temp_tda = get_ul_tda(nr_mac, frame, slot); const int temp_tda = get_ul_tda(nr_mac, frame, slot);
if (temp_tda < 0) if (temp_tda < 0)
return false; return false;
AssertFatal(temp_tda < tdaList->list.count, AssertFatal(temp_tda < tdaList->list.count, "time domain assignment %d >= %d\n", temp_tda, tdaList->list.count);
"time domain assignment %d >= %d\n", const int mu = ul_bwp->scs;
temp_tda,
tdaList->list.count);
int K2 = get_K2(tdaList, temp_tda, mu, scc); int K2 = get_K2(tdaList, temp_tda, mu, scc);
const int sched_frame = (frame + (slot + K2) / nr_slots_per_frame[mu]) % MAX_FRAME_NUMBER; int slots_frame = nr_mac->frame_structure.numb_slots_frame;
const int sched_slot = (slot + K2) % nr_slots_per_frame[mu]; const int sched_frame = (frame + (slot + K2) / slots_frame) % MAX_FRAME_NUMBER;
const int sched_slot = (slot + K2) % slots_frame;
const int tda = get_ul_tda(nr_mac, sched_frame, sched_slot); const int tda = get_ul_tda(nr_mac, sched_frame, sched_slot);
if (tda < 0) if (tda < 0)
return false; return false;
...@@ -293,7 +291,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ ...@@ -293,7 +291,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
// TODO implement beam procedures for phy-test mode // TODO implement beam procedures for phy-test mode
int beam = 0; int beam = 0;
const int buffer_index = ul_buffer_index(sched_frame, sched_slot, mu, nr_mac->vrb_map_UL_size); const int buffer_index = ul_buffer_index(sched_frame, sched_slot, slots_frame, nr_mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[beam][buffer_index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nr_mac->common_channels[CC_id].vrb_map_UL[beam][buffer_index * MAX_BWP_SIZE];
for (int i = rbStart; i < rbStart + rbSize; ++i) { for (int i = rbStart; i < rbStart + rbSize; ++i) {
if ((vrb_map_UL[i+BWPStart] & SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols)) != 0) { if ((vrb_map_UL[i+BWPStart] & SL_to_bitmap(tda_info.startSymbolIndex, tda_info.nrOfSymbols)) != 0) {
......
...@@ -2770,12 +2770,12 @@ int get_pdsch_to_harq_feedback(NR_PUCCH_Config_t *pucch_Config, ...@@ -2770,12 +2770,12 @@ int get_pdsch_to_harq_feedback(NR_PUCCH_Config_t *pucch_Config,
} }
} }
void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slots_frame, nfapi_nr_dl_tti_request_t *DL_req) void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, nfapi_nr_dl_tti_request_t *DL_req)
{ {
int CC_id = 0; int CC_id = 0;
NR_UEs_t *UE_info = &RC.nrmac[Mod_idP]->UE_info; NR_UEs_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
gNB_MAC_INST *gNB_mac = RC.nrmac[Mod_idP]; gNB_MAC_INST *gNB_mac = RC.nrmac[Mod_idP];
int n_slots_frame = gNB_mac->frame_structure.numb_slots_frame;
NR_SCHED_ENSURE_LOCKED(&gNB_mac->sched_lock); NR_SCHED_ENSURE_LOCKED(&gNB_mac->sched_lock);
UE_info->sched_csirs = 0; UE_info->sched_csirs = 0;
...@@ -3171,9 +3171,9 @@ void nr_mac_update_timers(module_id_t module_id, ...@@ -3171,9 +3171,9 @@ void nr_mac_update_timers(module_id_t module_id,
} }
} }
int ul_buffer_index(int frame, int slot, int scs, int size) int ul_buffer_index(int frame, int slot, int slots_per_frame, int size)
{ {
const int abs_slot = frame * nr_slots_per_frame[scs] + slot; const int abs_slot = frame * slots_per_frame + slot;
return abs_slot % size; return abs_slot % size;
} }
......
...@@ -407,15 +407,16 @@ void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr ...@@ -407,15 +407,16 @@ void nr_srs_ri_computation(const nfapi_nr_srs_normalized_channel_iq_matrix_t *nr
} }
} }
static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, static void nr_configure_srs(gNB_MAC_INST *nrmac,
nfapi_nr_srs_pdu_t *srs_pdu,
int frame, int frame,
int slot, int slot,
int module_id,
int CC_id, int CC_id,
NR_UE_info_t *UE, NR_UE_info_t *UE,
NR_SRS_ResourceSet_t *srs_resource_set, NR_SRS_ResourceSet_t *srs_resource_set,
NR_SRS_Resource_t *srs_resource, NR_SRS_Resource_t *srs_resource,
int buffer_index) int buffer_index,
int slots_per_frame)
{ {
NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP; NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP;
...@@ -461,26 +462,22 @@ static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu, ...@@ -461,26 +462,22 @@ static void nr_configure_srs(nfapi_nr_srs_pdu_t *srs_pdu,
srs_pdu->srs_parameters_v4.report_type[0] = 1; srs_pdu->srs_parameters_v4.report_type[0] = 1;
srs_pdu->srs_parameters_v4.iq_representation = 1; srs_pdu->srs_parameters_v4.iq_representation = 1;
srs_pdu->srs_parameters_v4.prg_size = 1; srs_pdu->srs_parameters_v4.prg_size = 1;
srs_pdu->srs_parameters_v4.num_total_ue_antennas = 1<<srs_pdu->num_ant_ports; srs_pdu->srs_parameters_v4.num_total_ue_antennas = 1 << srs_pdu->num_ant_ports;
if (srs_resource_set->usage == NR_SRS_ResourceSet__usage_beamManagement) { if (srs_resource_set->usage == NR_SRS_ResourceSet__usage_beamManagement) {
srs_pdu->beamforming.trp_scheme = 0; srs_pdu->beamforming.trp_scheme = 0;
srs_pdu->beamforming.num_prgs = m_SRS[srs_pdu->config_index]; srs_pdu->beamforming.num_prgs = m_SRS[srs_pdu->config_index];
srs_pdu->beamforming.prg_size = 1; srs_pdu->beamforming.prg_size = 1;
} }
srs_pdu->beamforming.prgs_list[0].dig_bf_interface_list[0].beam_idx = UE->UE_beam_index; srs_pdu->beamforming.prgs_list[0].dig_bf_interface_list[0].beam_idx = UE->UE_beam_index;
NR_beam_alloc_t beam = beam_allocation_procedure(&RC.nrmac[module_id]->beam_info, NR_beam_alloc_t beam = beam_allocation_procedure(&nrmac->beam_info, frame, slot, UE->UE_beam_index, slots_per_frame);
frame,
slot,
UE->UE_beam_index,
nr_slots_per_frame[current_BWP->scs]);
AssertFatal(beam.idx >= 0, "Cannot allocate SRS in any available beam\n"); AssertFatal(beam.idx >= 0, "Cannot allocate SRS in any available beam\n");
uint16_t *vrb_map_UL = &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[beam.idx][buffer_index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nrmac->common_channels[CC_id].vrb_map_UL[beam.idx][buffer_index * MAX_BWP_SIZE];
uint64_t mask = SL_to_bitmap(srs_pdu->time_start_position, srs_pdu->num_symbols); uint64_t mask = SL_to_bitmap(srs_pdu->time_start_position, srs_pdu->num_symbols);
for (int i = 0; i < srs_pdu->bwp_size; ++i) for (int i = 0; i < srs_pdu->bwp_size; ++i)
vrb_map_UL[i + srs_pdu->bwp_start] |= mask; vrb_map_UL[i + srs_pdu->bwp_start] |= mask;
} }
static void nr_fill_nfapi_srs(int module_id, static void nr_fill_nfapi_srs(gNB_MAC_INST *nrmac,
int CC_id, int CC_id,
NR_UE_info_t *UE, NR_UE_info_t *UE,
int frame, int frame,
...@@ -488,9 +485,9 @@ static void nr_fill_nfapi_srs(int module_id, ...@@ -488,9 +485,9 @@ static void nr_fill_nfapi_srs(int module_id,
NR_SRS_ResourceSet_t *srs_resource_set, NR_SRS_ResourceSet_t *srs_resource_set,
NR_SRS_Resource_t *srs_resource) NR_SRS_Resource_t *srs_resource)
{ {
int slots_frame = nrmac->frame_structure.numb_slots_frame;
int index = ul_buffer_index(frame, slot, UE->current_UL_BWP.scs, RC.nrmac[module_id]->UL_tti_req_ahead_size); int index = ul_buffer_index(frame, slot, slots_frame, nrmac->UL_tti_req_ahead_size);
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &RC.nrmac[module_id]->UL_tti_req_ahead[0][index]; nfapi_nr_ul_tti_request_t *future_ul_tti_req = &nrmac->UL_tti_req_ahead[0][index];
AssertFatal(future_ul_tti_req->n_pdus < AssertFatal(future_ul_tti_req->n_pdus <
sizeof(future_ul_tti_req->pdus_list) / sizeof(future_ul_tti_req->pdus_list[0]), sizeof(future_ul_tti_req->pdus_list) / sizeof(future_ul_tti_req->pdus_list[0]),
"Invalid future_ul_tti_req->n_pdus %d\n", future_ul_tti_req->n_pdus); "Invalid future_ul_tti_req->n_pdus %d\n", future_ul_tti_req->n_pdus);
...@@ -499,8 +496,8 @@ static void nr_fill_nfapi_srs(int module_id, ...@@ -499,8 +496,8 @@ static void nr_fill_nfapi_srs(int module_id,
nfapi_nr_srs_pdu_t *srs_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].srs_pdu; nfapi_nr_srs_pdu_t *srs_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].srs_pdu;
memset(srs_pdu, 0, sizeof(nfapi_nr_srs_pdu_t)); memset(srs_pdu, 0, sizeof(nfapi_nr_srs_pdu_t));
future_ul_tti_req->n_pdus += 1; future_ul_tti_req->n_pdus += 1;
index = ul_buffer_index(frame, slot, UE->current_UL_BWP.scs, RC.nrmac[module_id]->vrb_map_UL_size); index = ul_buffer_index(frame, slot, slots_frame, nrmac->vrb_map_UL_size);
nr_configure_srs(srs_pdu, frame, slot, module_id, CC_id, UE, srs_resource_set, srs_resource, index); nr_configure_srs(nrmac, srs_pdu, frame, slot, CC_id, UE, srs_resource_set, srs_resource, index, slots_frame);
} }
/******************************************************************* /*******************************************************************
...@@ -583,7 +580,7 @@ void nr_schedule_srs(int module_id, frame_t frame, int slot) ...@@ -583,7 +580,7 @@ void nr_schedule_srs(int module_id, frame_t frame, int slot)
} }
// we are sheduling SRS max_k2 slot in advance for the presence of SRS to be taken into account when scheduling PUSCH // we are sheduling SRS max_k2 slot in advance for the presence of SRS to be taken into account when scheduling PUSCH
const int n_slots_frame = nr_slots_per_frame[current_BWP->scs]; const int n_slots_frame = nrmac->frame_structure.numb_slots_frame;
const int sched_slot = (slot + max_k2) % n_slots_frame; const int sched_slot = (slot + max_k2) % n_slots_frame;
const int sched_frame = (frame + (slot + max_k2) / n_slots_frame) % MAX_FRAME_NUMBER; const int sched_frame = (frame + (slot + max_k2) / n_slots_frame) % MAX_FRAME_NUMBER;
...@@ -593,7 +590,7 @@ void nr_schedule_srs(int module_id, frame_t frame, int slot) ...@@ -593,7 +590,7 @@ void nr_schedule_srs(int module_id, frame_t frame, int slot)
// Check if UE will transmit the SRS in this frame // Check if UE will transmit the SRS in this frame
if ((sched_frame * n_slots_frame + sched_slot - offset) % period == 0) { if ((sched_frame * n_slots_frame + sched_slot - offset) % period == 0) {
LOG_D(NR_MAC," %d.%d Scheduling SRS reception for %d.%d\n", frame, slot, sched_frame, sched_slot); LOG_D(NR_MAC," %d.%d Scheduling SRS reception for %d.%d\n", frame, slot, sched_frame, sched_slot);
nr_fill_nfapi_srs(module_id, CC_id, UE, sched_frame, sched_slot, srs_resource_set, srs_resource); nr_fill_nfapi_srs(nrmac, CC_id, UE, sched_frame, sched_slot, srs_resource_set, srs_resource);
sched_ctrl->sched_srs.frame = sched_frame; sched_ctrl->sched_srs.frame = sched_frame;
sched_ctrl->sched_srs.slot = sched_slot; sched_ctrl->sched_srs.slot = sched_slot;
sched_ctrl->sched_srs.srs_scheduled = true; sched_ctrl->sched_srs.srs_scheduled = true;
......
...@@ -40,10 +40,13 @@ static void nr_fill_nfapi_pucch(gNB_MAC_INST *nrmac, ...@@ -40,10 +40,13 @@ static void nr_fill_nfapi_pucch(gNB_MAC_INST *nrmac,
NR_UE_info_t* UE) NR_UE_info_t* UE)
{ {
const int index = ul_buffer_index(pucch->frame, pucch->ul_slot, UE->current_UL_BWP.scs, nrmac->UL_tti_req_ahead_size); const int index = ul_buffer_index(pucch->frame,
pucch->ul_slot,
nrmac->frame_structure.numb_slots_frame,
nrmac->UL_tti_req_ahead_size);
nfapi_nr_ul_tti_request_t *future_ul_tti_req = &nrmac->UL_tti_req_ahead[0][index]; nfapi_nr_ul_tti_request_t *future_ul_tti_req = &nrmac->UL_tti_req_ahead[0][index];
if (future_ul_tti_req->SFN != pucch->frame || future_ul_tti_req->Slot != pucch->ul_slot) if (future_ul_tti_req->SFN != pucch->frame || future_ul_tti_req->Slot != pucch->ul_slot)
LOG_W(MAC, LOG_W(NR_MAC,
"Current %d.%d : future UL_tti_req's frame.slot %4d.%2d does not match PUCCH %4d.%2d\n", "Current %d.%d : future UL_tti_req's frame.slot %4d.%2d does not match PUCCH %4d.%2d\n",
frame,slot, frame,slot,
future_ul_tti_req->SFN, future_ul_tti_req->SFN,
...@@ -53,8 +56,11 @@ static void nr_fill_nfapi_pucch(gNB_MAC_INST *nrmac, ...@@ -53,8 +56,11 @@ static void nr_fill_nfapi_pucch(gNB_MAC_INST *nrmac,
// n_pdus is number of pdus, so, in the array, it is the index of the next free element // n_pdus is number of pdus, so, in the array, it is the index of the next free element
if (future_ul_tti_req->n_pdus >= sizeofArray(future_ul_tti_req->pdus_list) ) { if (future_ul_tti_req->n_pdus >= sizeofArray(future_ul_tti_req->pdus_list) ) {
LOG_E(NR_MAC,"future_ul_tti_req->n_pdus %d is full, slot: %d, sr flag %d dropping request\n", LOG_E(NR_MAC,
future_ul_tti_req->n_pdus, pucch->ul_slot, pucch->sr_flag); "future_ul_tti_req->n_pdus %d is full, slot: %d, sr flag %d dropping request\n",
future_ul_tti_req->n_pdus,
pucch->ul_slot,
pucch->sr_flag);
return; return;
} }
future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE; future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE;
...@@ -77,8 +83,14 @@ static void nr_fill_nfapi_pucch(gNB_MAC_INST *nrmac, ...@@ -77,8 +83,14 @@ static void nr_fill_nfapi_pucch(gNB_MAC_INST *nrmac,
NR_COMMON_channels_t * common_ch=nrmac->common_channels; NR_COMMON_channels_t * common_ch=nrmac->common_channels;
NR_ServingCellConfigCommon_t *scc = common_ch->ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = common_ch->ServingCellConfigCommon;
LOG_D(NR_MAC,"%4d.%2d Calling nr_configure_pucch (pucch_Config %p,r_pucch %d) pucch to be scheduled in %4d.%2d\n", LOG_D(NR_MAC,
frame,slot,UE->current_UL_BWP.pucch_Config,pucch->r_pucch,pucch->frame,pucch->ul_slot); "%4d.%2d Calling nr_configure_pucch (pucch_Config %p,r_pucch %d) pucch to be scheduled in %4d.%2d\n",
frame,
slot,
UE->current_UL_BWP.pucch_Config,
pucch->r_pucch,
pucch->frame,
pucch->ul_slot);
nr_configure_pucch(pucch_pdu, nr_configure_pucch(pucch_pdu,
scc, scc,
...@@ -213,7 +225,7 @@ void nr_csi_meas_reporting(int Mod_idP,frame_t frame, sub_frame_t slot) ...@@ -213,7 +225,7 @@ void nr_csi_meas_reporting(int Mod_idP,frame_t frame, sub_frame_t slot)
UE_iterator(nrmac->UE_info.list, UE ) { UE_iterator(nrmac->UE_info.list, UE ) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP;
const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; const int n_slots_frame = nrmac->frame_structure.numb_slots_frame;
if (nr_timer_is_active(&sched_ctrl->transm_interrupt) || (sched_ctrl->ul_failure && !get_softmodem_params()->phy_test)) { if (nr_timer_is_active(&sched_ctrl->transm_interrupt) || (sched_ctrl->ul_failure && !get_softmodem_params()->phy_test)) {
continue; continue;
} }
...@@ -270,7 +282,7 @@ void nr_csi_meas_reporting(int Mod_idP,frame_t frame, sub_frame_t slot) ...@@ -270,7 +282,7 @@ void nr_csi_meas_reporting(int Mod_idP,frame_t frame, sub_frame_t slot)
// going through the list of PUCCH resources to find the one indexed by resource_id // going through the list of PUCCH resources to find the one indexed by resource_id
NR_beam_alloc_t beam = beam_allocation_procedure(&nrmac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, n_slots_frame); NR_beam_alloc_t beam = beam_allocation_procedure(&nrmac->beam_info, sched_frame, sched_slot, UE->UE_beam_index, n_slots_frame);
AssertFatal(beam.idx >= 0, "Cannot allocate CSI measurements on PUCCH in any available beam\n"); AssertFatal(beam.idx >= 0, "Cannot allocate CSI measurements on PUCCH in any available beam\n");
const int index = ul_buffer_index(sched_frame, sched_slot, ul_bwp->scs, nrmac->vrb_map_UL_size); const int index = ul_buffer_index(sched_frame, sched_slot, n_slots_frame, nrmac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nrmac->common_channels[0].vrb_map_UL[beam.idx][index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nrmac->common_channels[0].vrb_map_UL[beam.idx][index * MAX_BWP_SIZE];
const int m = pucch_Config->resourceToAddModList->list.count; const int m = pucch_Config->resourceToAddModList->list.count;
for (int j = 0; j < m; j++) { for (int j = 0; j < m; j++) {
...@@ -623,10 +635,10 @@ static void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig, ...@@ -623,10 +635,10 @@ static void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig,
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP;
NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP;
const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; const int n_slots_frame = nrmac->frame_structure.numb_slots_frame;
int cumul_bits = 0; int cumul_bits = 0;
int r_index = -1; int r_index = -1;
for (int csi_report_id = 0; csi_report_id < csi_MeasConfig->csi_ReportConfigToAddModList->list.count; csi_report_id++ ) { for (int csi_report_id = 0; csi_report_id < csi_MeasConfig->csi_ReportConfigToAddModList->list.count; csi_report_id++) {
nr_csi_report_t *csi_report = &UE->csi_report_template[csi_report_id]; nr_csi_report_t *csi_report = &UE->csi_report_template[csi_report_id];
csi_report->nb_of_csi_ssb_report = 0; csi_report->nb_of_csi_ssb_report = 0;
uint8_t cri_bitlen = 0; uint8_t cri_bitlen = 0;
...@@ -1002,7 +1014,7 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac, ...@@ -1002,7 +1014,7 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
const int minfbtime = mac->radio_config.minRXTXTIME + NTN_gNB_Koffset; const int minfbtime = mac->radio_config.minRXTXTIME + NTN_gNB_Koffset;
const NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; const NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP;
const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; const int n_slots_frame = mac->frame_structure.numb_slots_frame;
const frame_structure_t *fs = &mac->frame_structure; const frame_structure_t *fs = &mac->frame_structure;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
...@@ -1089,7 +1101,7 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac, ...@@ -1089,7 +1101,7 @@ int nr_acknack_scheduling(gNB_MAC_INST *mac,
pucch_slot); pucch_slot);
continue; continue;
} }
const int index = ul_buffer_index(pucch_frame, pucch_slot, ul_bwp->scs, mac->vrb_map_UL_size); const int index = ul_buffer_index(pucch_frame, pucch_slot, n_slots_frame, mac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[beam.idx][index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &mac->common_channels[CC_id].vrb_map_UL[beam.idx][index * MAX_BWP_SIZE];
bool ret = test_pucch0_vrb_occupation(curr_pucch, vrb_map_UL, bwp_start, bwp_size); bool ret = test_pucch0_vrb_occupation(curr_pucch, vrb_map_UL, bwp_start, bwp_size);
if(!ret) { if(!ret) {
...@@ -1136,7 +1148,7 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot) ...@@ -1136,7 +1148,7 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot)
UE_iterator(nrmac->UE_info.list, UE) { UE_iterator(nrmac->UE_info.list, UE) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP;
const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; const int n_slots_frame = nrmac->frame_structure.numb_slots_frame;
if (sched_ctrl->ul_failure || nr_timer_is_active(&sched_ctrl->transm_interrupt)) if (sched_ctrl->ul_failure || nr_timer_is_active(&sched_ctrl->transm_interrupt))
continue; continue;
NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config; NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config;
...@@ -1187,7 +1199,7 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot) ...@@ -1187,7 +1199,7 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot)
else { else {
NR_beam_alloc_t beam = beam_allocation_procedure(&nrmac->beam_info, SFN, slot, UE->UE_beam_index, n_slots_frame); NR_beam_alloc_t beam = beam_allocation_procedure(&nrmac->beam_info, SFN, slot, UE->UE_beam_index, n_slots_frame);
AssertFatal(beam.idx >= 0, "Cannot allocate SR in any available beam\n"); AssertFatal(beam.idx >= 0, "Cannot allocate SR in any available beam\n");
const int index = ul_buffer_index(SFN, slot, ul_bwp->scs, nrmac->vrb_map_UL_size); const int index = ul_buffer_index(SFN, slot, n_slots_frame, nrmac->vrb_map_UL_size);
uint16_t *vrb_map_UL = &nrmac->common_channels[CC_id].vrb_map_UL[beam.idx][index * MAX_BWP_SIZE]; uint16_t *vrb_map_UL = &nrmac->common_channels[CC_id].vrb_map_UL[beam.idx][index * MAX_BWP_SIZE];
const int bwp_start = ul_bwp->BWPStart; const int bwp_start = ul_bwp->BWPStart;
const int bwp_size = ul_bwp->BWPSize; const int bwp_size = ul_bwp->BWPSize;
......
...@@ -191,11 +191,9 @@ int get_pucch_resourceid(NR_PUCCH_Config_t *pucch_Config, int O_uci, int pucch_r ...@@ -191,11 +191,9 @@ int get_pucch_resourceid(NR_PUCCH_Config_t *pucch_Config, int O_uci, int pucch_r
void nr_schedule_srs(int module_id, frame_t frame, int slot); void nr_schedule_srs(int module_id, frame_t frame, int slot);
void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, int n_slots_frame, nfapi_nr_dl_tti_request_t *DL_req); void nr_csirs_scheduling(int Mod_idP, frame_t frame, sub_frame_t slot, nfapi_nr_dl_tti_request_t *DL_req);
void nr_csi_meas_reporting(int Mod_idP, void nr_csi_meas_reporting(int Mod_idP, frame_t frameP, sub_frame_t slotP);
frame_t frameP,
sub_frame_t slotP);
int nr_acknack_scheduling(gNB_MAC_INST *mac, int nr_acknack_scheduling(gNB_MAC_INST *mac,
NR_UE_info_t *UE, NR_UE_info_t *UE,
...@@ -453,7 +451,7 @@ int get_mcs_from_bler(const NR_bler_options_t *bler_options, ...@@ -453,7 +451,7 @@ int get_mcs_from_bler(const NR_bler_options_t *bler_options,
int max_mcs, int max_mcs,
frame_t frame); frame_t frame);
int ul_buffer_index(int frame, int slot, int scs, int size); int ul_buffer_index(int frame, int slot, int slots_per_frame, int size);
void UL_tti_req_ahead_initialization(gNB_MAC_INST *gNB, int n, int CCid, frame_t frameP, int slotP); void UL_tti_req_ahead_initialization(gNB_MAC_INST *gNB, int n, int CCid, frame_t frameP, int slotP);
void fapi_beam_index_allocation(NR_ServingCellConfigCommon_t *scc, gNB_MAC_INST *mac); void fapi_beam_index_allocation(NR_ServingCellConfigCommon_t *scc, gNB_MAC_INST *mac);
......
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