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Michael Black
OpenXG UE
Commits
09af43b3
Commit
09af43b3
authored
Sep 26, 2018
by
Guy De Souza
Browse files
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Browse Files
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Plain Diff
Merge branch 'nr_pdsch' of
https://gitlab.eurecom.fr/oai/openairinterface5g
into nr_pdsch
parents
4810d7a5
d1fb8e83
Changes
6
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Showing
6 changed files
with
889 additions
and
28 deletions
+889
-28
openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
+364
-1
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
+413
-0
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
+9
-5
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
+61
-9
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
+17
-10
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+25
-3
No files found.
openair1/PHY/NR_TRANSPORT/nr_dci_tools.c
View file @
09af43b3
...
...
@@ -121,7 +121,8 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
nfapi_nr_config_request_t
*
cfg
=
&
gNB
->
gNB_config
;
uint16_t
N_RB
=
fp
->
initial_bwp_dl
.
N_RB
;
uint8_t
fsize
=
0
,
pos
=
0
,
cand_idx
=
0
;
uint16_t
N_RB_UL
=
fp
->
initial_bwp_ul
.
N_RB
;
uint8_t
fsize
=
0
,
pos
=
0
,
pos2
=
0
,
cand_idx
=
0
;
/// Payload generation
switch
(
params_rel15
->
dci_format
)
{
...
...
@@ -131,6 +132,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
case
NFAPI_NR_RNTI_RA
:
// Freq domain assignment
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
printf
(
"fsize = %d
\n
"
,
fsize
);
for
(
int
i
=
0
;
i
<
fsize
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
>>
(
fsize
-
i
-
1
))
&
1
)
<<
pos
++
;
// Time domain assignment
...
...
@@ -144,14 +146,375 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// TB scaling
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
tb_scaling
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
printf
(
"***************************
\n
"
);
break
;
case
NFAPI_NR_RNTI_C
:
// indicating a DL DCI format 1bit
*
dci_pdu
|=
(
pdu_rel15
->
format_indicator
&
1
)
<<
pos
++
;
// Freq domain assignment (275rb >> fsize = 16)
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
for
(
int
i
=
0
;
i
<
fsize
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
>>
(
fsize
-
i
-
1
))
&
1
)
<<
pos
++
;
printf
(
"fsize = %d
\n
"
,
fsize
);
printf
(
"NFAPI_NR_RNTI_C
\n
"
);
if
((
pdu_rel15
->
frequency_domain_assignment
+
1
)
&
1
==
0
)
//fsize are all 1 38.212 p86
{
printf
(
"***************************
\n
"
);
// ra_preamble_index 6bit
for
(
int
i
=
0
;
i
<
6
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
ra_preamble_index
>>
(
5
-
i
-
1
))
&
1
)
<<
pos
++
;
// UL/SUL indicator 1bit
*
dci_pdu
|=
(
pdu_rel15
->
ul_sul_indicator
&
1
)
<<
pos
++
;
// SS/PBCH index 6bit
for
(
int
i
=
0
;
i
<
6
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
ss_pbch_index
>>
(
5
-
i
))
&
1
)
<<
pos
++
;
// prach_mask_index "2"+2bit // cause it 32bit and bit over 32 ,so dci_pdu ++
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
prach_mask_index
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
//--------------------------dci_pdu ++------------------------------
// prach_mask_index 2+"2"bit //
for
(
int
i
=
2
;
i
<
4
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
prach_mask_index
>>
(
3
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
prach_mask_index
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
}
}
//end if
else
{
// Time domain assignment 4bit
for
(
int
i
=
0
;
i
<
4
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// VRB to PRB mapping 1bit
*
dci_pdu
|=
(
pdu_rel15
->
vrb_to_prb_mapping
&
1
)
<<
pos
++
;
// MCS 5bit //bit over 32, so dci_pdu ++
for
(
int
i
=
0
;
i
<
5
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos
++
;
// New data indicator 1bit
*
dci_pdu
|=
(
pdu_rel15
->
ndi
&
1
)
<<
pos
++
;
// Redundancy version 2bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
rv
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
// HARQ process number 4bit "2"+2
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
//--------------------------dci_pdu ++------------------------------
// HARQ process number 4bit 2+"2"
for
(
int
i
=
2
;
i
<
4
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
}
// Downlink assignment index 2bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
dai
>>
(
1
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
dai
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
}
// TPC command for scheduled PUCCH 2bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
}
// PUCCH resource indicator 3bit
for
(
int
i
=
0
;
i
<
3
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
pucch_resource_indicator
>>
(
2
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
pucch_resource_indicator
>>
(
2
-
i
))
&
1
)
<<
pos
++
;
}
// PDSCH-to-HARQ_feedback timing indicator 3bit
for
(
int
i
=
0
;
i
<
3
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
>>
(
2
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
>>
(
2
-
i
))
&
1
)
<<
pos
++
;
}
}
//end else
break
;
case
NFAPI_NR_RNTI_P
:
// Short Messages Indicator – 2 bits
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
short_messages_indicator
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
// Short Messages – 8 bits
for
(
int
i
=
0
;
i
<
8
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
short_messages
>>
(
7
-
i
))
&
1
)
<<
pos
++
;
// Freq domain assignment 0-16 bit
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
for
(
int
i
=
0
;
i
<
fsize
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
>>
(
fsize
-
i
-
1
))
&
1
)
<<
pos
++
;
// Time domain assignment 4 bit
for
(
int
i
=
0
;
i
<
4
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// VRB to PRB mapping 1 bit
*
dci_pdu
|=
(
pdu_rel15
->
vrb_to_prb_mapping
&
1
)
<<
pos
++
;
// MCS "1"+4 = 5 bit
for
(
int
i
=
0
;
i
<
1
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos
++
;
// MCS 1+"4" = 5 bit
for
(
int
i
=
1
;
i
<
4
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos
++
;
}
// TB scaling 2 bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
tb_scaling
>>
(
1
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
tb_scaling
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
}
break
;
case
NFAPI_NR_RNTI_SI
:
// Freq domain assignment 0-16 bit
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
for
(
int
i
=
0
;
i
<
fsize
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
>>
(
fsize
-
i
-
1
))
&
1
)
<<
pos
++
;
// Time domain assignment 4 bit
for
(
int
i
=
0
;
i
<
4
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// VRB to PRB mapping 1 bit
*
dci_pdu
|=
(
pdu_rel15
->
vrb_to_prb_mapping
&
1
)
<<
pos
++
;
// MCS 5bit //bit over 32, so dci_pdu ++
for
(
int
i
=
0
;
i
<
5
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos
++
;
// Redundancy version 2bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
rv
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
break
;
case
NFAPI_NR_RNTI_TC
:
// indicating a DL DCI format 1bit
*
dci_pdu
|=
(
pdu_rel15
->
format_indicator
&
1
)
<<
pos
++
;
// Freq domain assignment 0-16 bit
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
for
(
int
i
=
0
;
i
<
fsize
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
>>
(
fsize
-
i
-
1
))
&
1
)
<<
pos
++
;
// Time domain assignment 4 bit
for
(
int
i
=
0
;
i
<
4
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// VRB to PRB mapping 1 bit
*
dci_pdu
|=
(
pdu_rel15
->
vrb_to_prb_mapping
&
1
)
<<
pos
++
;
// MCS 5bit //bit over 32, so dci_pdu ++
for
(
int
i
=
0
;
i
<
5
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos
++
;
// New data indicator 1bit
*
dci_pdu
|=
(
pdu_rel15
->
ndi
&
1
)
<<
pos
++
;
// Redundancy version 2bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
rv
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
// HARQ process number 4bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// HARQ process number 4bit
for
(
int
i
=
2
;
i
<
4
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
}
// Downlink assignment index – 2 bits
for
(
int
i
=
0
;
i
<
2
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
dai
>>
(
1
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
dai
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
}
// TPC command for scheduled PUCCH – 2 bits
for
(
int
i
=
0
;
i
<
2
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
}
// PUCCH resource indicator – 3 bits
for
(
int
i
=
0
;
i
<
3
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
pucch_resource_indicator
>>
(
2
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
pucch_resource_indicator
>>
(
2
-
i
))
&
1
)
<<
pos
++
;
}
// PDSCH-to-HARQ_feedback timing indicator – 3 bits
for
(
int
i
=
0
;
i
<
3
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
>>
(
2
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
>>
(
2
-
i
))
&
1
)
<<
pos
++
;
}
///-----------------------------------?????????????????????------------------------
break
;
}
break
;
case
NFAPI_NR_UL_DCI_FORMAT_0_0
:
switch
(
params_rel15
->
rnti_type
)
{
case
NFAPI_NR_RNTI_C
:
// indicating a DL DCI format 1bit
*
dci_pdu
|=
(
pdu_rel15
->
format_indicator
&
1
)
<<
pos
++
;
// Freq domain assignment max 16 bit
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB_UL
*
(
N_RB_UL
+
1
))
>>
1
)
);
for
(
int
i
=
0
;
i
<
fsize
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
>>
(
fsize
-
i
-
1
))
&
1
)
<<
pos
++
;
// Time domain assignment 4bit
for
(
int
i
=
0
;
i
<
4
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// Frequency hopping flag – 1 bit
*
dci_pdu
|=
(
pdu_rel15
->
frequency_hopping_flag
&
1
)
<<
pos
++
;
// MCS 5 bit
for
(
int
i
=
0
;
i
<
5
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos
++
;
// New data indicator 1bit
*
dci_pdu
|=
(
pdu_rel15
->
ndi
&
1
)
<<
pos
++
;
// Redundancy version 2bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
rv
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
// HARQ process number 4bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// HARQ process number 4bit
for
(
int
i
=
2
;
i
<
4
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
}
// TPC command for scheduled PUSCH – 2 bits
for
(
int
i
=
0
;
i
<
2
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
}
// Padding bits
if
(
pos
<
32
)
{
for
(
int
a
=
pos
;
a
<
32
;
a
++
)
*
dci_pdu
|=
(
pdu_rel15
->
padding
&
1
)
<<
pos
++
;
}
// UL/SUL indicator – 1 bit
if
(
cfg
->
pucch_config
.
pucch_GroupHopping
.
value
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
(
pdu_rel15
->
ul_sul_indicator
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
(
pdu_rel15
->
ul_sul_indicator
&
1
)
<<
pos
++
;
}
break
;
case
NFAPI_NR_RNTI_TC
:
// indicating a DL DCI format 1bit
*
dci_pdu
|=
(
pdu_rel15
->
format_indicator
&
1
)
<<
pos
++
;
// Freq domain assignment max 16 bit
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB_UL
*
(
N_RB_UL
+
1
))
>>
1
)
);
for
(
int
i
=
0
;
i
<
fsize
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
frequency_domain_assignment
>>
(
fsize
-
i
-
1
))
&
1
)
<<
pos
++
;
// Time domain assignment 4bit
for
(
int
i
=
0
;
i
<
4
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
time_domain_assignment
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// Frequency hopping flag – 1 bit
*
dci_pdu
|=
(
pdu_rel15
->
frequency_hopping_flag
&
1
)
<<
pos
++
;
// MCS 5 bit
for
(
int
i
=
0
;
i
<
5
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
mcs
>>
(
4
-
i
))
&
1
)
<<
pos
++
;
// New data indicator 1bit
*
dci_pdu
|=
(
pdu_rel15
->
ndi
&
1
)
<<
pos
++
;
// Redundancy version 2bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
rv
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
// HARQ process number 4bit
for
(
int
i
=
0
;
i
<
2
;
i
++
)
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
// HARQ process number 4bit
for
(
int
i
=
2
;
i
<
4
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
harq_pid
>>
(
3
-
i
))
&
1
)
<<
pos
++
;
}
// TPC command for scheduled PUSCH – 2 bits
for
(
int
i
=
0
;
i
<
2
;
i
++
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
((
pdu_rel15
->
tpc
>>
(
1
-
i
))
&
1
)
<<
pos
++
;
}
// Padding bits
if
(
pos
<
32
)
{
for
(
int
a
=
pos
;
a
<
32
;
a
++
)
*
dci_pdu
|=
(
pdu_rel15
->
padding
&
1
)
<<
pos
++
;
}
// UL/SUL indicator – 1 bit
if
(
cfg
->
pucch_config
.
pucch_GroupHopping
.
value
)
{
if
(
pos
>
31
)
*
(
dci_pdu
+
1
)
|=
(
pdu_rel15
->
ul_sul_indicator
&
1
)
<<
pos2
++
;
else
*
dci_pdu
|=
(
pdu_rel15
->
ul_sul_indicator
&
1
)
<<
pos
++
;
}
break
;
}
break
;
}
LOG_I
(
PHY
,
"DCI PDU: [0]->0x%08x
\t
[1]->0x%08x
\t
[2]->0x%08x
\t
[3]->0x%08x
\n
"
,
dci_pdu
[
0
],
dci_pdu
[
1
],
dci_pdu
[
2
],
dci_pdu
[
3
]);
...
...
openair1/PHY/NR_TRANSPORT/nr_dlsch_coding.c
0 → 100644
View file @
09af43b3
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file PHY/LTE_TRANSPORT/dlsch_coding.c
* \brief Top-level routines for implementing LDPC-coded (DLSCH) transport channels from 38-212, 15.2
* \author H.Wang
* \date 2018
* \version 0.1
* \company Eurecom
* \email:
* \note
* \warning
*/
#include "PHY/defs_gNB.h"
#include "PHY/phy_extern.h"
#include "PHY/CODING/coding_extern.h"
#include "PHY/CODING/coding_defs.h"
#include "PHY/CODING/lte_interleaver_inline.h"
#include "PHY/NR_TRANSPORT/nr_transport.h"
#include "PHY/NR_TRANSPORT/nr_transport_common_proto.h"
#include "SCHED_NR/sched_nr.h"
#include "defs.h"
#include "UTIL/LOG/vcd_signal_dumper.h"
#include "UTIL/LOG/log.h"
#include <syscall.h>
//#define DEBUG_DLSCH_CODING
//#define DEBUG_DLSCH_FREE 1
void
free_gNB_dlsch
(
NR_gNB_DLSCH_t
*
dlsch
)
{
int
i
;
int
r
;
if
(
dlsch
)
{
#ifdef DEBUG_DLSCH_FREE
printf
(
"Freeing dlsch %p
\n
"
,
dlsch
);
#endif
for
(
i
=
0
;
i
<
dlsch
->
Mdlharq
;
i
++
)
{
#ifdef DEBUG_DLSCH_FREE
printf
(
"Freeing dlsch process %d
\n
"
,
i
);
#endif
if
(
dlsch
->
harq_processes
[
i
])
{
#ifdef DEBUG_DLSCH_FREE
printf
(
"Freeing dlsch process %d (%p)
\n
"
,
i
,
dlsch
->
harq_processes
[
i
]);
#endif
if
(
dlsch
->
harq_processes
[
i
]
->
b
)
{
free16
(
dlsch
->
harq_processes
[
i
]
->
b
,
MAX_DLSCH_PAYLOAD_BYTES
);
dlsch
->
harq_processes
[
i
]
->
b
=
NULL
;
#ifdef DEBUG_DLSCH_FREE
printf
(
"Freeing dlsch process %d b (%p)
\n
"
,
i
,
dlsch
->
harq_processes
[
i
]
->
b
);
#endif
}
#ifdef DEBUG_DLSCH_FREE
printf
(
"Freeing dlsch process %d c (%p)
\n
"
,
i
,
dlsch
->
harq_processes
[
i
]
->
c
);
#endif
for
(
r
=
0
;
r
<
MAX_NUM_DLSCH_SEGMENTS
;
r
++
)
{
#ifdef DEBUG_DLSCH_FREE
printf
(
"Freeing dlsch process %d c[%d] (%p)
\n
"
,
i
,
r
,
dlsch
->
harq_processes
[
i
]
->
c
[
r
]);
#endif
if
(
dlsch
->
harq_processes
[
i
]
->
c
[
r
])
{
free16
(
dlsch
->
harq_processes
[
i
]
->
c
[
r
],((
r
==
0
)
?
8
:
0
)
+
3
+
1056
);
dlsch
->
harq_processes
[
i
]
->
c
[
r
]
=
NULL
;
}
if
(
dlsch
->
harq_processes
[
i
]
->
d
[
r
])
{
free16
(
dlsch
->
harq_processes
[
i
]
->
d
[
r
],(
96
+
12
+
3
+
(
3
*
8448
)));
dlsch
->
harq_processes
[
i
]
->
d
[
r
]
=
NULL
;
}
}
free16
(
dlsch
->
harq_processes
[
i
],
sizeof
(
NR_DL_gNB_HARQ_t
));
dlsch
->
harq_processes
[
i
]
=
NULL
;
}
}
free16
(
dlsch
,
sizeof
(
NR_gNB_DLSCH_t
));
dlsch
=
NULL
;
}
}
NR_gNB_DLSCH_t
*
new_gNB_dlsch
(
unsigned
char
Kmimo
,
unsigned
char
Mdlharq
,
uint32_t
Nsoft
,
unsigned
char
N_RB_DL
,
uint8_t
abstraction_flag
,
NR_DL_FRAME_PARMS
*
frame_parms
)
{
NR_gNB_DLSCH_t
*
dlsch
;
unsigned
char
exit_flag
=
0
,
i
,
j
,
r
,
aa
,
layer
;
int
re
;
unsigned
char
bw_scaling
=
1
;
switch
(
N_RB_DL
)
{
case
106
:
bw_scaling
=
2
;
break
;
default:
bw_scaling
=
1
;
break
;
}
dlsch
=
(
NR_gNB_DLSCH_t
*
)
malloc16
(
sizeof
(
NR_gNB_DLSCH_t
));
if
(
dlsch
)
{
bzero
(
dlsch
,
sizeof
(
NR_gNB_DLSCH_t
));
dlsch
->
Kmimo
=
Kmimo
;
dlsch
->
Mdlharq
=
Mdlharq
;
dlsch
->
Mlimit
=
4
;
dlsch
->
Nsoft
=
Nsoft
;
for
(
layer
=
0
;
layer
<
4
;
layer
++
)
{
dlsch
->
ue_spec_bf_weights
[
layer
]
=
(
int32_t
**
)
malloc16
(
frame_parms
->
nb_antennas_tx
*
sizeof
(
int32_t
*
));
for
(
aa
=
0
;
aa
<
frame_parms
->
nb_antennas_tx
;
aa
++
)
{
dlsch
->
ue_spec_bf_weights
[
layer
][
aa
]
=
(
int32_t
*
)
malloc16
(
OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES
*
sizeof
(
int32_t
));
for
(
re
=
0
;
re
<
OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES
;
re
++
)
{
dlsch
->
ue_spec_bf_weights
[
layer
][
aa
][
re
]
=
0x00007fff
;
}
}
}
dlsch
->
calib_dl_ch_estimates
=
(
int32_t
**
)
malloc16
(
frame_parms
->
nb_antennas_tx
*
sizeof
(
int32_t
*
));
for
(
aa
=
0
;
aa
<
frame_parms
->
nb_antennas_tx
;
aa
++
)
{
dlsch
->
calib_dl_ch_estimates
[
aa
]
=
(
int32_t
*
)
malloc16
(
OFDM_SYMBOL_SIZE_COMPLEX_SAMPLES
*
sizeof
(
int32_t
));
}
for
(
i
=
0
;
i
<
10
;
i
++
)
dlsch
->
harq_ids
[
i
]
=
Mdlharq
;
for
(
i
=
0
;
i
<
Mdlharq
;
i
++
)
{
dlsch
->
harq_processes
[
i
]
=
(
NR_DL_gNB_HARQ_t
*
)
malloc16
(
sizeof
(
NR_DL_gNB_HARQ_t
));
LOG_T
(
PHY
,
"Required mem size %d (bw scaling %d), dlsch->harq_processes[%d] %p
\n
"
,
MAX_NR_ULSCH_PAYLOAD_BYTES
/
bw_scaling
,
bw_scaling
,
i
,
dlsch
->
harq_processes
[
i
]);
if
(
dlsch
->
harq_processes
[
i
])
{
bzero
(
dlsch
->
harq_processes
[
i
],
sizeof
(
NR_DL_gNB_HARQ_t
));
// dlsch->harq_processes[i]->first_tx=1;
dlsch
->
harq_processes
[
i
]
->
b
=
(
unsigned
char
*
)
malloc16
(
MAX_NR_ULSCH_PAYLOAD_BYTES
/
bw_scaling
);
if
(
dlsch
->
harq_processes
[
i
]
->
b
)
{
bzero
(
dlsch
->
harq_processes
[
i
]
->
b
,
MAX_NR_ULSCH_PAYLOAD_BYTES
/
bw_scaling
);
}
else
{
printf
(
"Can't get b
\n
"
);
exit_flag
=
1
;
}
if
(
abstraction_flag
==
0
)
{
for
(
r
=
0
;
r
<
MAX_NUM_NR_DLSCH_SEGMENTS
/
bw_scaling
;
r
++
)
{
// account for filler in first segment and CRCs for multiple segment case
dlsch
->
harq_processes
[
i
]
->
c
[
r
]
=
(
uint8_t
*
)
malloc16
(
8448
);
dlsch
->
harq_processes
[
i
]
->
d
[
r
]
=
(
uint8_t
*
)
malloc16
(
3
*
8448
);
if
(
dlsch
->
harq_processes
[
i
]
->
c
[
r
])
{
bzero
(
dlsch
->
harq_processes
[
i
]
->
c
[
r
],
8448
);
}
else
{
printf
(
"Can't get c
\n
"
);
exit_flag
=
2
;
}
if
(
dlsch
->
harq_processes
[
i
]
->
d
[
r
])
{
bzero
(
dlsch
->
harq_processes
[
i
]
->
d
[
r
],(
3
*
8448
));
}
else
{
printf
(
"Can't get d
\n
"
);
exit_flag
=
2
;
}
}
}
}
else
{
printf
(
"Can't get harq_p %d
\n
"
,
i
);
exit_flag
=
3
;
}
}
if
(
exit_flag
==
0
)
{
for
(
i
=
0
;
i
<
Mdlharq
;
i
++
)
{
dlsch
->
harq_processes
[
i
]
->
round
=
0
;
}
return
(
dlsch
);
}
}
LOG_D
(
PHY
,
"new_gNB_dlsch exit flag %d, size of %ld
\n
"
,
exit_flag
,
sizeof
(
NR_gNB_DLSCH_t
));
free_gNB_dlsch
(
dlsch
);
return
(
NULL
);
}
void
clean_gNB_dlsch
(
NR_gNB_DLSCH_t
*
dlsch
)
{
unsigned
char
Mdlharq
;
unsigned
char
i
,
j
,
r
;
if
(
dlsch
)
{
Mdlharq
=
dlsch
->
Mdlharq
;
dlsch
->
rnti
=
0
;
dlsch
->
active
=
0
;
for
(
i
=
0
;
i
<
10
;
i
++
)
dlsch
->
harq_ids
[
i
]
=
Mdlharq
;
for
(
i
=
0
;
i
<
Mdlharq
;
i
++
)
{
if
(
dlsch
->
harq_processes
[
i
])
{
// dlsch->harq_processes[i]->Ndi = 0;
dlsch
->
harq_processes
[
i
]
->
status
=
0
;
dlsch
->
harq_processes
[
i
]
->
round
=
0
;
for
(
j
=
0
;
j
<
96
;
j
++
)
for
(
r
=
0
;
r
<
MAX_NUM_DLSCH_SEGMENTS
;
r
++
)
if
(
dlsch
->
harq_processes
[
i
]
->
d
[
r
])
dlsch
->
harq_processes
[
i
]
->
d
[
r
][
j
]
=
NR_NULL
;
}
}
}
}
int
dlsch_encoding
(
PHY_VARS_gNB
*
gNB
,
unsigned
char
*
a
,
uint8_t
num_pdcch_symbols
,
NR_gNB_DLSCH_t
*
dlsch
,
int
frame
,
uint8_t
subframe
,
time_stats_t
*
rm_stats
,
time_stats_t
*
te_stats
,
time_stats_t
*
i_stats
)
{
unsigned
int
G
;
unsigned
int
crc
=
1
;
unsigned
short
iind
;
NR_DL_FRAME_PARMS
*
frame_parms
=
&
gNB
->
frame_parms
;
unsigned
char
harq_pid
=
dlsch
->
current_harq_pid
;
unsigned
short
nb_rb
=
dlsch
->
harq_processes
[
harq_pid
]
->
nb_rb
;
unsigned
int
A
,
Z
;
unsigned
*
pz
=
&
Z
;
unsigned
char
mod_order
;
unsigned
int
Kr
=
0
,
Kr_bytes
,
r
,
r_offset
=
0
,
Kr_int
=
0
;
unsigned
short
m
=
dlsch
->
harq_processes
[
harq_pid
]
->
mcs
;
uint8_t
beamforming_mode
=
0
;
uint8_t
*
d_tmp
[
MAX_NUM_DLSCH_SEGMENTS
];
double
rate
=
0
.
33
;
uint8_t
kb
,
BG
;
uint32_t
E
;
uint8_t
Ilbrm
=
0
;
uint32_t
Tbslbrm
=
950984
;
//to compute tbs
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
(
VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING
,
VCD_FUNCTION_IN
);
A
=
dlsch
->
harq_processes
[
harq_pid
]
->
TBS
;
//printf("Encoder: A: %d frame.subframe %d.%d \n",A, frame,subframe);
mod_order
=
get_nr_Qm
(
dlsch
->
harq_processes
[
harq_pid
]
->
mcs
);
G
=
get_G
(
frame_parms
,
nb_rb
,
dlsch
->
harq_processes
[
harq_pid
]
->
rb_alloc
,
mod_order
,
dlsch
->
harq_processes
[
harq_pid
]
->
Nl
,
num_pdcch_symbols
,
frame
,
subframe
,
beamforming_mode
);
// if (dlsch->harq_processes[harq_pid]->Ndi == 1) { // this is a new packet
if
(
dlsch
->
harq_processes
[
harq_pid
]
->
round
==
0
)
{
// this is a new packet
#ifdef DEBUG_DLSCH_CODING
printf
(
"encoding thinks this is a new packet
\n
"
);
#endif
/*
int i;
printf("dlsch (tx): \n");
for (i=0;i<(A>>3);i++)
printf("%02x.",a[i]);
printf("\n");
*/
// Add 24-bit crc (polynomial A) to payload
crc
=
crc24a
(
a
,
A
)
>>
8
;
a
[
A
>>
3
]
=
((
uint8_t
*
)
&
crc
)[
2
];
a
[
1
+
(
A
>>
3
)]
=
((
uint8_t
*
)
&
crc
)[
1
];
a
[
2
+
(
A
>>
3
)]
=
((
uint8_t
*
)
&
crc
)[
0
];
//printf("CRC %x (A %d)\n",crc,A);
dlsch
->
harq_processes
[
harq_pid
]
->
B
=
A
+
24
;
// dlsch->harq_processes[harq_pid]->b = a;
memcpy
(
dlsch
->
harq_processes
[
harq_pid
]
->
b
,
a
,(
A
/
8
)
+
4
);
nr_segmentation
(
dlsch
->
harq_processes
[
harq_pid
]
->
b
,
dlsch
->
harq_processes
[
harq_pid
]
->
c
,
dlsch
->
harq_processes
[
harq_pid
]
->
B
,
&
dlsch
->
harq_processes
[
harq_pid
]
->
C
,
&
dlsch
->
harq_processes
[
harq_pid
]
->
K
,
pz
,
&
dlsch
->
harq_processes
[
harq_pid
]
->
F
);
kb
=
dlsch
->
harq_processes
[
harq_pid
]
->
K
/
(
*
pz
);
if
(
kb
==
22
){
BG
=
1
;
}
else
{
BG
=
2
;
}
//printf("Encoder: B %d F %d \n",dlsch->harq_processes[harq_pid]->B, dlsch->harq_processes[harq_pid]->F);
Kr
=
dlsch
->
harq_processes
[
harq_pid
]
->
K
;
Kr_bytes
=
Kr
>>
3
;
start_meas
(
te_stats
);
for
(
r
=
0
;
r
<
dlsch
->
harq_processes
[
harq_pid
]
->
C
;
r
++
)
{
d_tmp
[
r
]
=
&
dlsch
->
harq_processes
[
harq_pid
]
->
d
[
r
][
0
];
#ifdef DEBUG_DLSCH_CODING
printf
(
"start ldpc encoder segment %d/%d
\n
"
,
r
,
dlsch
->
harq_processes
[
harq_pid
]
->
C
);
printf
(
"input %d %d %d %d %d
\n
"
,
dlsch
->
harq_processes
[
harq_pid
]
->
c
[
r
][
0
],
dlsch
->
harq_processes
[
harq_pid
]
->
c
[
r
][
1
],
dlsch
->
harq_processes
[
harq_pid
]
->
c
[
r
][
2
],
dlsch
->
harq_processes
[
harq_pid
]
->
c
[
r
][
3
],
dlsch
->
harq_processes
[
harq_pid
]
->
c
[
r
][
4
]);
/*for (int cnt =0 ; cnt < 22*(*pz); cnt ++){
printf("%d ", dlsch->harq_processes[harq_pid]->c[r][cnt]);
}*/
#endif
//ldpc_encoder_orig((unsigned char*)dlsch->harq_processes[harq_pid]->c[r],&dlsch->harq_processes[harq_pid]->d[r][96],Kr,1,3,0);
//ldpc_encoder((unsigned char*)dlsch->harq_processes[harq_pid]->c[r],&dlsch->harq_processes[harq_pid]->d[r][96],Kr,1,3);
//ldpc_encoder_optim((unsigned char*)dlsch->harq_processes[harq_pid]->c[r],(unsigned char*)&dlsch->harq_processes[harq_pid]->d[r][96],Kr,1,3,NULL,NULL,NULL,NULL);
}
ldpc_encoder_optim_8seg
(
dlsch
->
harq_processes
[
harq_pid
]
->
c
,
d_tmp
,
Kr
,
1
,
3
,
dlsch
->
harq_processes
[
harq_pid
]
->
C
,
NULL
,
NULL
,
NULL
,
NULL
);
stop_meas
(
te_stats
);
/*printf("end ldpc encoder -- output\n");
printf("output %d %d %d %d %d \n", dlsch->harq_processes[harq_pid]->d[r][0], dlsch->harq_processes[harq_pid]->d[r][1], dlsch->harq_processes[harq_pid]->d[r][2],dlsch->harq_processes[harq_pid]->d[r][3], dlsch->harq_processes[harq_pid]->d[r][4]);
for (int cnt =0 ; cnt < 66*(*pz); cnt ++){
printf("%d \n", dlsch->harq_processes[harq_pid]->d[r][cnt]);
}
printf("\n");*/
#ifdef DEBUG_DLSCH_CODING
write_output
(
"enc_input0.m"
,
"enc_in0"
,
&
dlsch
->
harq_processes
[
harq_pid
]
->
c
[
0
][
0
],
Kr_bytes
,
1
,
4
);
write_output
(
"enc_output0.m"
,
"enc0"
,
&
dlsch
->
harq_processes
[
harq_pid
]
->
d
[
0
][
0
],(
3
*
8
*
Kr_bytes
)
+
12
,
1
,
4
);
#endif
}
for
(
r
=
0
;
r
<
dlsch
->
harq_processes
[
harq_pid
]
->
C
;
r
++
)
{
#ifdef DEBUG_DLSCH_CODING
printf
(
"Rate Matching, Code segment %d (coded bits (G) %d,unpunctured/repeated bits per code segment %d,mod_order %d, nb_rb %d)...
\n
"
,
r
,
G
,
Kr
*
3
,
mod_order
,
nb_rb
);
#endif
start_meas
(
rm_stats
);
#ifdef DEBUG_DLSCH_CODING
printf
(
"rvidx in encoding = %d
\n
"
,
dlsch
->
harq_processes
[
harq_pid
]
->
rvidx
);
#endif
r_offset
+=
nr_rate_matching_ldpc
(
Ilbrm
,
Tbslbrm
,
BG
,
*
pz
,
G
,
dlsch
->
harq_processes
[
harq_pid
]
->
d
[
r
],
dlsch
->
harq_processes
[
harq_pid
]
->
e
+
r_offset
,
dlsch
->
harq_processes
[
harq_pid
]
->
C
,
dlsch
->
harq_processes
[
harq_pid
]
->
rvidx
,
mod_order
,
dlsch
->
harq_processes
[
harq_pid
]
->
Nl
,
r
);
stop_meas
(
rm_stats
);
if
(
r
==
0
)
E
=
r_offset
;
start_meas
(
i_stats
);
nr_interleaving_ldpc
(
E
,
&
dlsch
->
harq_processes
[
harq_pid
]
->
Qm
,
dlsch
->
harq_processes
[
harq_pid
]
->
e
+
r_offset
,
dlsch
->
harq_processes
[
harq_pid
]
->
f
+
r_offset
);
stop_meas
(
i_stats
);
#ifdef DEBUG_DLSCH_CODING
if
(
r
==
dlsch
->
harq_processes
[
harq_pid
]
->
C
-
1
)
write_output
(
"enc_output.m"
,
"enc"
,
dlsch
->
harq_processes
[
harq_pid
]
->
f
,
r_offset
,
1
,
4
);
#endif
}
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME
(
VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_ENCODING
,
VCD_FUNCTION_OUT
);
return
(
0
);
}
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_decoding.c
View file @
09af43b3
...
...
@@ -382,7 +382,7 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
#endif
nr_deinterleaving_ldpc
(
E
,
harq_process
->
Qm
,
&
harq_process
->
d
[
r
],
harq_process
->
d
[
r
],
harq_process
->
w
[
r
]);
#if UE_TIMING_TRACE
...
...
@@ -445,16 +445,20 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
}
printf(" \n");*/
memset
(
pv
,
0
,
2
*
p_decParams
->
Z
*
sizeof
(
int16_t
));
memset
(
pv
,
0
,
harq_process
->
K
*
sizeof
(
int16_t
));
//memset(pl,0,2*p_decParams->Z*sizeof(int8_t));
for
(
i
=
((
2
*
p_decParams
->
Z
)
>>
3
),
j
=
0
;
i
<
(
Kr_bytes
-
(
harq_process
->
F
>>
3
));
i
++
,
j
++
)
{
pv
[
i
]
=
_mm_loadu_si128
((
__m128i
*
)(
&
inv_d
[
8
*
j
]));
}
for
(
i
=
2
*
p_decParams
->
Z
/
8
,
j
=
0
;
i
<
(
kc
*
p_decParams
->
Z
/
8
+
1
);
i
++
,
j
++
)
for
(
i
=
Kr_bytes
,
j
=
(
Kr_bytes
-
(
harq_process
->
F
>>
3
));
i
<
((
kc
*
p_decParams
->
Z
)
>>
3
);
i
++
,
j
++
)
{
pv
[
i
]
=
_mm_loadu_si128
((
__m128i
*
)(
&
inv_d
[
8
*
j
]));
}
for
(
i
=
0
,
j
=
0
;
j
<
(
kc
*
p_decParams
->
Z
/
16
);
i
+=
2
,
j
++
)
for
(
i
=
0
,
j
=
0
;
j
<
(
(
kc
*
p_decParams
->
Z
)
>>
4
);
i
+=
2
,
j
++
)
{
pl
[
j
]
=
_mm_packs_epi16
(
pv
[
i
],
pv
[
i
+
1
]);
...
...
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
View file @
09af43b3
...
...
@@ -856,13 +856,18 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
// -> // compute @pointer where llrs should filled for this ofdm-symbol
int8_t
*
pllr_symbol_cw0
;
int8_t
*
pllr_symbol_cw1
;
int8_t
*
pllr_symbol_cw0_deint
;
int8_t
*
pllr_symbol_cw1_deint
;
uint32_t
llr_offset_symbol
;
uint32_t
nb_rb_pdsch
=
106
;
uint16_t
bundle_L
=
2
;
llr_offset_symbol
=
pdsch_vars
[
eNB_id
]
->
llr_offset
[
symbol
];
pllr_symbol_cw0
=
(
int8_t
*
)
pdsch_vars
[
eNB_id
]
->
llr
[
0
];
pllr_symbol_cw1
=
(
int8_t
*
)
pdsch_vars
[
eNB_id
]
->
llr
[
1
];
pllr_symbol_cw0
_deint
=
(
int8_t
*
)
pdsch_vars
[
eNB_id
]
->
llr
[
0
];
pllr_symbol_cw1
_deint
=
(
int8_t
*
)
pdsch_vars
[
eNB_id
]
->
llr
[
1
];
pllr_symbol_cw0
+=
llr_offset_symbol
;
pllr_symbol_cw1
+=
llr_offset_symbol
;
/*LOG_I(PHY,"compute LLRs [AbsSubframe %d.%d-%d] NbRB %d Qm %d LLRs-Length %d LLR-Offset %d @LLR Buff %x @LLR Buff(symb) %x\n",
proc->frame_rx, proc->subframe_rx,symbol,
nb_rb,dlsch0_harq->Qm,
...
...
@@ -1198,6 +1203,8 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
}
}
nr_dlsch_deinterleaving
(
symbol
,
bundle_L
,(
int16_t
*
)
pllr_symbol_cw0
,(
int16_t
*
)
pllr_symbol_cw0_deint
,
nb_rb_pdsch
);
#if UE_TIMING_TRACE
stop_meas
(
&
ue
->
generic_stat_bis
[
ue
->
current_thread_id
[
nr_tti_rx
]][
slot
]);
#if DISABLE_LOG_X
...
...
@@ -1256,6 +1263,51 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
}
void
nr_dlsch_deinterleaving
(
uint8_t
symbol
,
uint16_t
L
,
uint16_t
*
llr
,
uint16_t
*
llr_deint
,
uint32_t
nb_rb_pdsch
)
{
uint32_t
bundle_idx
,
N_bundle
,
R
,
C
,
r
,
c
;
int32_t
m
,
k
;
uint8_t
nb_re
;
R
=
2
;
N_bundle
=
nb_rb_pdsch
/
L
;
C
=
N_bundle
/
R
;
uint32_t
*
bundle_deint
=
malloc
(
N_bundle
*
sizeof
(
uint32_t
));
printf
(
"N_bundle %d L %d nb_rb_pdsch %d
\n
"
,
N_bundle
,
L
,
nb_rb_pdsch
);
if
(
symbol
==
2
)
nb_re
=
6
;
else
nb_re
=
12
;
AssertFatal
(
llr
!=
NULL
,
"nr_dlsch_deinterleaving: FATAL llr is Null
\n
"
);
for
(
c
=
0
;
c
<
C
;
c
++
){
for
(
r
=
0
;
r
<
R
;
r
++
){
bundle_idx
=
r
*
C
+
c
;
bundle_deint
[
bundle_idx
]
=
c
*
R
+
r
;
//printf("c %u r %u bundle_idx %u bundle_deinter %u\n", c, r, bundle_idx, bundle_deint[bundle_idx]);
}
}
for
(
k
=
0
;
k
<
N_bundle
;
k
++
)
{
for
(
m
=
0
;
m
<
nb_re
*
L
;
m
++
){
llr_deint
[
bundle_deint
[
k
]
*
nb_re
*
L
+
m
]
=
llr
[
k
*
nb_re
*
L
+
m
];
//printf("k %d m %d bundle_deint %d llr_deint %d\n", k, m, bundle_deint[k], llr_deint[bundle_deint[k]*nb_re*L+m]);
}
}
}
//==============================================================================================
// Pre-processing for LLR computation
//==============================================================================================
...
...
@@ -1302,11 +1354,11 @@ void nr_dlsch_channel_compensation(int **rxdataF_ext,
for
(
aarx
=
0
;
aarx
<
frame_parms
->
nb_antennas_rx
;
aarx
++
)
{
dl_ch128
=
(
__m128i
*
)
&
dl_ch_estimates_ext
[(
aatx
<<
1
)
+
aarx
][
symbol
*
frame_parms
->
N_RB_DL
*
12
];
dl_ch_mag128
=
(
__m128i
*
)
&
dl_ch_mag
[(
aatx
<<
1
)
+
aarx
][
symbol
*
frame_parms
->
N_RB_DL
*
12
];
dl_ch_mag128b
=
(
__m128i
*
)
&
dl_ch_magb
[(
aatx
<<
1
)
+
aarx
][
symbol
*
frame_parms
->
N_RB_DL
*
12
];
rxdataF128
=
(
__m128i
*
)
&
rxdataF_ext
[
aarx
][
symbol
*
frame_parms
->
N_RB_DL
*
12
];
rxdataF_comp128
=
(
__m128i
*
)
&
rxdataF_comp
[(
aatx
<<
1
)
+
aarx
][
symbol
*
frame_parms
->
N_RB_DL
*
12
];
dl_ch128
=
(
__m128i
*
)
&
dl_ch_estimates_ext
[(
aatx
<<
1
)
+
aarx
][
symbol
*
nb_rb
*
12
];
dl_ch_mag128
=
(
__m128i
*
)
&
dl_ch_mag
[(
aatx
<<
1
)
+
aarx
][
symbol
*
nb_rb
*
12
];
dl_ch_mag128b
=
(
__m128i
*
)
&
dl_ch_magb
[(
aatx
<<
1
)
+
aarx
][
symbol
*
nb_rb
*
12
];
rxdataF128
=
(
__m128i
*
)
&
rxdataF_ext
[
aarx
][
symbol
*
nb_rb
*
12
];
rxdataF_comp128
=
(
__m128i
*
)
&
rxdataF_comp
[(
aatx
<<
1
)
+
aarx
][
symbol
*
nb_rb
*
12
];
for
(
rb
=
0
;
rb
<
nb_rb
;
rb
++
)
{
...
...
@@ -1515,7 +1567,7 @@ void nr_dlsch_channel_compensation(int **rxdataF_ext,
}
if
(
first_symbol_flag
==
1
)
{
measurements
->
rx_correlation
[
0
][
aarx
]
=
signal_energy
(
&
rho
[
aarx
][
symbol
*
frame_parms
->
N_RB_DL
*
12
],
rb
*
12
);
measurements
->
rx_correlation
[
0
][
aarx
]
=
signal_energy
(
&
rho
[
aarx
][
symbol
*
nb_rb
*
12
],
rb
*
12
);
}
}
}
...
...
@@ -1945,7 +1997,7 @@ unsigned short nr_dlsch_extract_rbs_single(int **rxdataF,
unsigned
char
symbol_mod
,
pilots
=
0
,
j
=
0
,
poffset
=
0
;
symbol_mod
=
(
symbol
>=
(
7
-
frame_parms
->
Ncp
))
?
symbol
-
(
7
-
frame_parms
->
Ncp
)
:
symbol
;
pilots
=
(
(
symbol_mod
==
0
)
||
(
symbol_mod
==
(
4
-
frame_parms
->
Ncp
)))
?
1
:
0
;
pilots
=
(
symbol
==
2
)
?
1
:
0
;
//to updated from config
l
=
symbol
;
nsymb
=
(
frame_parms
->
Ncp
==
NORMAL
)
?
14
:
12
;
...
...
openair1/PHY/NR_UE_TRANSPORT/nr_transport_proto_ue.h
View file @
09af43b3
...
...
@@ -830,6 +830,12 @@ void nr_dlsch_channel_compensation(int32_t **rxdataF_ext,
uint8_t
output_shift
,
PHY_NR_MEASUREMENTS
*
phy_measurements
);
void
nr_dlsch_deinterleaving
(
uint8_t
symbol
,
uint16_t
L
,
uint16_t
*
llr
,
uint16_t
*
llr_deint
,
uint32_t
nb_rb_pdsch
);
void
dlsch_dual_stream_correlation
(
NR_DL_FRAME_PARMS
*
frame_parms
,
unsigned
char
symbol
,
unsigned
short
nb_rb
,
...
...
@@ -991,13 +997,14 @@ void nr_dlsch_scale_channel(int32_t **dl_ch_estimates_ext,
@param llr8_flag If 1, indicate that the 8-bit turbo decoder should be used
@returns 0 on success, 1 on unsuccessful decoding
*/
uint32_t
dlsch_decoding
(
PHY_VARS_NR_UE
*
phy_vars_ue
,
int16_t
*
dlsch_llr
,
NR_DL_FRAME_PARMS
*
lte_frame_parms
,
uint32_t
nr_dlsch_decoding
(
PHY_VARS_NR_UE
*
phy_vars_ue
,
short
*
dlsch_llr
,
NR_DL_FRAME_PARMS
*
frame_parms
,
NR_UE_DLSCH_t
*
dlsch
,
NR_DL_UE_HARQ_t
*
harq_process
,
uint32_t
frame
,
uint8_t
subframe
,
uint8_t
nr_tti_rx
,
uint8_t
harq_pid
,
uint8_t
is_crnti
,
uint8_t
llr8_flag
);
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @
09af43b3
...
...
@@ -71,10 +71,32 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
memcpy
((
void
*
)
params_rel15
,
(
void
*
)
&
gNB
->
pdcch_type0_params
,
sizeof
(
nfapi_nr_dl_config_pdcch_parameters_rel15_t
));
pdu_rel15
->
frequency_domain_assignment
=
5
;
pdu_rel15
->
time_domain_assignment
=
2
;
pdu_rel15
->
vrb_to_prb_mapping
=
0
;
pdu_rel15
->
time_domain_assignment
=
3
;
pdu_rel15
->
vrb_to_prb_mapping
=
1
;
pdu_rel15
->
mcs
=
12
;
pdu_rel15
->
tb_scaling
=
1
;
pdu_rel15
->
ra_preamble_index
=
25
;
pdu_rel15
->
format_indicator
=
1
;
pdu_rel15
->
ul_sul_indicator
=
1
;
pdu_rel15
->
ss_pbch_index
=
21
;
pdu_rel15
->
prach_mask_index
=
3
;
pdu_rel15
->
ndi
=
1
;
pdu_rel15
->
rv
=
2
;
pdu_rel15
->
harq_pid
=
7
;
pdu_rel15
->
dai
=
2
;
pdu_rel15
->
tpc
=
2
;
pdu_rel15
->
pucch_resource_indicator
=
7
;
pdu_rel15
->
pdsch_to_harq_feedback_timing_indicator
=
7
;
pdu_rel15
->
tb_scaling
=
1
;
pdu_rel15
->
tb_scaling
=
1
;
pdu_rel15
->
tb_scaling
=
1
;
pdu_rel15
->
tb_scaling
=
1
;
LOG_I
(
MAC
,
"[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d
\n
"
,
pdu_rel15
->
frequency_domain_assignment
,
pdu_rel15
->
time_domain_assignment
,
...
...
@@ -83,7 +105,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
pdu_rel15
->
tb_scaling
);
params_rel15
->
rnti
=
0x03
;
params_rel15
->
rnti_type
=
NFAPI_NR_RNTI_
RA
;
params_rel15
->
rnti_type
=
NFAPI_NR_RNTI_
C
;
params_rel15
->
dci_format
=
NFAPI_NR_DL_DCI_FORMAT_1_0
;
//params_rel15->aggregation_level = 1;
LOG_I
(
MAC
,
"DCI type 1 params: rmsi_pdcch_config %d, rnti %d, rnti_type %d, dci_format %d
\n
\
...
...
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