Merge remote-tracking branch 'origin/liteon-fr2-cleanup' into integration_2026_w12 (!3956)

[FHI72] [xran F] Revert and simplify the code for Liteon FR2 interoperability The MR !3668 introduced a lot of unnecessary changes. This MR removes useless code in both OAI and xran F release library.

Merge remote-tracking branch 'origin/liteon-fr2-cleanup' into integration_2026_w12 (!3956)
[FHI72] [xran F] Revert and simplify the code for Liteon FR2 interoperability The MR !3668 introduced a lot of unnecessary changes. This MR removes useless code in both OAI and xran F release library.
2e4445ac · Jaroslava Fiedlerova · f3618597 · a7ff360c · 2e4445ac · 2e4445ac
Commit 2e4445ac authored Mar 17, 2026 by Jaroslava Fiedlerova
7 changed files
--- a/cmake_targets/tools/oran_fhi_integration_patches/F/oaioran_F.patch
+++ b/cmake_targets/tools/oran_fhi_integration_patches/F/oaioran_F.patch
 diff --git a/fhi_lib/app/src/common.h b/fhi_lib/app/src/common.h
-index ac5f471..b1acb26 100644
+index ac5f471..fe27425 100644
 --- a/fhi_lib/app/src/common.h
 +++ b/fhi_lib/app/src/common.h
 @@ -28,7 +28,7 @@
@@ -7,7 +7,7 @@ index ac5f471..b1acb26 100644
 #include <rte_mbuf.h>
 -#define VERSIONX                "oran_f_release_v1.0"
-+#define VERSIONX                "oran_f_release_v1.8"
+#define VERSIONX                "oran_f_release_v1.9"
 #define APP_O_DU  0
 #define APP_O_RU  1
@@ -173,20 +173,18 @@ index eccc4ae..a97fdc6 100644
 CPP_FLAGS_FULL := $(CPP_FLAGS) $(CPP_COMP) $(INC) $(DEF)
 CPP_FLAGS_FULL_SNC := $(CPP_FLAGS) $(CPP_COMP_SNC) $(INC) $(DEF)
 diff --git a/fhi_lib/lib/api/xran_fh_o_du.h b/fhi_lib/lib/api/xran_fh_o_du.h
-index bacf597..18597d6 100644
+index bacf597..c37e132 100644
 --- a/fhi_lib/lib/api/xran_fh_o_du.h
 +++ b/fhi_lib/lib/api/xran_fh_o_du.h
-@@ -141,8 +141,8 @@ extern "C" {
+@@ -141,7 +141,7 @@ extern "C" {
 #define XRAN_MAX_SECTIONS_PER_SYM    (XRAN_MAX_SECTIONS_PER_SLOT)  /**< Max number of different sections in single slot (section may be equal to RB allocation for UE) */
 #define XRAN_MIN_SECTIONS_PER_SYM    (XRAN_MIN_SECTIONS_PER_SLOT)  /**< Min number of different sections in single slot (section may be equal to RB allocation for UE) */
 -#define XRAN_MAX_FRAGMENT            (4)   /**< Max number of fragmentations in single symbol */
-#define XRAN_MAX_SET_BFWS            (64)  /**< Assumed 64Ant, BFP 9bit with 9K jumbo frame */
 +#define XRAN_MAX_FRAGMENT            (7)   /**< Max number of fragmentations in single symbol */
-+#define XRAN_MAX_SET_BFWS            (1) //(64)  /**< Assumed 64Ant, BFP 9bit with 9K jumbo frame */
+ #define XRAN_MAX_SET_BFWS            (64)  /**< Assumed 64Ant, BFP 9bit with 9K jumbo frame */
 #define XRAN_MAX_PKT_BURST (448+4) /**< 4x14x8 symbols per ms */
- #define XRAN_N_MAX_BUFFER_SEGMENT XRAN_MAX_PKT_BURST /**< Max number of segments per ms */
 @@ -419,6 +419,7 @@ struct xran_io_cfg {
     uint16_t num_rxq;             /**< number of RX queues per VF */
     char *dpdk_dev[XRAN_VF_MAX]; /**< VFs devices  */
@@ -195,15 +193,7 @@ index bacf597..18597d6 100644
     int32_t bbdev_mode;      /**< DPDK for BBDev */
     uint32_t dpdkIoVaMode;   /**< IOVA Mode */
     uint32_t dpdkMemorySize; /**< DPDK max memory allocation */
-@@ -713,6 +714,7 @@ struct xran_fh_config {
+@@ -1193,6 +1194,31 @@ int32_t xran_reg_physide_cb_by_dev_id(void *pHandle, xran_fh_tti_callback_fn Cb,
-     uint16_t max_sections_per_slot; /**< M-Plane settings for section */
-     uint16_t max_sections_per_symbol; /**< M-Plane settings for section */
-     int32_t RunSlotPrbMapBySymbolEnable; /**< enable prb mapping by symbol with multisection*/
-+    uint8_t LiteOnIgnoreUPSectionIdEnable; /**< handle LiteOn issue where section id on UP packet is wrongly set to 13. */
-     uint8_t dssEnable;  /**< enable DSS (extension-9) */
-     uint8_t dssPeriod;  /**< DSS pattern period for LTE/NR */
-@@ -1193,6 +1195,31 @@ int32_t xran_reg_physide_cb_by_dev_id(void *pHandle, xran_fh_tti_callback_fn Cb,
  */
 int32_t xran_get_slot_idx (uint32_t PortId, uint32_t *nFrameIdx, uint32_t *nSubframeIdx,  uint32_t *nSlotIdx, uint64_t *nSecond);
@@ -594,7 +584,7 @@ index 08660f3..b5de607 100644
         time_diff_nSymb = time_diff_us*1000/(interval_us_local*1000/N_SYM_PER_SLOT);
 diff --git a/fhi_lib/lib/src/xran_common.c b/fhi_lib/lib/src/xran_common.c
-index dc40ad9..1b88013 100644
+index dc40ad9..5968d01 100644
 --- a/fhi_lib/lib/src/xran_common.c
 +++ b/fhi_lib/lib/src/xran_common.c
 @@ -31,7 +31,10 @@
@@ -608,110 +598,7 @@ index dc40ad9..1b88013 100644
 #include <rte_mbuf.h>
 #include <stdio.h>
 #include <stdbool.h>
-@@ -49,6 +52,8 @@
+@@ -714,11 +717,14 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
- #include "xran_printf.h"
- #include "xran_mlog_lnx.h"
-+#include "xran_frame_struct.h"
-+
- static struct timespec sleeptime = {.tv_nsec = 1E3 }; /* 1 us */
- extern int32_t first_call;
-@@ -529,13 +534,30 @@ int process_mbuf_batch(struct rte_mbuf* pkt_q[], void* handle, int16_t num, stru
-             if (pRbMap)
-             {
-                 /** Get the prb_elem_id */
-+                u_int8_t section_id_tmp;    // hack for LiteON FR2 : receive UP section ID = 13
-+                u_int8_t prb_elem_id_tmp;   // hack for LiteON FR2 : receive UP section ID = 13
-+                if(0 == p_dev_ctx->LiteOnIgnoreUPSectionIdEnable) {
-+                    section_id_tmp = prb_elem_id_tmp = sect_id[i];
-+                } else {
-+                    u_int8_t mixed_ul_sym_start = 0;
-+                    if (xran_fs_get_slot_type(xran_port, CC_ID[i], tti, XRAN_SLOT_TYPE_SP)) {
-+                        mixed_ul_sym_start = XRAN_NUM_OF_SYMBOL_PER_SLOT - xran_fs_get_num_ul_sym_sp(xran_port, CC_ID[i], tti);
-+                    }
-+                    u_int8_t section_id_tmp = symb_id[i] - mixed_ul_sym_start;  // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                    prb_elem_id_tmp = section_id_tmp;                           // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                    //Note for future reference when using MTU 1500
-+                    //prb_elem_id_tmp = 2*section_id_tmp;                       // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                    //if (start_prbu !=0)                                       // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                    //    prb_elem_id_tmp++;                                    // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                }
-+
-                 total_sections=0;
-                 if(pRbMap->prbMap[0].bf_weight.extType == 1)
-                 {
-                     for(idxElm=0 ; idxElm < pRbMap->nPrbElm ; idxElm++)
-                     {
-                         total_sections += pRbMap->prbMap[idxElm].bf_weight.numSetBFWs;
-                        if(total_sections >= (sect_id[i] + 1))
-+                        if(total_sections >= (/*sect_id[i]*/ prb_elem_id_tmp + 1))
-                 {
-                             prb_elem_id[i] = idxElm;
-                             break;
-@@ -544,12 +566,12 @@ int process_mbuf_batch(struct rte_mbuf* pkt_q[], void* handle, int16_t num, stru
-                 }
-                 else
-                 {
-                    prb_elem_id[i] = sect_id[i];
-+                    prb_elem_id[i] = prb_elem_id_tmp; /*sect_id[i];*/
-                 }
-                 if (prb_elem_id[i] >= pRbMap->nPrbElm)
-                 {
-                    print_err("sect_id %d, prb_elem_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], prb_elem_id[i], pRbMap->nPrbElm);
-+                    print_err("sect_id %d, prb_elem_id %d !=pRbMap->nPrbElm %d\n", /*sect_id[i]*/ section_id_tmp, prb_elem_id[i], pRbMap->nPrbElm);
-                     ret_data[i] = MBUF_FREE;
-                     continue;
-                 }
-@@ -615,13 +637,30 @@ int process_mbuf_batch(struct rte_mbuf* pkt_q[], void* handle, int16_t num, stru
-             if (pRbMap)
-             {
-                 /** Get the prb_elem_id */
-+                u_int8_t section_id_tmp;    // hack for LiteON FR2 : receive UP section ID = 13
-+                u_int8_t prb_elem_id_tmp;   // hack for LiteON FR2 : receive UP section ID = 13
-+                if(0 == p_dev_ctx->LiteOnIgnoreUPSectionIdEnable) {
-+                    section_id_tmp = prb_elem_id_tmp = sect_id[i];
-+                } else {
-+                    u_int8_t mixed_ul_sym_start = 0;
-+                    if (xran_fs_get_slot_type(xran_port, CC_ID[i], tti, XRAN_SLOT_TYPE_SP)) {
-+                        mixed_ul_sym_start = XRAN_NUM_OF_SYMBOL_PER_SLOT - xran_fs_get_num_ul_sym_sp(xran_port, CC_ID[i], tti);
-+                    }
-+                    u_int8_t section_id_tmp = symb_id[i] - mixed_ul_sym_start;  // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                    prb_elem_id_tmp = section_id_tmp;                           // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                    //Note for future reference when using MTU 1500
-+                    //prb_elem_id_tmp = 2*section_id_tmp;                       // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                    //if (start_prbu !=0)                                       // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                    //    prb_elem_id_tmp++;                                    // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                }
-+
-                 total_sections=0;
-                 if(pRbMap->prbMap[0].bf_weight.extType == 1)
-                 {
-                     for(idxElm=0 ; idxElm < pRbMap->nPrbElm ; idxElm++)
-                     {
-                         total_sections += pRbMap->prbMap[idxElm].bf_weight.numSetBFWs;
-                        if(total_sections >= (sect_id[i] + 1))
-+                        if(total_sections >= (/*sect_id[i]*/ prb_elem_id_tmp + 1))
-                         {
-                             prb_elem_id[i] = idxElm;
-                             break;
-@@ -630,12 +669,12 @@ int process_mbuf_batch(struct rte_mbuf* pkt_q[], void* handle, int16_t num, stru
-                 }
-                 else
-                 {
-                    prb_elem_id[i] = sect_id[i];
-+                    prb_elem_id[i] = prb_elem_id_tmp; /*sect_id[i];*/
-                 }
-                 if (prb_elem_id[i] >= pRbMap->nPrbElm)
-                 {
-                    print_err("sect_id %d, prb_elem_id %d !=pRbMap->nPrbElm %d\n", sect_id[i], prb_elem_id[i], pRbMap->nPrbElm);
-+                    print_err("sect_id %d, prb_elem_id %d !=pRbMap->nPrbElm %d\n", /*sect_id[i]*/ section_id_tmp, prb_elem_id[i], pRbMap->nPrbElm);
-                     ret_data[i] = MBUF_FREE;
-                     continue;
-                 }
-@@ -714,11 +753,14 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
     uint8_t compMeth = 0;
     uint8_t iqWidth = 0;
@@ -726,7 +613,7 @@ index dc40ad9..1b88013 100644
     if(first_call == 0)
         return ret;
-@@ -733,9 +775,9 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
+@@ -733,9 +739,9 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
         return MBUF_FREE;
     num_bytes = xran_extract_iq_samples(pkt, &iq_samp_buf,
@@ -738,7 +625,7 @@ index dc40ad9..1b88013 100644
     if (num_bytes <= 0)
     {
         print_err("num_bytes is wrong [%d]\n", num_bytes);
-@@ -781,10 +823,9 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
+@@ -781,10 +787,9 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
     else
     {
@@ -752,7 +639,7 @@ index dc40ad9..1b88013 100644
 #ifndef FCN_ADAPT
         if(valid_res != 0)
         {
-@@ -807,8 +848,7 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
+@@ -807,8 +812,7 @@ process_mbuf(struct rte_mbuf *pkt, void* handle, struct xran_eaxc_info *p_cid)
             PrachCfg = &(p_dev_ctx->PrachCPConfig);
         }
@@ -762,7 +649,7 @@ index dc40ad9..1b88013 100644
         /* PRACH packet has ruportid = num_eAxc + ant_id */
             Ant_ID -= PrachCfg->eAxC_offset;
         symbol_total_bytes[p_dev_ctx->xran_port_id][CC_ID][Ant_ID] += num_bytes;
-@@ -1412,7 +1452,7 @@ int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struc
+@@ -1412,7 +1416,7 @@ int generate_cpmsg_prach(void *pHandle, struct xran_cp_gen_params *params, struc
     if(XRAN_FILTERINDEX_PRACH_ABC == pPrachCPConfig->filterIdx)
     {
     timeOffset = timeOffset >> nNumerology; //original number is Tc, convert to Ts based on mu
@@ -771,7 +658,7 @@ index dc40ad9..1b88013 100644
         timeOffset += 16;
     }
     else
-@@ -1547,8 +1587,7 @@ int32_t ring_processing_func(void* args)
+@@ -1547,8 +1551,7 @@ int32_t ring_processing_func(void* args)
     for (i = 0; i < ctx->io_cfg.num_vfs && i < XRAN_VF_MAX; i++){
         for(qi = 0; qi < ctx->rxq_per_port[i]; qi++) {
@@ -1081,18 +968,10 @@ index 4acade1..c939edc 100644
         for(i = 0; i < xran_ports_num; i++){
             g_xran_dev_ctx[i] = pCtx;
 diff --git a/fhi_lib/lib/src/xran_dev.h b/fhi_lib/lib/src/xran_dev.h
-index 0371a53..778b38d 100644
+index 0371a53..b417619 100644
 --- a/fhi_lib/lib/src/xran_dev.h
 +++ b/fhi_lib/lib/src/xran_dev.h
-@@ -201,6 +201,7 @@ struct __rte_cache_aligned xran_device_ctx
+@@ -254,6 +254,11 @@ struct __rte_cache_aligned xran_device_ctx
-     int32_t DynamicSectionEna;
-     int32_t RunSlotPrbMapBySymbolEnable;
-+    uint8_t LiteOnIgnoreUPSectionIdEnable; /**< handle LiteOn issue where section id on UP packet is wrongly set to 13. */
-     int64_t offset_sec;
-     int64_t offset_nsec;    //offset to GPS time calcuated based on alpha and beta
-     uint32_t interval_us_local;
-@@ -254,6 +255,11 @@ struct __rte_cache_aligned xran_device_ctx
     int32_t sym_up; /**< when we start sym 0 of up with respect to OTA time as measured in symbols */
     int32_t sym_up_ul;
@@ -1105,45 +984,17 @@ index 0371a53..778b38d 100644
     void *TtiCbParam[XRAN_CB_MAX];
     uint32_t SkipTti[XRAN_CB_MAX];
 diff --git a/fhi_lib/lib/src/xran_frame_struct.c b/fhi_lib/lib/src/xran_frame_struct.c
-index fbb1298..44aaf92 100644
+index fbb1298..385de76 100644
 --- a/fhi_lib/lib/src/xran_frame_struct.c
 +++ b/fhi_lib/lib/src/xran_frame_struct.c
-@@ -519,4 +519,20 @@ int32_t xran_fs_get_symbol_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlot
+@@ -518,5 +518,3 @@ int32_t xran_fs_get_symbol_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlot
-     return xran_fs_slot_symb_type[PortId][nCellIdx][nSfIdxMod][nSymbIdx];
- }
-+uint32_t xran_fs_get_num_dl_sym_sp(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx)
+     return xran_fs_slot_symb_type[PortId][nCellIdx][nSfIdxMod][nSymbIdx];
-+{
-+    int32_t nSfIdxMod;
-+
-+    nSfIdxMod = xran_fs_slot_limit(PortId, nSlotdx) % ((xran_fs_num_slot_tdd_loop[PortId][nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[PortId][nCellIdx]: 1);
-+
-+    return xran_fs_num_dl_sym_sp[PortId][nCellIdx][nSfIdxMod];
-+}
-+uint32_t xran_fs_get_num_ul_sym_sp(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx)
-+{
-+    int32_t nSfIdxMod;
-+
-+    nSfIdxMod = xran_fs_slot_limit(PortId, nSlotdx) % ((xran_fs_num_slot_tdd_loop[PortId][nCellIdx] > 0) ? xran_fs_num_slot_tdd_loop[PortId][nCellIdx]: 1);
-+
-+    return xran_fs_num_ul_sym_sp[PortId][nCellIdx][nSfIdxMod];
-+}
-diff --git a/fhi_lib/lib/src/xran_frame_struct.h b/fhi_lib/lib/src/xran_frame_struct.h
-index 7ed0a3a..8e66945 100644
--- a/fhi_lib/lib/src/xran_frame_struct.h
-+++ b/fhi_lib/lib/src/xran_frame_struct.h
-@@ -75,6 +75,8 @@ uint32_t xran_fs_slot_limit_init(uint32_t PortId, int32_t tti_interval_us);
- uint32_t xran_fs_get_max_slot(uint32_t PortId);
- uint32_t xran_fs_get_max_slot_SFN(uint32_t PortId);
- int32_t xran_fs_get_symbol_type(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx,  int32_t nSymbIdx);
-+uint32_t xran_fs_get_num_dl_sym_sp(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx);
-+uint32_t xran_fs_get_num_ul_sym_sp(uint32_t PortId, int32_t nCellIdx, int32_t nSlotdx);
- #ifdef __cplusplus
 }
+-
+-
 diff --git a/fhi_lib/lib/src/xran_main.c b/fhi_lib/lib/src/xran_main.c
-index 7c472d7..db03d94 100644
+index 7c472d7..758616d 100644
 --- a/fhi_lib/lib/src/xran_main.c
 +++ b/fhi_lib/lib/src/xran_main.c
 @@ -35,7 +35,11 @@
@@ -1847,15 +1698,7 @@ index 7c472d7..db03d94 100644
                 if(pThCtx == NULL){
                     print_err("pThCtx allocation error\n");
                     return XRAN_STATUS_FAIL;
-@@ -3754,6 +3808,7 @@ xran_open(void *pHandle, struct xran_fh_config* pConf)
+@@ -4034,6 +4088,24 @@ xran_get_slot_idx (uint32_t PortId, uint32_t *nFrameIdx, uint32_t *nSubframeIdx,
-     p_xran_dev_ctx->puschMaskSlot = pConf->puschMaskSlot;
-     p_xran_dev_ctx->DynamicSectionEna = pConf->DynamicSectionEna;
-     p_xran_dev_ctx->RunSlotPrbMapBySymbolEnable = pConf->RunSlotPrbMapBySymbolEnable;
-+    p_xran_dev_ctx->LiteOnIgnoreUPSectionIdEnable = pConf->LiteOnIgnoreUPSectionIdEnable;
-     p_xran_dev_ctx->dssEnable = pConf->dssEnable;
-     p_xran_dev_ctx->dssPeriod = pConf->dssPeriod;
-     for(i=0; i<pConf->dssPeriod; i++) {
-@@ -4034,6 +4089,24 @@ xran_get_slot_idx (uint32_t PortId, uint32_t *nFrameIdx, uint32_t *nSubframeIdx,
     return tti;
 }
@@ -1880,7 +1723,7 @@ index 7c472d7..db03d94 100644
 int32_t
 xran_set_debug_stop(int32_t value, int32_t count)
 {
-@@ -4208,7 +4281,7 @@ int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, str
+@@ -4208,7 +4280,7 @@ int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, str
     int32_t i = 0, j = 0, nPrbElm = 0;
     int16_t iqwidth = p_PrbMapIn->prbMap[0].iqWidth;
     struct xran_prb_elm *p_prb_elm_src, *p_prb_elm_dst;
@@ -1889,7 +1732,7 @@ index 7c472d7..db03d94 100644
     int32_t nRBStart_tmp, nRBremain, nStartSymb, nEndSymb, nRBStart, nRBEnd, nRBSize;
     // int32_t eth_xran_up_headers_sz = sizeof(struct eth_xran_up_pkt_hdr);
     // int32_t nmaxRB = (mtu - eth_xran_up_headers_sz - RTE_PKTMBUF_HEADROOM)/XRAN_PAYLOAD_1_RB_SZ(iqwidth);
-@@ -4217,7 +4290,6 @@ int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, str
+@@ -4217,7 +4289,6 @@ int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, str
     if (mtu==9600)
         nmaxRB--;   //for some reason when mtu is 9600, only 195 RB can be sent, not 196
@@ -1897,7 +1740,7 @@ index 7c472d7..db03d94 100644
     memcpy(p_PrbMapOut, p_PrbMapIn, sizeof(struct xran_prb_map));
     for(i = 0; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++)
     {
-@@ -4292,26 +4364,30 @@ int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, str
+@@ -4292,27 +4363,23 @@ int32_t xran_init_PrbMap_by_symbol_from_cfg(struct xran_prb_map* p_PrbMapIn, str
     for(; i < XRAN_NUM_OF_SYMBOL_PER_SLOT; i++)
     {
@@ -1906,8 +1749,7 @@ index 7c472d7..db03d94 100644
 -                prbMapTemp[nPrbElm].numSymb++;
 -        }
 -        else
-+        if((prbMapTemp[i].nRBSize != 0))
+-        {
-         {
 -            nPrbElm++;
 -            prbMapTemp[nPrbElm].nStartSymb = prbMapTemp[i].nStartSymb;
 -            prbMapTemp[nPrbElm].nRBStart = prbMapTemp[i].nRBStart;
@@ -1922,31 +1764,27 @@ index 7c472d7..db03d94 100644
 -
 -            nRBStart = prbMapTemp[i].nRBStart;
 -            nRBSize = prbMapTemp[i].nRBSize;
-+            if (false) // Force it to generate multiple prbMapElm, one for each symbol even if they are of the same RBs
+-        }
-+            //if((nRBStart == prbMapTemp[i].nRBStart) && (nRBSize == prbMapTemp[i].nRBSize))
+        /* force using a separate section for each symbol in one multisection CP (both DL and UL) message;
-+            {
+         * when generating DL UP, symbol index should be within nStartSymb and (nStartSymb + numSymb);
-+                    prbMapTemp[nPrbElm].numSymb++;
+         * nPrbElm doesn't have any affect on UL UP */
-+            }
+        nPrbElm++;
-+            else
+        prbMapTemp[nPrbElm].nStartSymb = prbMapTemp[i].nStartSymb;
-+            {
+        prbMapTemp[nPrbElm].nRBStart = prbMapTemp[i].nRBStart;
-+                nPrbElm++;
+        prbMapTemp[nPrbElm].nRBSize = prbMapTemp[i].nRBSize;
-+                prbMapTemp[nPrbElm].nStartSymb = prbMapTemp[i].nStartSymb;
+        prbMapTemp[nPrbElm].nBeamIndex = prbMapTemp[i].nBeamIndex;
-+                prbMapTemp[nPrbElm].nRBStart = prbMapTemp[i].nRBStart;
+        prbMapTemp[nPrbElm].bf_weight_update = prbMapTemp[i].bf_weight_update;
-+                prbMapTemp[nPrbElm].nRBSize = prbMapTemp[i].nRBSize;
+        prbMapTemp[nPrbElm].compMethod = prbMapTemp[i].compMethod;
-+                prbMapTemp[nPrbElm].nBeamIndex = prbMapTemp[i].nBeamIndex;
+        prbMapTemp[nPrbElm].iqWidth = prbMapTemp[i].iqWidth;
-+                prbMapTemp[nPrbElm].bf_weight_update = prbMapTemp[i].bf_weight_update;
+        prbMapTemp[nPrbElm].ScaleFactor = prbMapTemp[i].ScaleFactor;
-+                prbMapTemp[nPrbElm].compMethod = prbMapTemp[i].compMethod;
+        prbMapTemp[nPrbElm].reMask = prbMapTemp[i].reMask;
-+                prbMapTemp[nPrbElm].iqWidth = prbMapTemp[i].iqWidth;
+        prbMapTemp[nPrbElm].BeamFormingType = prbMapTemp[i].BeamFormingType;
-+                prbMapTemp[nPrbElm].ScaleFactor = prbMapTemp[i].ScaleFactor;
-+                prbMapTemp[nPrbElm].reMask = prbMapTemp[i].reMask;
-+                prbMapTemp[nPrbElm].BeamFormingType = prbMapTemp[i].BeamFormingType;
 +
-+                nRBStart = prbMapTemp[i].nRBStart;
+        nRBStart = prbMapTemp[i].nRBStart;
-+                nRBSize = prbMapTemp[i].nRBSize;
+        nRBSize = prbMapTemp[i].nRBSize;
-+            }
-         }
     }
+     for(i = 0; i < nPrbElm; i++)
 diff --git a/fhi_lib/lib/src/xran_mem_mgr.c b/fhi_lib/lib/src/xran_mem_mgr.c
 index e1dcb6c..b3c3fae 100644
 --- a/fhi_lib/lib/src/xran_mem_mgr.c
@@ -1980,7 +1818,7 @@ index 7d4a5d0..b9b44ac 100644
 #endif
 }
 diff --git a/fhi_lib/lib/src/xran_rx_proc.c b/fhi_lib/lib/src/xran_rx_proc.c
-index e7056f4..34b6d3b 100644
+index e7056f4..4941360 100644
 --- a/fhi_lib/lib/src/xran_rx_proc.c
 +++ b/fhi_lib/lib/src/xran_rx_proc.c
 @@ -35,7 +35,11 @@
@@ -1995,127 +1833,16 @@ index e7056f4..34b6d3b 100644
 #include <rte_common.h>
 #include <rte_eal.h>
-@@ -339,13 +343,33 @@ int32_t xran_process_srs_sym(void *arg,
+@@ -537,6 +541,9 @@ int32_t xran_process_rx_sym(void *arg,
-             pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFHSrsRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData;
-             if(pRbMap)
-             {
-            prbMapElm = &pRbMap->prbMap[sect_id];
-                if(sect_id >= pRbMap->nPrbElm)
-+                u_int8_t section_id_tmp;    // hack for LiteON FR2 : receive UP section ID = 13
-+                u_int8_t prb_elem_id_tmp;   // hack for LiteON FR2 : receive UP section ID = 13
-+                if(0 == p_xran_dev_ctx->LiteOnIgnoreUPSectionIdEnable) {
-+                    section_id_tmp = prb_elem_id_tmp = sect_id;
-+                } else {
-+                    /** Get the prb_elem_id */
-+                    int8_t xran_port = xran_dev_ctx_get_port_id(p_xran_dev_ctx);
-+                    u_int8_t mixed_ul_sym_start = 0;
-+                    if (xran_fs_get_slot_type(xran_port, CC_ID, tti, XRAN_SLOT_TYPE_SP)) {
-+                        mixed_ul_sym_start = XRAN_NUM_OF_SYMBOL_PER_SLOT - xran_fs_get_num_ul_sym_sp(xran_port, CC_ID, tti);
-+                    }
-+
-+                    section_id_tmp = symb_id - mixed_ul_sym_start;     // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                    prb_elem_id_tmp = section_id_tmp;                  // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                    //Note for future reference when using MTU 1500
-+                    //prb_elem_id_tmp = 2*section_id_tmp;              // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                    //if (start_prbu !=0)                              // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                    //    prb_elem_id_tmp++;                           // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                }
-+
-+                prbMapElm = &pRbMap->prbMap[prb_elem_id_tmp /*sect_id*/];
-+                if(/*sect_id*/ prb_elem_id_tmp >= pRbMap->nPrbElm)
-                 {
-                print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id,pRbMap->nPrbElm);
-                *mb_free = MBUF_FREE;
-                return size;
-            }
-+                    print_err("sect_id %d !=pRbMap->nPrbElm %d\n", sect_id,pRbMap->nPrbElm);
-+                    *mb_free = MBUF_FREE;
-+                    return size;
-+                }
-             }
-             else
-             {
-@@ -397,7 +421,25 @@ int32_t xran_process_srs_sym(void *arg,
-                     else */
-                     {
-                     struct xran_section_desc *p_sec_desc = NULL;
-                    prbMapElm = &pRbMap->prbMap[sect_id];
-+                    u_int8_t section_id_tmp;    // hack for LiteON FR2 : receive UP section ID = 13
-+                    u_int8_t prb_elem_id_tmp;   // hack for LiteON FR2 : receive UP section ID = 13
-+                    if(0 == p_xran_dev_ctx->LiteOnIgnoreUPSectionIdEnable) {
-+                        section_id_tmp = prb_elem_id_tmp = sect_id;
-+                    } else {
-+                        int8_t xran_port = xran_dev_ctx_get_port_id(p_xran_dev_ctx);
-+                        u_int8_t mixed_ul_sym_start = 0;
-+                        if (xran_fs_get_slot_type(xran_port, CC_ID, tti, XRAN_SLOT_TYPE_SP)) {
-+                            mixed_ul_sym_start = XRAN_NUM_OF_SYMBOL_PER_SLOT - xran_fs_get_num_ul_sym_sp(xran_port, CC_ID, tti);
-+                        }
-+                        u_int8_t section_id_tmp = symb_id - mixed_ul_sym_start;     // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                        prb_elem_id_tmp = section_id_tmp;                           // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                        //Note for future reference when using MTU 1500
-+                        //prb_elem_id_tmp = 2*section_id_tmp;                       // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                        //if (start_prbu !=0)                                       // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                        //    prb_elem_id_tmp++;                                    // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                    }
-+
-+                    prbMapElm = &pRbMap->prbMap[prb_elem_id_tmp /*sect_id*/];
-     //                    sec_desc_idx = 0;//prbMapElm->nSecDesc[symb_id];
-                         sec_desc_idx = prbMapElm->nSecDesc[symb_id];
-@@ -537,14 +579,33 @@ int32_t xran_process_rx_sym(void *arg,
         pos = (char*) p_xran_dev_ctx->sFrontHaulRxBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers[symb_id].pData;
         pRbMap = (struct xran_prb_map *) p_xran_dev_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[tti % XRAN_N_FE_BUF_LEN][CC_ID][Ant_ID].sBufferList.pBuffers->pData;
         if(pRbMap){
-            /** Get the prb_elem_id */
+            if (p_xran_dev_ctx->RunSlotPrbMapBySymbolEnable) {
-+            u_int8_t section_id_tmp;    // hack for LiteON FR2 : receive UP section ID = 13
+              sect_id = (pRbMap->nPrbElm == XRAN_NUM_OF_SYMBOL_PER_SLOT) ? symb_id : symb_id - (XRAN_NUM_OF_SYMBOL_PER_SLOT - pRbMap->nPrbElm);
-+            u_int8_t prb_elem_id_tmp;   // hack for LiteON FR2 : receive UP section ID = 13
-+            if(0 == p_xran_dev_ctx->LiteOnIgnoreUPSectionIdEnable) {
-+                section_id_tmp = prb_elem_id_tmp = sect_id;
-+            } else {
-+                /** Get the prb_elem_id */
-+                int8_t xran_port = xran_dev_ctx_get_port_id(p_xran_dev_ctx);
-+                u_int8_t mixed_ul_sym_start = 0;
-+                if (xran_fs_get_slot_type(xran_port, CC_ID, tti, XRAN_SLOT_TYPE_SP)) {
-+                    mixed_ul_sym_start = XRAN_NUM_OF_SYMBOL_PER_SLOT - xran_fs_get_num_ul_sym_sp(xran_port, CC_ID, tti);
-+                }
-+
-+                section_id_tmp = symb_id - mixed_ul_sym_start;     // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                prb_elem_id_tmp = section_id_tmp;                  // hack for LiteON FR2 : receive UP section ID = 13, MTU 9000
-+                //Note for future reference when using MTU 1500
-+                //prb_elem_id_tmp = 2*section_id_tmp;              // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                //if (start_prbu !=0)                              // For LiteON FR2 : receive UP section ID = 13, MTU 1500
-+                //    prb_elem_id_tmp++;                           // For LiteON FR2 : receive UP section ID = 13, MTU 1500
 +            }
-+
+             /** Get the prb_elem_id */
             total_sections=0;
             if(pRbMap->prbMap[0].bf_weight.extType == 1)
-             {
-                 for(i=0 ; i < pRbMap->nPrbElm ; i++)
-                 {
-                     total_sections += pRbMap->prbMap[i].bf_weight.numSetBFWs;
-                    if(total_sections >= (sect_id + 1))
-+                    if(total_sections >= (/*sect_id*/ section_id_tmp + 1))
-                     {
-                         prb_elem_id = i;
-                         break;
-@@ -553,7 +614,7 @@ int32_t xran_process_rx_sym(void *arg,
-             }
-             else
-             {
-                prb_elem_id = sect_id;
-+                prb_elem_id = prb_elem_id_tmp; /*sect_id*/;
-             }
-             prbMapElm = &pRbMap->prbMap[prb_elem_id];
-@@ -597,7 +658,7 @@ int32_t xran_process_rx_sym(void *arg,
-                     if(p_sec_desc){
-                         mb = p_sec_desc->pCtrl;
-                         if(mb){
-                           rte_pktmbuf_free(mb);
-+                            rte_pktmbuf_free(mb);
-                         }
-                         p_sec_desc->pData         = iq_data_start;
-                         p_sec_desc->pCtrl         = mbuf;
 diff --git a/fhi_lib/lib/src/xran_timer.c b/fhi_lib/lib/src/xran_timer.c
 index 14a6a41..55182d8 100644
 --- a/fhi_lib/lib/src/xran_timer.c

--- a/doc/ORAN_FHI7.2_Tutorial.md
+++ b/doc/ORAN_FHI7.2_Tutorial.md
@@ -565,12 +565,6 @@ dl_tuning_special_slot=0x13b6
 #### LITEON
-The OAI configuration file [`gnb.sa.band78.273prb.fhi72.4x4-liteon.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.273prb.fhi72.4x4-liteon.conf) corresponds to:
- TDD pattern `DDDSU`, 2.5ms
- Bandwidth 100MHz
- MTU 1500
- MTU 9216: v02.00.10
 ##### RU configuration
 SSH to the unit as user `user`. Write `enable` in the terminal to enter the configuration console; the password should be in the user guide. Use the command `show oru-status` to check the RU status. The output should be similar to:
@@ -593,7 +587,15 @@ Once the RU is PTP synced, and RF state and DPD are `Ready`, write `configure te
 - DU MAC address
 ...
-The configuration mode example:
+###### FR1
+The OAI configuration file [`gnb.sa.band78.273prb.fhi72.4x4-liteon.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.273prb.fhi72.4x4-liteon.conf) corresponds to:
+- TDD pattern `DDDSU`, 2.5ms
+- Bandwidth 100MHz
+- MTU 1500
+- MTU 9216: v02.00.10
+The RU configuration mode example:
 ```bash
 compression-bit 9 # set IQ bitwidth for PxSCH/PRACH
 eAXC_id 4 5 6 7 # set PRACH eAxC IDs
@@ -601,6 +603,21 @@ jumboframe 1 # enable jumbo frame
 ...
 ```
+###### FR2
+The OAI configuration file [`gnb.sa.band257.66prb.fhi72.2x2-liteon.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.66prb.fhi72.2x2-liteon.conf) corresponds to:
+- TDD pattern `DDDDDDDSUU`, 1.25ms
+- Bandwidth 100MHz
+- FW v02.00.07
+- DL uses jumbo frame, UL uses standard MTU of 1500 bytes
+The RU configuration mode example:
+```bash
+compression-bit 8 # set IQ bitwidth for PxSCH/PRACH
+eAXC_id 0 1 # set PRACH eAxC IDs
+...
+```
 #### VVDN LPRU
 **Version 3.x**
@@ -1012,6 +1029,7 @@ Edit the sample OAI gNB configuration file and check following parameters:
      [Memory in DPDK](https://www.dpdk.org/memory-in-dpdk-part-2-deep-dive-into-iova/)
  * `owdm_enable`: used for eCPRI One-Way Delay Measurements; it depends if the RU supports it; if not set to 1 (enabled), default value is 0 (disabled)
  * `fh_config`
+    * `RunSlotPrbMapBySymbol`: enable CP multisection (one symbol per section); default value is 0
    *  DU delay profile (`T1a` and `Ta4`): pairs of numbers `(x, y)` specifying minimum and maximum delays
    * `ru_config`: RU-specific configuration:
      * `iq_width`: Width of DL/UL IQ samples: if 16, no compression, if <16, applies

--- a/radio/fhi_72/CMakeLists.txt
+++ b/radio/fhi_72/CMakeLists.txt
@@ -16,10 +16,10 @@ add_library(oran_fhlib_5g MODULE
            oran-init.c
 )
-set(F_VERSION 6.1.8)
+set(F_VERSION 6.1.9)
 find_package(xran REQUIRED)
-if(xran_VERSION MATCHES "5.*")
+if(xran_VERSION VERSION_GREATER_EQUAL 5 AND xran_VERSION VERSION_LESS 6)
  message(FATAL_ERROR "xran E release not supported starting from tag 2026.w08.\nPlease switch to F version ${F_VERSION}")
 elseif(xran_VERSION VERSION_EQUAL F_VERSION)
  target_compile_definitions(oran_fhlib_5g PRIVATE F_RELEASE)

--- a/radio/fhi_72/oran-config.c
+++ b/radio/fhi_72/oran-config.c
@@ -432,12 +432,10 @@ void print_fh_config(const struct xran_fh_config *fh_config)
 #if defined F_RELEASE
  printf("\
  RunSlotPrbMapBySymbolEnable %d\n\
-  LiteOnIgnoreUPSectionIdEnable %d\n\
  dssEnable %d\n\
  dssPeriod %d\n\
  technology[XRAN_MAX_DSS_PERIODICITY] (not filled as DSS disabled)\n",
      fh_config->RunSlotPrbMapBySymbolEnable,
-      fh_config->LiteOnIgnoreUPSectionIdEnable,
      fh_config->dssEnable,
      fh_config->dssPeriod);
 #endif
@@ -777,8 +775,7 @@ static bool set_fh_prach_config(void *mplane_api,
                                const uint32_t max_num_ant,
                                const paramdef_t *prachp,
                                int nprach,
-                                struct xran_prach_config *prach_config,
+                                struct xran_prach_config *prach_config)
-                                bool liteon_prach_eAxC_offset)
 {
  const split7_config_t *s7cfg = &oai0->split7;
@@ -814,11 +811,8 @@ static bool set_fh_prach_config(void *mplane_api,
  xran_mplane_t *xran_mplane = (xran_mplane_t *)mplane_api;
  prach_config->eAxC_offset = xran_mplane->prach_offset;
 #else
-  uint8_t offset = *gpd(prachp, nprach, ORAN_PRACH_CONFIG_EAXC_OFFSET)->u8ptr;
+  const paramdef_t *pd = gpd(prachp, nprach, ORAN_PRACH_CONFIG_EAXC_OFFSET);
-  if (liteon_prach_eAxC_offset)
+  prach_config->eAxC_offset = pd->paramflags & PARAMFLAG_PARAMSET ? *pd->u8ptr : max_num_ant;
-    prach_config->eAxC_offset = offset;
-  else
-    prach_config->eAxC_offset = (offset != 0) ? offset : max_num_ant;
 #endif
  g_kbar = *gpd(prachp, nprach, ORAN_PRACH_CONFIG_KBAR)->uptr;
@@ -964,13 +958,9 @@ static bool set_fh_config(void *mplane_api, int ru_idx, int num_rus, enum xran_c
  fh_config->prachEnable = 1; // enable PRACH
  fh_config->srsEnable = 0; // enable SRS; used only if XRAN_CATEGORY_B
  // For LiteOn E release, no need to take care of prach eAxC_offset. xran lib is hacked to handle it.
-  bool liteon_prach_eAxC_offset = false;
 #if defined F_RELEASE
  fh_config->srsEnableCp = 0; // enable SRS CP; used only if XRAN_CATEGORY_B
  fh_config->SrsDelaySym = 0; // number of SRS delay symbols; used only if XRAN_CATEGORY_B
-  fh_config->RunSlotPrbMapBySymbolEnable    = *gpd(fhp, nfh, ORAN_CONFIG_RunSlotPrbMapBySymbol)->uptr;    // enable RunSlotPrbMapBySymbol
-  fh_config->LiteOnIgnoreUPSectionIdEnable  = *gpd(fhp, nfh, ORAN_CONFIG_LiteOnIgnoreUPSectionId)->uptr;  // enable LiteOnIgnoreUPSectionId
-  liteon_prach_eAxC_offset = fh_config->LiteOnIgnoreUPSectionIdEnable;
 #endif
  fh_config->puschMaskEnable = 0; // enable PUSCH mask; only used if id = O_RU
  fh_config->puschMaskSlot = 0; // specific which slot PUSCH channel masked; only used if id = O_RU
@@ -982,7 +972,7 @@ static bool set_fh_config(void *mplane_api, int ru_idx, int num_rus, enum xran_c
  fh_config->GPS_Alpha = 0; // refers to alpha as defined in section 9.7.2 of ORAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns); offset_nsec = (pConf->GPS_Beta - offset_sec * 100) * 1e7 + pConf->GPS_Alpha
  fh_config->GPS_Beta = 0; // beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767; offset_sec = pConf->GPS_Beta / 100
-  if (!set_fh_prach_config(mplane_api, oai0, fh_config->neAxc, prachp, nprach, &fh_config->prach_conf, liteon_prach_eAxC_offset))
+  if (!set_fh_prach_config(mplane_api, oai0, fh_config->neAxc, prachp, nprach, &fh_config->prach_conf))
    return false;
  /* SRS only used if XRAN_CATEGORY_B
    Note: srs_config->eAxC_offset >= prach_config->eAxC_offset + PRACH */
@@ -1014,6 +1004,8 @@ static bool set_fh_config(void *mplane_api, int ru_idx, int num_rus, enum xran_c
  fh_config->max_sections_per_symbol = 0; // not used in xran
 #if defined F_RELEASE
+  fh_config->RunSlotPrbMapBySymbolEnable = *gpd(fhp, nfh, ORAN_CONFIG_CP_MULTISECTION)->uptr; // enable PRB mapping by symbol with multisection
  fh_config->dssEnable = 0; // enable DSS (extension-9)
  fh_config->dssPeriod = 0; // DSS pattern period for LTE/NR
  // fh_config->technology[XRAN_MAX_DSS_PERIODICITY] // technology array represents slot is LTE(0)/NR(1); used only if DSS enabled

--- a/radio/fhi_72/oran-init.c
+++ b/radio/fhi_72/oran-init.c
@@ -315,16 +315,8 @@ static void oran_allocate_buffers(void *handle,
  };
 #if defined F_RELEASE
-  uint32_t size_of_prb_map;
+  uint32_t numPrbElm = (fh_config->RunSlotPrbMapBySymbolEnable) ? XRAN_NUM_OF_SYMBOL_PER_SLOT : xran_get_num_prb_elm(&dlPm, mtu);
-  if (fh_config->RunSlotPrbMapBySymbolEnable) {
+  uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (numPrbElm);
-    // For Liteon FR2 with RunSlotPrbMapBySymbolEnable, xran_prb_map will have xran_prb_elm prbMap[14]
-    size_of_prb_map  = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (XRAN_NUM_OF_SYMBOL_PER_SLOT);
-  }
-  else {
-    // For non-Liteon w/o RunSlotPrbMapBySymbolEnable, xran_prb_map will have xran_prb_elm prbMap[1]
-    uint32_t numPrbElm = xran_get_num_prb_elm(&dlPm, mtu);
-    size_of_prb_map  = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (numPrbElm);
-  }
 #endif
  // PDSCH

--- a/radio/fhi_72/oran-params.h
+++ b/radio/fhi_72/oran-params.h
@@ -106,8 +106,7 @@
 #define CONFIG_STRING_ORAN_FH "fh_config"
-#define ORAN_CONFIG_RunSlotPrbMapBySymbol "RunSlotPrbMapBySymbol"
+#define ORAN_CONFIG_CP_MULTISECTION "RunSlotPrbMapBySymbol"
-#define ORAN_CONFIG_LiteOnIgnoreUPSectionId "LiteOnIgnoreUPSectionId"
 #define ORAN_FH_CONFIG_T1A_CP_DL "T1a_cp_dl"
 #define ORAN_FH_CONFIG_T1A_CP_UL "T1a_cp_ul"
 #define ORAN_FH_CONFIG_T1A_UP "T1a_up"
@@ -117,8 +116,7 @@
 // clang-format off
 #define ORAN_FH_DESC { \
-  {ORAN_CONFIG_RunSlotPrbMapBySymbol,   "RunSlotPrbMapBySymbol\n",     PARAMFLAG_BOOL,      .uptr=NULL, .defuintval=0,     TYPE_UINT,      0}, \
+  {ORAN_CONFIG_CP_MULTISECTION,         "RunSlotPrbMapBySymbol\n",     PARAMFLAG_BOOL,      .iptr=NULL, .defintval=0,      TYPE_INT32,     0}, \
-  {ORAN_CONFIG_LiteOnIgnoreUPSectionId, "Liteon Ignore Section Id\n",  PARAMFLAG_BOOL,      .uptr=NULL, .defuintval=0,     TYPE_UINT,      0}, \
  {ORAN_FH_CONFIG_T1A_CP_DL,            "T1a_cp_dl" ORAN_FH_HLP_CPLT,  PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
  {ORAN_FH_CONFIG_T1A_CP_UL,            "T1a_cp_ul" ORAN_FH_HLP_CPLT,  PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
  {ORAN_FH_CONFIG_T1A_UP,               "T1a_up" ORAN_FH_HLP_CPLT,     PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
@@ -145,7 +143,7 @@
 // clang-format off
 #define ORAN_PRACH_DESC {\
-  {ORAN_PRACH_CONFIG_EAXC_OFFSET, "RU's eAxC offset for PRACH\n", PARAMFLAG_MANDATORY, .u8ptr=NULL, .defuintval=0, TYPE_UINT8, 0}, \
+  {ORAN_PRACH_CONFIG_EAXC_OFFSET, "RU's eAxC offset for PRACH\n", 0,                   .u8ptr=NULL, .defuintval=0, TYPE_UINT8, 0}, \
  {ORAN_PRACH_CONFIG_KBAR,        "PRACH guard interval\n",       0,                   .uptr=NULL,  .defuintval=4, TYPE_UINT,  0}, \
 }
 // clang-format on

--- a/targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.66prb.fhi72.2x2-liteon.conf
+++ b/targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.66prb.fhi72.2x2-liteon.conf
+Active_gNBs = ( "inria-gnb");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+gNBs =
+(
+ {
+    ////////// Identification parameters:
+    gNB_ID    =  0xe99;
+   cell_type =  "CELL_MACRO_GNB";
+    gNB_name  =  "inria-gnb";
+    // Tracking area code, 0x0000 and 0xfffe are reserved values
+    tracking_area_code  =  1;
+    plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ( { sst = 1; }); });
+    nr_cellid = 1;
+    ////////// Physical parameters:
+    pdsch_AntennaPorts_XP = 2;
+    pusch_AntennaPorts    = 2;
+    maxMIMO_layers        = 2;
+    do_CSIRS              = 1;
+    do_SRS                = 0;
+    min_rxtxtime          = 4;
+    servingCellConfigCommon = (
+    {
+ #spCellConfigCommon
+      physCellId                                                    = 0;
+#  downlinkConfigCommon
+    #frequencyInfoDL
+      # center frequency = 28701.12 MHz
+      # selected SSB frequency = 28691.04 MHz
+      absoluteFrequencySSB                                          = 2090683;
+      dl_frequencyBand                                              = 257;
+      # frequency point A = 28653.6 MHz
+      dl_absoluteFrequencyPointA                                    = 2090059;
+      #scs-SpecificCarrierList
+        dl_offstToCarrier                                           = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+        dl_subcarrierSpacing                                        = 3;
+        dl_carrierBandwidth                                         = 66;
+     #initialDownlinkBWP
+      #genericParameters
+       initialDLBWPlocationAndBandwidth                             = 17875;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+        initialDLBWPsubcarrierSpacing                               = 3;
+      #pdcch-ConfigCommon
+        initialDLBWPcontrolResourceSetZero                          = 2;
+        initialDLBWPsearchSpaceZero                                 = 0;
+  #uplinkConfigCommon
+     #frequencyInfoUL
+      ul_frequencyBand                                              = 257;
+      #scs-SpecificCarrierList
+      ul_offstToCarrier                                             = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+      ul_subcarrierSpacing                                          = 3;
+      ul_carrierBandwidth                                           = 66;
+      pMax                                                          = 20;
+     #initialUplinkBWP
+      #genericParameters
+        initialULBWPlocationAndBandwidth                            = 17875;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+        initialULBWPsubcarrierSpacing                               = 3;
+      #rach-ConfigCommon
+        #rach-ConfigGeneric
+          prach_ConfigurationIndex                                  = 135;
+#prach_msg1_FDM
+#0 = one, 1=two, 2=four, 3=eight
+          prach_msg1_FDM                                            = 0;
+          prach_msg1_FrequencyStart                                 = 0;
+          zeroCorrelationZoneConfig                                 = 15;
+          preambleReceivedTargetPower                               = -118;
+#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
+          preambleTransMax                                          = 8;
+#powerRampingStep
+# 0=dB0,1=dB2,2=dB4,3=dB6
+        powerRampingStep                                            = 2;
+#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+        ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR                = 3;
+#one (0..15) 4,8,12,16,...60,64
+        ssb_perRACH_OccasionAndCB_PreamblesPerSSB                   = 15;
+#ra_ContentionResolutionTimer
+#(0..7) 8,16,24,32,40,48,56,64
+        ra_ContentionResolutionTimer                                = 7;
+        rsrp_ThresholdSSB                                           = 19;
+#prach-RootSequenceIndex_PR
+#1 = 839, 2 = 139
+        prach_RootSequenceIndex_PR                                  = 2;
+        prach_RootSequenceIndex                                     = 1;
+        # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
+        #
+        msg1_SubcarrierSpacing                                      = 3,
+# restrictedSetConfig
+# 0=unrestricted, 1=restricted type A, 2=restricted type B
+        restrictedSetConfig                                         = 0,
+# this is the offset between the last PRACH preamble power and the Msg3 PUSCH, 2 times the field value in dB
+        msg3_DeltaPreamble                                          = 0;
+        p0_NominalWithGrant                                         = -90;
+# pucch-ConfigCommon setup :
+# pucchGroupHopping
+# 0 = neither, 1= group hopping, 2=sequence hopping
+        pucchGroupHopping                                           = 0;
+        hoppingId                                                   = 40;
+        p0_nominal                                                  = -90;
+      ssb_PositionsInBurst_Bitmap                                   = 1;
+# ssb_periodicityServingCell
+# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
+      ssb_periodicityServingCell                                    = 1;
+# dmrs_TypeA_position
+# 0 = pos2, 1 = pos3
+      dmrs_TypeA_Position                                           = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+      subcarrierSpacing                                             = 3;
+  #tdd-UL-DL-ConfigurationCommon
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+      referenceSubcarrierSpacing                                    = 3;
+      # pattern1
+      # dl_UL_TransmissionPeriodicity
+      # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
+      dl_UL_TransmissionPeriodicity                                 = 3;
+      nrofDownlinkSlots                                             = 7;
+      nrofDownlinkSymbols                                           = 6;
+      nrofUplinkSlots                                               = 2;
+      nrofUplinkSymbols                                             = 4;
+  ssPBCH_BlockPower                                                 = 0;
+  }
+  );
+    # ------- SCTP definitions
+    SCTP :
+    {
+        # Number of streams to use in input/output
+        SCTP_INSTREAMS  = 2;
+        SCTP_OUTSTREAMS = 2;
+    };
+    ////////// AMF parameters:
+    amf_ip_address = ({ ipv4 = "172.21.6.4"; });
+    NETWORK_INTERFACES :
+    {
+        GNB_IPV4_ADDRESS_FOR_NG_AMF              = "172.21.16.51";
+        GNB_IPV4_ADDRESS_FOR_NGU                 = "172.21.16.51";
+        GNB_PORT_FOR_S1U                         = 2152; # Spec 2152
+    };
+  }
+);
+MACRLCs = (
+{
+  num_cc                      = 1;
+  tr_s_preference             = "local_L1";
+  tr_n_preference             = "local_RRC";
+  pusch_TargetSNRx10          = 200;
+  pucch_TargetSNRx10          = 200;
+  pusch_FailureThres          = 1000;
+  #ul_bler_target_upper        =.02;
+  #ul_bler_target_lower        =.01;
+  #dl_bler_target_upper        =.15;
+  #dl_bler_target_lower        =.05
+  set_analog_beamforming      = "lophy";
+  beam_duration               = 1;
+  beams_per_period            = 1;
+  beam_weights = [1];
+}
+);
+L1s = (
+{
+  num_cc = 1;
+  tr_n_preference = "local_mac";
+  prach_dtx_threshold = 250;
+  pucch0_dtx_threshold = 100;
+  pusch_dtx_threshold = -200;
+  max_ldpc_iterations = 10;
+  tx_amp_backoff_dB = 18;
+  L1_rx_thread_core = 10;
+  L1_tx_thread_core = 11;
+  phase_compensation = 1;
+}
+);
+RUs = (
+{
+  local_rf       = "no";
+  nb_tx          = 2;
+  nb_rx          = 2;
+  att_tx         = 0
+  att_rx         = 0;
+  bands          = [257];
+  nr_scs_for_raster = 3;
+  max_pdschReferenceSignalPower = -40;
+  max_rxgain                    = 60;
+  #sf_extension                  = 0;
+  eNB_instances  = [0];
+  ru_thread_core = 9;
+  sl_ahead       = 10;
+  tr_preference  = "raw_if4p5";
+  do_precoding = 0;
+}
+);
+security = {
+  # preferred ciphering algorithms
+  # the first one of the list that an UE supports in chosen
+  # valid values: nea0, nea1, nea2, nea3
+  ciphering_algorithms = ( "nea0" );
+  # preferred integrity algorithms
+  # the first one of the list that an UE supports in chosen
+  # valid values: nia0, nia1, nia2, nia3
+  integrity_algorithms = ( "nia2", "nia0" );
+  # setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
+  # what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
+  drb_ciphering = "yes";
+  drb_integrity = "no";
+};
+log_config :
+{
+  global_log_level = "info";
+  hw_log_level     = "info";
+  phy_log_level    = "info";
+  mac_log_level    = "info";
+  rlc_log_level    = "info";
+  pdcp_log_level   = "info";
+  rrc_log_level    = "info";
+  ngap_log_level   = "info";
+  f1ap_log_level   = "info";
+};
+fhi_72 = {
+  dpdk_devices = ("0000:c1:11.0", "0000:c1:11.1"); # one VF can be used as well
+  system_core = 6;
+  io_core = 7;
+  worker_cores = (8);
+  ru_addr = ("E8:C7:4F:1E:C7:5B", "E8:C7:4F:1E:C7:5B");
+  mtu = 9216;
+  fh_config = ({
+    RunSlotPrbMapBySymbol = 1;
+    T1a_cp_dl = (110, 111);
+    T1a_cp_ul = (69, 70);
+    T1a_up = (30, 64);
+    Ta4 = (30, 64);
+    ru_config = {
+      iq_width = 8;
+      iq_width_prach = 8;
+    };
+    prach_config = {
+      eAxC_offset = 0;
+      kbar = 0;
+    };
+  });
+};