Merge remote-tracking branch 'origin/liteon-fr2-cleanup' into integration_2026_w12 (!3956)

[FHI72] [xran F] Revert and simplify the code for Liteon FR2 interoperability

The MR !3668 introduced a lot of unnecessary changes. This MR removes useless
code in both OAI and xran F release library.

doc/ORAN_FHI7.2_Tutorial.md

@@ -565,12 +565,6 @@ dl_tuning_special_slot=0x13b6
 
 #### LITEON
 
-The OAI configuration file [`gnb.sa.band78.273prb.fhi72.4x4-liteon.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.273prb.fhi72.4x4-liteon.conf) corresponds to:
-- TDD pattern `DDDSU`, 2.5ms
-- Bandwidth 100MHz
-- MTU 1500
-- MTU 9216: v02.00.10
-
 ##### RU configuration
 
 SSH to the unit as user `user`. Write `enable` in the terminal to enter the configuration console; the password should be in the user guide. Use the command `show oru-status` to check the RU status. The output should be similar to:
@@ -593,7 +587,15 @@ Once the RU is PTP synced, and RF state and DPD are `Ready`, write `configure te
 - DU MAC address
 ...
 
-The configuration mode example:
+###### FR1
+
+The OAI configuration file [`gnb.sa.band78.273prb.fhi72.4x4-liteon.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.273prb.fhi72.4x4-liteon.conf) corresponds to:
+- TDD pattern `DDDSU`, 2.5ms
+- Bandwidth 100MHz
+- MTU 1500
+- MTU 9216: v02.00.10
+
+The RU configuration mode example:
 ```bash
 compression-bit 9 # set IQ bitwidth for PxSCH/PRACH
 eAXC_id 4 5 6 7 # set PRACH eAxC IDs
@@ -601,6 +603,21 @@ jumboframe 1 # enable jumbo frame
 ...
 ```
 
+###### FR2
+
+The OAI configuration file [`gnb.sa.band257.66prb.fhi72.2x2-liteon.conf`](../targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.66prb.fhi72.2x2-liteon.conf) corresponds to:
+- TDD pattern `DDDDDDDSUU`, 1.25ms
+- Bandwidth 100MHz
+- FW v02.00.07
+- DL uses jumbo frame, UL uses standard MTU of 1500 bytes
+
+The RU configuration mode example:
+```bash
+compression-bit 8 # set IQ bitwidth for PxSCH/PRACH
+eAXC_id 0 1 # set PRACH eAxC IDs
+...
+```
+
 #### VVDN LPRU
 
 **Version 3.x**
@@ -1012,6 +1029,7 @@ Edit the sample OAI gNB configuration file and check following parameters:
       [Memory in DPDK](https://www.dpdk.org/memory-in-dpdk-part-2-deep-dive-into-iova/)
   * `owdm_enable`: used for eCPRI One-Way Delay Measurements; it depends if the RU supports it; if not set to 1 (enabled), default value is 0 (disabled)
   * `fh_config`
+    * `RunSlotPrbMapBySymbol`: enable CP multisection (one symbol per section); default value is 0
     *  DU delay profile (`T1a` and `Ta4`): pairs of numbers `(x, y)` specifying minimum and maximum delays
     * `ru_config`: RU-specific configuration:
       * `iq_width`: Width of DL/UL IQ samples: if 16, no compression, if <16, applies

radio/fhi_72/CMakeLists.txt

@@ -16,10 +16,10 @@ add_library(oran_fhlib_5g MODULE
             oran-init.c
 )
 
-set(F_VERSION 6.1.8)
+set(F_VERSION 6.1.9)
 
 find_package(xran REQUIRED)
-if(xran_VERSION MATCHES "5.*")
+if(xran_VERSION VERSION_GREATER_EQUAL 5 AND xran_VERSION VERSION_LESS 6)
   message(FATAL_ERROR "xran E release not supported starting from tag 2026.w08.\nPlease switch to F version ${F_VERSION}")
 elseif(xran_VERSION VERSION_EQUAL F_VERSION)
   target_compile_definitions(oran_fhlib_5g PRIVATE F_RELEASE)

radio/fhi_72/oran-config.c

@@ -432,12 +432,10 @@ void print_fh_config(const struct xran_fh_config *fh_config)
 #if defined F_RELEASE
   printf("\
   RunSlotPrbMapBySymbolEnable %d\n\
-  LiteOnIgnoreUPSectionIdEnable %d\n\
   dssEnable %d\n\
   dssPeriod %d\n\
   technology[XRAN_MAX_DSS_PERIODICITY] (not filled as DSS disabled)\n",
       fh_config->RunSlotPrbMapBySymbolEnable,
-      fh_config->LiteOnIgnoreUPSectionIdEnable,
       fh_config->dssEnable,
       fh_config->dssPeriod);
 #endif
@@ -777,8 +775,7 @@ static bool set_fh_prach_config(void *mplane_api,
                                 const uint32_t max_num_ant,
                                 const paramdef_t *prachp,
                                 int nprach,
-                                struct xran_prach_config *prach_config,
-                                bool liteon_prach_eAxC_offset)
+                                struct xran_prach_config *prach_config)
 {
   const split7_config_t *s7cfg = &oai0->split7;
 
@@ -814,11 +811,8 @@ static bool set_fh_prach_config(void *mplane_api,
   xran_mplane_t *xran_mplane = (xran_mplane_t *)mplane_api;
   prach_config->eAxC_offset = xran_mplane->prach_offset;
 #else
-  uint8_t offset = *gpd(prachp, nprach, ORAN_PRACH_CONFIG_EAXC_OFFSET)->u8ptr;
-  if (liteon_prach_eAxC_offset)
-    prach_config->eAxC_offset = offset;
-  else
-    prach_config->eAxC_offset = (offset != 0) ? offset : max_num_ant;
+  const paramdef_t *pd = gpd(prachp, nprach, ORAN_PRACH_CONFIG_EAXC_OFFSET);
+  prach_config->eAxC_offset = pd->paramflags & PARAMFLAG_PARAMSET ? *pd->u8ptr : max_num_ant;
 #endif
 
   g_kbar = *gpd(prachp, nprach, ORAN_PRACH_CONFIG_KBAR)->uptr;
@@ -964,13 +958,9 @@ static bool set_fh_config(void *mplane_api, int ru_idx, int num_rus, enum xran_c
   fh_config->prachEnable = 1; // enable PRACH
   fh_config->srsEnable = 0; // enable SRS; used only if XRAN_CATEGORY_B
   // For LiteOn E release, no need to take care of prach eAxC_offset. xran lib is hacked to handle it.
-  bool liteon_prach_eAxC_offset = false;
 #if defined F_RELEASE
   fh_config->srsEnableCp = 0; // enable SRS CP; used only if XRAN_CATEGORY_B
   fh_config->SrsDelaySym = 0; // number of SRS delay symbols; used only if XRAN_CATEGORY_B
-  fh_config->RunSlotPrbMapBySymbolEnable    = *gpd(fhp, nfh, ORAN_CONFIG_RunSlotPrbMapBySymbol)->uptr;    // enable RunSlotPrbMapBySymbol
-  fh_config->LiteOnIgnoreUPSectionIdEnable  = *gpd(fhp, nfh, ORAN_CONFIG_LiteOnIgnoreUPSectionId)->uptr;  // enable LiteOnIgnoreUPSectionId
-  liteon_prach_eAxC_offset = fh_config->LiteOnIgnoreUPSectionIdEnable;
 #endif
   fh_config->puschMaskEnable = 0; // enable PUSCH mask; only used if id = O_RU
   fh_config->puschMaskSlot = 0; // specific which slot PUSCH channel masked; only used if id = O_RU
@@ -982,7 +972,7 @@ static bool set_fh_config(void *mplane_api, int ru_idx, int num_rus, enum xran_c
   fh_config->GPS_Alpha = 0; // refers to alpha as defined in section 9.7.2 of ORAN spec. this value should be alpha*(1/1.2288ns), range 0 - 1e7 (ns); offset_nsec = (pConf->GPS_Beta - offset_sec * 100) * 1e7 + pConf->GPS_Alpha
   fh_config->GPS_Beta = 0; // beta value as defined in section 9.7.2 of ORAN spec. range -32767 ~ +32767; offset_sec = pConf->GPS_Beta / 100
 
-  if (!set_fh_prach_config(mplane_api, oai0, fh_config->neAxc, prachp, nprach, &fh_config->prach_conf, liteon_prach_eAxC_offset))
+  if (!set_fh_prach_config(mplane_api, oai0, fh_config->neAxc, prachp, nprach, &fh_config->prach_conf))
     return false;
   /* SRS only used if XRAN_CATEGORY_B
     Note: srs_config->eAxC_offset >= prach_config->eAxC_offset + PRACH */
@@ -1014,6 +1004,8 @@ static bool set_fh_config(void *mplane_api, int ru_idx, int num_rus, enum xran_c
   fh_config->max_sections_per_symbol = 0; // not used in xran
 
 #if defined F_RELEASE
+  fh_config->RunSlotPrbMapBySymbolEnable = *gpd(fhp, nfh, ORAN_CONFIG_CP_MULTISECTION)->uptr; // enable PRB mapping by symbol with multisection
+
   fh_config->dssEnable = 0; // enable DSS (extension-9)
   fh_config->dssPeriod = 0; // DSS pattern period for LTE/NR
   // fh_config->technology[XRAN_MAX_DSS_PERIODICITY] // technology array represents slot is LTE(0)/NR(1); used only if DSS enabled

radio/fhi_72/oran-init.c

@@ -315,16 +315,8 @@ static void oran_allocate_buffers(void *handle,
   };
 
 #if defined F_RELEASE
-  uint32_t size_of_prb_map;
-  if (fh_config->RunSlotPrbMapBySymbolEnable) {
-    // For Liteon FR2 with RunSlotPrbMapBySymbolEnable, xran_prb_map will have xran_prb_elm prbMap[14]
-    size_of_prb_map  = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (XRAN_NUM_OF_SYMBOL_PER_SLOT);
-  }
-  else {
-    // For non-Liteon w/o RunSlotPrbMapBySymbolEnable, xran_prb_map will have xran_prb_elm prbMap[1]
-    uint32_t numPrbElm = xran_get_num_prb_elm(&dlPm, mtu);
-    size_of_prb_map  = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (numPrbElm);
-  }
+  uint32_t numPrbElm = (fh_config->RunSlotPrbMapBySymbolEnable) ? XRAN_NUM_OF_SYMBOL_PER_SLOT : xran_get_num_prb_elm(&dlPm, mtu);
+  uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (numPrbElm);
 #endif
 
   // PDSCH

radio/fhi_72/oran-params.h

@@ -106,8 +106,7 @@
 
 #define CONFIG_STRING_ORAN_FH "fh_config"
 
-#define ORAN_CONFIG_RunSlotPrbMapBySymbol "RunSlotPrbMapBySymbol"
-#define ORAN_CONFIG_LiteOnIgnoreUPSectionId "LiteOnIgnoreUPSectionId"
+#define ORAN_CONFIG_CP_MULTISECTION "RunSlotPrbMapBySymbol"
 #define ORAN_FH_CONFIG_T1A_CP_DL "T1a_cp_dl"
 #define ORAN_FH_CONFIG_T1A_CP_UL "T1a_cp_ul"
 #define ORAN_FH_CONFIG_T1A_UP "T1a_up"
@@ -117,8 +116,7 @@
 
 // clang-format off
 #define ORAN_FH_DESC { \
-  {ORAN_CONFIG_RunSlotPrbMapBySymbol,   "RunSlotPrbMapBySymbol\n",     PARAMFLAG_BOOL,      .uptr=NULL, .defuintval=0,     TYPE_UINT,      0}, \
-  {ORAN_CONFIG_LiteOnIgnoreUPSectionId, "Liteon Ignore Section Id\n",  PARAMFLAG_BOOL,      .uptr=NULL, .defuintval=0,     TYPE_UINT,      0}, \
+  {ORAN_CONFIG_CP_MULTISECTION,         "RunSlotPrbMapBySymbol\n",     PARAMFLAG_BOOL,      .iptr=NULL, .defintval=0,      TYPE_INT32,     0}, \
   {ORAN_FH_CONFIG_T1A_CP_DL,            "T1a_cp_dl" ORAN_FH_HLP_CPLT,  PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
   {ORAN_FH_CONFIG_T1A_CP_UL,            "T1a_cp_ul" ORAN_FH_HLP_CPLT,  PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
   {ORAN_FH_CONFIG_T1A_UP,               "T1a_up" ORAN_FH_HLP_CPLT,     PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
@@ -145,7 +143,7 @@
 
 // clang-format off
 #define ORAN_PRACH_DESC {\
-  {ORAN_PRACH_CONFIG_EAXC_OFFSET, "RU's eAxC offset for PRACH\n", PARAMFLAG_MANDATORY, .u8ptr=NULL, .defuintval=0, TYPE_UINT8, 0}, \
+  {ORAN_PRACH_CONFIG_EAXC_OFFSET, "RU's eAxC offset for PRACH\n", 0,                   .u8ptr=NULL, .defuintval=0, TYPE_UINT8, 0}, \
   {ORAN_PRACH_CONFIG_KBAR,        "PRACH guard interval\n",       0,                   .uptr=NULL,  .defuintval=4, TYPE_UINT,  0}, \
 }
 // clang-format on

targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.66prb.fhi72.2x2-liteon.conf

+Active_gNBs = ( "inria-gnb");
+# Asn1_verbosity, choice in: none, info, annoying
+Asn1_verbosity = "none";
+
+gNBs =
+(
+ {
+    ////////// Identification parameters:
+    gNB_ID    =  0xe99;
+   cell_type =  "CELL_MACRO_GNB";
+
+    gNB_name  =  "inria-gnb";
+
+    // Tracking area code, 0x0000 and 0xfffe are reserved values
+    tracking_area_code  =  1;
+    plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ( { sst = 1; }); });
+
+    nr_cellid = 1;
+
+    ////////// Physical parameters:
+
+    pdsch_AntennaPorts_XP = 2;
+    pusch_AntennaPorts    = 2;
+    maxMIMO_layers        = 2;
+    do_CSIRS              = 1;
+    do_SRS                = 0;
+    min_rxtxtime          = 4;
+
+    servingCellConfigCommon = (
+    {
+ #spCellConfigCommon
+
+      physCellId                                                    = 0;
+
+#  downlinkConfigCommon
+    #frequencyInfoDL
+      # center frequency = 28701.12 MHz
+      # selected SSB frequency = 28691.04 MHz
+      absoluteFrequencySSB                                          = 2090683;
+      dl_frequencyBand                                              = 257;
+      # frequency point A = 28653.6 MHz
+      dl_absoluteFrequencyPointA                                    = 2090059;
+      #scs-SpecificCarrierList
+        dl_offstToCarrier                                           = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+        dl_subcarrierSpacing                                        = 3;
+        dl_carrierBandwidth                                         = 66;
+     #initialDownlinkBWP
+      #genericParameters
+       initialDLBWPlocationAndBandwidth                             = 17875;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+        initialDLBWPsubcarrierSpacing                               = 3;
+      #pdcch-ConfigCommon
+        initialDLBWPcontrolResourceSetZero                          = 2;
+        initialDLBWPsearchSpaceZero                                 = 0;
+
+  #uplinkConfigCommon
+     #frequencyInfoUL
+      ul_frequencyBand                                              = 257;
+      #scs-SpecificCarrierList
+      ul_offstToCarrier                                             = 0;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+      ul_subcarrierSpacing                                          = 3;
+      ul_carrierBandwidth                                           = 66;
+      pMax                                                          = 20;
+     #initialUplinkBWP
+      #genericParameters
+        initialULBWPlocationAndBandwidth                            = 17875;
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+        initialULBWPsubcarrierSpacing                               = 3;
+      #rach-ConfigCommon
+        #rach-ConfigGeneric
+          prach_ConfigurationIndex                                  = 135;
+#prach_msg1_FDM
+#0 = one, 1=two, 2=four, 3=eight
+          prach_msg1_FDM                                            = 0;
+          prach_msg1_FrequencyStart                                 = 0;
+          zeroCorrelationZoneConfig                                 = 15;
+          preambleReceivedTargetPower                               = -118;
+#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
+          preambleTransMax                                          = 8;
+#powerRampingStep
+# 0=dB0,1=dB2,2=dB4,3=dB6
+        powerRampingStep                                            = 2;
+#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
+#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
+        ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR                = 3;
+#one (0..15) 4,8,12,16,...60,64
+        ssb_perRACH_OccasionAndCB_PreamblesPerSSB                   = 15;
+#ra_ContentionResolutionTimer
+#(0..7) 8,16,24,32,40,48,56,64
+        ra_ContentionResolutionTimer                                = 7;
+        rsrp_ThresholdSSB                                           = 19;
+#prach-RootSequenceIndex_PR
+#1 = 839, 2 = 139
+        prach_RootSequenceIndex_PR                                  = 2;
+        prach_RootSequenceIndex                                     = 1;
+        # SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
+        #
+        msg1_SubcarrierSpacing                                      = 3,
+# restrictedSetConfig
+# 0=unrestricted, 1=restricted type A, 2=restricted type B
+        restrictedSetConfig                                         = 0,
+
+# this is the offset between the last PRACH preamble power and the Msg3 PUSCH, 2 times the field value in dB
+        msg3_DeltaPreamble                                          = 0;
+        p0_NominalWithGrant                                         = -90;
+
+# pucch-ConfigCommon setup :
+# pucchGroupHopping
+# 0 = neither, 1= group hopping, 2=sequence hopping
+        pucchGroupHopping                                           = 0;
+        hoppingId                                                   = 40;
+        p0_nominal                                                  = -90;
+
+      ssb_PositionsInBurst_Bitmap                                   = 1;
+
+# ssb_periodicityServingCell
+# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
+      ssb_periodicityServingCell                                    = 1;
+
+# dmrs_TypeA_position
+# 0 = pos2, 1 = pos3
+      dmrs_TypeA_Position                                           = 0;
+
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+      subcarrierSpacing                                             = 3;
+
+
+  #tdd-UL-DL-ConfigurationCommon
+# subcarrierSpacing
+# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
+      referenceSubcarrierSpacing                                    = 3;
+      # pattern1
+      # dl_UL_TransmissionPeriodicity
+      # 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
+      dl_UL_TransmissionPeriodicity                                 = 3;
+      nrofDownlinkSlots                                             = 7;
+      nrofDownlinkSymbols                                           = 6;
+      nrofUplinkSlots                                               = 2;
+      nrofUplinkSymbols                                             = 4;
+
+  ssPBCH_BlockPower                                                 = 0;
+  }
+  );
+
+
+    # ------- SCTP definitions
+    SCTP :
+    {
+        # Number of streams to use in input/output
+        SCTP_INSTREAMS  = 2;
+        SCTP_OUTSTREAMS = 2;
+    };
+
+
+    ////////// AMF parameters:
+    amf_ip_address = ({ ipv4 = "172.21.6.4"; });
+
+    NETWORK_INTERFACES :
+    {
+        GNB_IPV4_ADDRESS_FOR_NG_AMF              = "172.21.16.51";
+        GNB_IPV4_ADDRESS_FOR_NGU                 = "172.21.16.51";
+        GNB_PORT_FOR_S1U                         = 2152; # Spec 2152
+    };
+  }
+);
+
+MACRLCs = (
+{
+  num_cc                      = 1;
+  tr_s_preference             = "local_L1";
+  tr_n_preference             = "local_RRC";
+  pusch_TargetSNRx10          = 200;
+  pucch_TargetSNRx10          = 200;
+  pusch_FailureThres          = 1000;
+  #ul_bler_target_upper        =.02;
+  #ul_bler_target_lower        =.01;
+  #dl_bler_target_upper        =.15;
+  #dl_bler_target_lower        =.05
+  set_analog_beamforming      = "lophy";
+  beam_duration               = 1;
+  beams_per_period            = 1;
+  beam_weights = [1];
+}
+);
+
+L1s = (
+{
+  num_cc = 1;
+  tr_n_preference = "local_mac";
+  prach_dtx_threshold = 250;
+  pucch0_dtx_threshold = 100;
+  pusch_dtx_threshold = -200;
+  max_ldpc_iterations = 10;
+  tx_amp_backoff_dB = 18;
+  L1_rx_thread_core = 10;
+  L1_tx_thread_core = 11;
+  phase_compensation = 1;
+
+}
+);
+
+RUs = (
+{
+  local_rf       = "no";
+  nb_tx          = 2;
+  nb_rx          = 2;
+  att_tx         = 0
+  att_rx         = 0;
+  bands          = [257];
+  nr_scs_for_raster = 3;
+  max_pdschReferenceSignalPower = -40;
+  max_rxgain                    = 60;
+  #sf_extension                  = 0;
+  eNB_instances  = [0];
+  ru_thread_core = 9;
+  sl_ahead       = 10;
+  tr_preference  = "raw_if4p5";
+  do_precoding = 0;
+}
+);
+
+security = {
+  # preferred ciphering algorithms
+  # the first one of the list that an UE supports in chosen
+  # valid values: nea0, nea1, nea2, nea3
+  ciphering_algorithms = ( "nea0" );
+
+  # preferred integrity algorithms
+  # the first one of the list that an UE supports in chosen
+  # valid values: nia0, nia1, nia2, nia3
+  integrity_algorithms = ( "nia2", "nia0" );
+
+  # setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
+  # what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
+  drb_ciphering = "yes";
+  drb_integrity = "no";
+};
+
+log_config :
+{
+  global_log_level = "info";
+  hw_log_level     = "info";
+  phy_log_level    = "info";
+  mac_log_level    = "info";
+  rlc_log_level    = "info";
+  pdcp_log_level   = "info";
+  rrc_log_level    = "info";
+  ngap_log_level   = "info";
+  f1ap_log_level   = "info";
+};
+
+fhi_72 = {
+  dpdk_devices = ("0000:c1:11.0", "0000:c1:11.1"); # one VF can be used as well
+  system_core = 6;
+  io_core = 7;
+  worker_cores = (8);
+  ru_addr = ("E8:C7:4F:1E:C7:5B", "E8:C7:4F:1E:C7:5B");
+  mtu = 9216;
+  fh_config = ({
+    RunSlotPrbMapBySymbol = 1;
+    T1a_cp_dl = (110, 111);
+    T1a_cp_ul = (69, 70);
+    T1a_up = (30, 64);
+    Ta4 = (30, 64);
+    ru_config = {
+      iq_width = 8;
+      iq_width_prach = 8;
+    };
+    prach_config = {
+      eAxC_offset = 0;
+      kbar = 0;
+    };
+  });
+};