From 60d553f13fdf9e306ea335330aa0f9b09743667d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niccol=C3=B2=20Iardella?= <niccolo.iardella@unifi.it> Date: Thu, 22 Mar 2018 14:17:07 +0100 Subject: [PATCH] Inter/intra-slice sharing are now optional --- openair2/COMMON/platform_types.h | 5 +++ openair2/LAYER2/MAC/defs.h | 5 +++ openair2/LAYER2/MAC/eNB_scheduler_dlsch.c | 32 ++++++++++++- openair2/LAYER2/MAC/eNB_scheduler_dlsch.h | 5 +++ openair2/LAYER2/MAC/pre_processor.c | 55 ++++++++++++----------- 5 files changed, 74 insertions(+), 28 deletions(-) diff --git a/openair2/COMMON/platform_types.h b/openair2/COMMON/platform_types.h index 366dc0a22f..30b458c4c4 100644 --- a/openair2/COMMON/platform_types.h +++ b/openair2/COMMON/platform_types.h @@ -110,6 +110,11 @@ typedef enum { CR_NUM = 6 } sorting_criterion_t; +typedef enum { + POL_FAIR = 0, + POL_GREEDY = 1, + POL_NUM = 2 +} accounting_policy_t; //----------------------------------------------------------------------------- // PHY TYPES //----------------------------------------------------------------------------- diff --git a/openair2/LAYER2/MAC/defs.h b/openair2/LAYER2/MAC/defs.h index b7cb9238ed..8d3ad9a5ce 100644 --- a/openair2/LAYER2/MAC/defs.h +++ b/openair2/LAYER2/MAC/defs.h @@ -1368,6 +1368,11 @@ typedef struct { uint8_t slice_allocation_mask[MAX_NUM_CCs][N_RBG_MAX]; uint8_t slice_allocated_rbgs[MAX_NUM_CCs][N_RBG_MAX]; uint8_t MIMO_mode_indicator[MAX_NUM_CCs][N_RBG_MAX]; + + uint32_t bytes_lcid[NUMBER_OF_UE_MAX][MAX_NUM_LCID]; + uint32_t wb_pmi[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; + uint8_t mcs[MAX_NUM_CCs][NUMBER_OF_UE_MAX]; + } pre_processor_results_t; #include "proto.h" diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c index 071386e08d..210642ca24 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.c @@ -436,6 +436,34 @@ schedule_dlsch(module_id_t module_idP, frame_t frameP, sub_frame_t subframeP, in slice_percentage_total += slice_percentage[i]; } + // Check for *intra*slice share activation + if (intraslice_share_active_current != intraslice_share_active) { + if (intraslice_share_active != 1 && intraslice_share_active != 0) { + LOG_W(MAC, + "[eNB %d][DL] frame %d subframe %d: invalid intraslice sharing status (%d), revert to its previous value (%d)\n", + module_idP, i, frameP, subframeP, intraslice_share_active, intraslice_share_active_current); + intraslice_share_active = intraslice_share_active_current; + } else { + LOG_N(MAC, "[eNB %d][DL] frame %d subframe %d: intraslice sharing status has changed (%x-->%x)\n", + module_idP, i, frameP, subframeP, intraslice_share_active_current, intraslice_share_active); + intraslice_share_active_current = intraslice_share_active; + } + } + + // Check for *inter*slice share activation + if (interslice_share_active_current != interslice_share_active) { + if (interslice_share_active != 1 && interslice_share_active != 0) { + LOG_W(MAC, + "[eNB %d][DL] frame %d subframe %d: invalid interslice sharing status (%d), revert to its previous value (%d)\n", + module_idP, i, frameP, subframeP, interslice_share_active, interslice_share_active_current); + interslice_share_active = interslice_share_active_current; + } else { + LOG_N(MAC, "[eNB %d][DL] frame %d subframe %d: interslice sharing status has changed (%x-->%x)\n", + module_idP, i, frameP, subframeP, interslice_share_active_current, interslice_share_active); + interslice_share_active_current = interslice_share_active; + } + } + for (i = 0; i < n_active_slices; i++) { // Load any updated functions @@ -722,7 +750,9 @@ schedule_ue_spec(module_id_t module_idP, slice_id_t slice_idP, return; } - dlsch_scheduler_interslice_multiplexing(module_idP, frameP, subframeP); + if (interslice_share_active) { + dlsch_scheduler_interslice_multiplexing(module_idP, frameP, subframeP); + } for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { LOG_D(MAC, "doing schedule_ue_spec for CC_id %d\n", CC_id); diff --git a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.h b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.h index 321f83c20d..e2aac32bf0 100644 --- a/openair2/LAYER2/MAC/eNB_scheduler_dlsch.h +++ b/openair2/LAYER2/MAC/eNB_scheduler_dlsch.h @@ -42,6 +42,11 @@ int n_active_slices = 1; int n_active_slices_current = 1; int slice_counter = 0; +int intraslice_share_active = 1; +int intraslice_share_active_current = 1; +int interslice_share_active = 1; +int interslice_share_active_current = 1; + // RB share for each slice for past and current time float slice_percentage[MAX_NUM_SLICES] = {1.0, 0.0, 0.0, 0.0}; float slice_percentage_current[MAX_NUM_SLICES] = {1.0, 0.0, 0.0, 0.0}; diff --git a/openair2/LAYER2/MAC/pre_processor.c b/openair2/LAYER2/MAC/pre_processor.c index cfc8f4b750..53dbd621eb 100644 --- a/openair2/LAYER2/MAC/pre_processor.c +++ b/openair2/LAYER2/MAC/pre_processor.c @@ -66,6 +66,8 @@ extern int slice_maxmcs[MAX_NUM_SLICES]; extern int slice_maxmcs_uplink[MAX_NUM_SLICES]; extern pre_processor_results_t pre_processor_results[MAX_NUM_SLICES]; +extern int intraslice_share_active; + //#define ICIC 0 /* this function checks that get_eNB_UE_stats returns @@ -162,6 +164,7 @@ store_dlsch_buffer(module_id_t Mod_id, #endif + } if (UE_template->dl_buffer_total > 0) @@ -202,7 +205,8 @@ assign_rbs_required(module_id_t Mod_id, CC_id = UE_list->ordered_CCids[n][UE_id]; eNB_UE_stats = &UE_list->eNB_UE_stats[CC_id][UE_id]; - eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], slice_maxmcs[slice_id]); +// eNB_UE_stats->dlsch_mcs1 = cmin(cqi_to_mcs[UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]], slice_maxmcs[slice_id]); + eNB_UE_stats->dlsch_mcs1 = cmin(cqi2mcs(UE_list->UE_sched_ctrl[UE_id].dl_cqi[CC_id]), slice_maxmcs[slice_id]); } @@ -264,6 +268,8 @@ assign_rbs_required(module_id_t Mod_id, Mod_id, frameP, UE_id, CC_id, min_rb_unit[CC_id], nb_rbs_required[CC_id][UE_id], TBS, eNB_UE_stats->dlsch_mcs1); + + pre_processor_results[slice_id].mcs[CC_id][UE_id] = eNB_UE_stats->dlsch_mcs1; } } } @@ -679,7 +685,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, CC_id = UE_list->ordered_CCids[i][UE_id]; ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; cc = &RC.mac[Mod_id]->common_channels[CC_id]; - // TODO Can we use subframe2harqpid() here? + // FIXME: Can we use subframe2harqpid() here? if (cc->tdd_Config) harq_pid = ((frameP * 10) + subframeP) % 10; else @@ -708,7 +714,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, switch (slice_accounting[slice_id]) { // If greedy scheduling, try to account all the required RBs - case 1: + case POL_GREEDY: for (UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) { rnti = UE_RNTI(Mod_id, UE_id); if (rnti == NOT_A_RNTI) continue; @@ -724,6 +730,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, // Use the old, fair algorithm // Loop over all active UEs and account the avg number of RBs to each UE, based on all non-retx UEs. + // case POL_FAIR: default: // FIXME: This is not ideal, why loop on UEs to find average_rbs_per_user[], that is per-CC? // TODO: Look how to loop on active CCs only without using the UE_num_active_CC() function. @@ -782,7 +789,7 @@ void dlsch_scheduler_pre_processor_accounting(module_id_t Mod_id, CC_id = UE_list->ordered_CCids[i][UE_id]; ue_sched_ctl = &UE_list->UE_sched_ctrl[UE_id]; cc = &RC.mac[Mod_id]->common_channels[CC_id]; - // TODO Can we use subframe2harqpid() here? + // FIXME: Can we use subframe2harqpid() here? if (cc->tdd_Config) harq_pid = ((frameP * 10) + subframeP) % 10; else @@ -1278,13 +1285,15 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, #endif // Initialize scheduling information for all active UEs + memset(&pre_processor_results[slice_id], 0, sizeof(pre_processor_results)); + // FIXME: After the memset above, some of the resets in reset() are redundant dlsch_scheduler_pre_processor_reset(Mod_id, slice_id, frameP, subframeP, N_RBG, min_rb_unit, nb_rbs_required, rballoc_sub, MIMO_mode_indicator, - mbsfn_flag); // TODO Not sure if useful + mbsfn_flag); // FIXME: Not sure if useful // STATUS // Store the DLSCH buffer for each logical channel @@ -1317,14 +1326,16 @@ dlsch_scheduler_pre_processor(module_id_t Mod_id, // SHARING // If there are available RBs left in the slice, allocate them to the highest priority UEs - dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_id, - N_RBG, - min_rb_unit, - nb_rbs_required, - nb_rbs_accounted, - nb_rbs_remaining, - rballoc_sub, - MIMO_mode_indicator); + if (intraslice_share_active) { + dlsch_scheduler_pre_processor_intraslice_sharing(Mod_id, slice_id, + N_RBG, + min_rb_unit, + nb_rbs_required, + nb_rbs_accounted, + nb_rbs_remaining, + rballoc_sub, + MIMO_mode_indicator); + } #ifdef TM5 // This has to be revisited!!!! @@ -1872,20 +1883,6 @@ ulsch_scheduler_pre_processor(module_id_t module_idP, } } } - -#if 0 - /* this logging is wrong, ue_sched_ctl may not be valid here - * TODO: fix - */ - for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++) { - - if (total_allocated_rbs[CC_id] > 0) { - LOG_D(MAC, "[eNB %d] total RB allocated for all UEs = %d/%d\n", - module_idP, total_allocated_rbs[CC_id], - ue_sched_ctl->max_rbs_allowed_slice_uplink[CC_id][slice_id] - first_rb[CC_id]); - } - } -#endif } @@ -2203,3 +2200,7 @@ void sort_ue_ul(module_id_t module_idP, int frameP, sub_frame_t subframeP) } #endif } + +int cqi2mcs(int cqi) { + return cqi_to_mcs[cqi]; +} -- 2.26.2