Commit bf819df6 authored by Sakthivel Velumani's avatar Sakthivel Velumani

changed dci_pdu_rel15 struct to hold bitwidth for each dci field

parent b4d273d6
develop 1 128-ues 256_QAM_demod NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRUE_usedlschparallel NR_10MHz NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguration_FR2 NR_RRC_PDCP NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_ue_dlsch_dmrs_cdm PUSCH_TA_update RA_CI_test UE_DL_DCI_hotfix bch-fixes-bitmap benetel_5g_prach_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_phase_rotation benetel_phase_rotation_old bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-x2-SgNBAdditionRequest bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-test ci-ul-iperf-from-trf-container cleanup_softmodem_main constant_power develop-SA-RA develop-SnT develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop_stable dfts_alternatives dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel dongzhanyi-zte-develop dongzhanyi-zte-develop2 feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fembms-enb-ue finalize-oaicn-integration firas fix-ci-tun fix-itti-segv fix-softmodem-restart fix_NR_DLUL_PF fix_do_ra_data fix_pdsch_low_prb fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun flexran-apps flexran-repair-mme-mgmt fujitsu_lte_contribution fujitsu_lte_contribution-128 gnb-only-test harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable improve_nr_modulation improve_ue_stability integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 inter-RRU-final itti-enhancement ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim nasmesh_kernel_5.8 new-gtpu nfapi_nr_develop ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nrUE nrUE-hs nrUE-upper-layer nr_bsr nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_fdd_if_fix nr_prach_fr2 nr_ue_msg3 nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oairu oairu-dockerfile-support oc-docker-october-improvements openxg/develop ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert_memcpy rh-ci-add-ue-parallelization rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_oc rh_ci_py rh_ci_ra_fr2 rh_ci_rfsim_ra rh_ci_ue_parallel rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rrc-enb-phy-testmode s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz small-bugfixes-w40 small-config-change smallcleanup testing_2symb_pdcch testing_with_external_txdata ue-csi ue-fixes ue_beam_selection ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes wireshark-T-hack-ueid wireshark-log-scheduling-requests x2-endc-processing xiangwab xiangwan yihongzheng_srb zzs 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 benetel_phase_rotation
No related merge requests found
...@@ -517,11 +517,44 @@ int get_num_dmrs(uint16_t dmrs_mask ) { ...@@ -517,11 +517,44 @@ int get_num_dmrs(uint16_t dmrs_mask ) {
return(num_dmrs); return(num_dmrs);
} }
uint16_t nr_dci_size(nr_dci_format_t format, // Table 5.1.2.2.1-1 38.214
uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
AssertFatal(bwp_size<276,"BWP Size > 275\n");
if (bwp_size < 37) return (rbg_size_config ? 4 : 2);
if (bwp_size < 73) return (rbg_size_config ? 8 : 4);
if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
if (bwp_size < 276) return 16;
}
uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size);
}
uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {
uint8_t nbitsA, nbitsB, nbits = 0;
if (typeA != NULL) nbitsA = (typeA->choice.setup->maxLength[0]==0) ? 4 : 5;
if (typeB != NULL) nbitsB = (typeB->choice.setup->maxLength[0]==0) ? 5 : 6;
if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB;
return nbits;
}
uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
dci_pdu_rel15_t *dci_pdu,
nr_dci_format_t format,
nr_rnti_type_t rnti_type, nr_rnti_type_t rnti_type,
uint16_t N_RB) { uint16_t N_RB) {
NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup;
uint16_t size = 0; uint16_t size = 0;
int bwp_id = 1;
NR_BWP_Downlink_t *bwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[bwp_id-1];
switch(format) { switch(format) {
/*Only sizes for 0_0 and 1_0 are correct at the moment*/ /*Only sizes for 0_0 and 1_0 are correct at the moment*/
...@@ -529,7 +562,7 @@ uint16_t nr_dci_size(nr_dci_format_t format, ...@@ -529,7 +562,7 @@ uint16_t nr_dci_size(nr_dci_format_t format,
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20 /// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
size += 20; size += 20;
size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment -- hopping scenario to be updated
size += nr_dci_size(NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size size += nr_dci_size(secondaryCellGroup,dci_pdu,NR_DL_DCI_FORMAT_1_0, rnti_type, N_RB) - size; // Padding to match 1_0 size
// UL/SUL indicator assumed to be 0 // UL/SUL indicator assumed to be 0
break; break;
...@@ -562,29 +595,123 @@ uint16_t nr_dci_size(nr_dci_format_t format, ...@@ -562,29 +595,123 @@ uint16_t nr_dci_size(nr_dci_format_t format,
break; break;
case NR_DL_DCI_FORMAT_1_1: case NR_DL_DCI_FORMAT_1_1:
// Format identifier
dci_pdu->format_indicator.nbits=1;
size = dci_pdu->format_indicator.nbits;
// Carrier indicator // Carrier indicator
size += 1; // Format identifier if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) {
dci_pdu->carrier_indicator.nbits=3;
size += dci_pdu->carrier_indicator.nbits;
}
// BWP Indicator // BWP Indicator
uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count;
dci_pdu->bwp_indicator.nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp)));
size += dci_pdu->bwp_indicator.nbits;
// Freq domain assignment // Freq domain assignment
long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size;
uint16_t numRBG = getNRBG(NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
NRRIV2PRBOFFSET(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
rbg_size_config);
if (pdsch_config->resourceAllocation == 0)
dci_pdu->frequency_domain_assignment.nbits = numRBG;
else if (pdsch_config->resourceAllocation == 1)
dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
else
dci_pdu->frequency_domain_assignment.nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
size += dci_pdu->frequency_domain_assignment.nbits;
// Time domain assignment // Time domain assignment
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
int num_entries;
if (pdsch_timeDomList != NULL)
num_entries = pdsch_timeDomList->list.count;
else
num_entries = 16; // num of entries in default table
dci_pdu->time_domain_assignment.nbits = (int)ceil(log2(num_entries));
size += dci_pdu->time_domain_assignment.nbits;
// VRB to PRB mapping // VRB to PRB mapping
if (pdsch_config->resourceAllocation == 1) {
dci_pdu->vrb_to_prb_mapping.nbits = 1;
size += dci_pdu->vrb_to_prb_mapping.nbits;
}
// PRB bundling size indicator // PRB bundling size indicator
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) {
dci_pdu->prb_bundling_size_indicator.nbits = 1;
size += dci_pdu->prb_bundling_size_indicator.nbits;
}
// Rate matching indicator // Rate matching indicator
NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1;
NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2;
if ((group1 != NULL) && (group2 != NULL))
dci_pdu->rate_matching_indicator.nbits = 2;
if ((group1 != NULL) != (group2 != NULL))
dci_pdu->rate_matching_indicator.nbits = 1;
size += dci_pdu->rate_matching_indicator.nbits;
// ZP CSI-RS trigger // ZP CSI-RS trigger
/// TB1- MCS 5, NDI 1, RV 2 uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count;
size += 8; dci_pdu->zp_csi_rs_trigger.nbits = (int)ceil(log2(nZP+1));
size += dci_pdu->zp_csi_rs_trigger.nbits;
// TB1- MCS 5, NDI 1, RV 2
dci_pdu->mcs[0].nbits = 5;
dci_pdu->ndi[0].nbits = 1;
dci_pdu->rv[0].nbits = 2;
size += (dci_pdu->mcs[0].nbits + dci_pdu->ndi[0].nbits + dci_pdu->rv[0].nbits);
// TB2 // TB2
size += 4 ; // HARQ PID long *maxCWperDCI = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
if ((maxCWperDCI != NULL) && (maxCWperDCI == 2)) {
dci_pdu->mcs[1].nbits = 5;
dci_pdu->ndi[1].nbits = 1;
dci_pdu->rv[1].nbits = 2;
size += (dci_pdu->mcs[1].nbits + dci_pdu->ndi[1].nbits + dci_pdu->rv[1].nbits);
}
// HARQ PID
dci_pdu->harq_pid.nbits = 4;
size += dci_pdu->harq_pid.nbits;
// DAI // DAI
size += 2; // TPC PUCCH if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells
size += 3; // PUCCH resource indicator dci_pdu->dai.nbits = 4;
size += 3; // PDSCH to HARQ timing indicator size += dci_pdu->dai.nbits;
}
// TPC PUCCH
dci_pdu->tpc.nbits = 2;
size += dci_pdu->tpc.nbits;
// PUCCH resource indicator
dci_pdu->pucch_resource_indicator.nbits = 3;
size += dci_pdu->pucch_resource_indicator.nbits;
// PDSCH to HARQ timing indicator
uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count;
dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits = (int)ceil(log2(I));
size += dci_pdu->pdsch_to_harq_feedback_timing_indicator.nbits;
// Antenna ports // Antenna ports
NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA;
NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB;
dci_pdu->antenna_ports.nbits = getAntPortBitWidth(typeA,typeB);
size += dci_pdu->antenna_ports.nbits;
// Tx Config Indication // Tx Config Indication
size += 2; // SRS request long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI;
if (isTciEnable != NULL) {
dci_pdu->transmission_configuration_indication.nbits = 3;
size += dci_pdu->transmission_configuration_indication.nbits;
}
// SRS request
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL)
dci_pdu->srs_request.nbits = 2;
else
dci_pdu->srs_request.nbits = 3;
size += dci_pdu->srs_request.nbits;
// CBGTI // CBGTI
uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2;
long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI;
uint8_t maxCW = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc;
dci_pdu->cbgti.nbits = maxCBGperTB * maxCW;
size += dci_pdu->cbgti.nbits;
// CBGFI // CBGFI
size += 1; // DMRS sequence init if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->pdsch_ServingCellConfig->choice.setup->codeBlockGroupTransmission->choice.setup->codeBlockGroupFlushIndicator) {
dci_pdu->cbgfi.nbits = 1;
size += dci_pdu->cbgfi.nbits;
}
// DMRS sequence init
dci_pdu->dmrs_sequence_initialization.nbits = 1;
size += dci_pdu->dmrs_sequence_initialization.nbits;
break; break;
case NR_DL_DCI_FORMAT_2_0: case NR_DL_DCI_FORMAT_2_0:
......
...@@ -336,37 +336,37 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -336,37 +336,37 @@ int configure_fapi_dl_pdu(int Mod_idP,
scc->dmrs_TypeA_Position, scc->dmrs_TypeA_Position,
pdsch_pdu_rel15->NrOfSymbols); pdsch_pdu_rel15->NrOfSymbols);
dci_pdu_rel15_t dci_pdu_rel15[MAX_DCI_CORESET]; dci_pdu_rel15_t *dci_pdu_rel15 = calloc(MAX_DCI_CORESET,sizeof(dci_pdu_rel15));
dci_pdu_rel15[0].frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize, dci_pdu_rel15[0].frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pdsch_pdu_rel15->rbSize,
pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbStart,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275)); NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15[0].time_domain_assignment = time_domain_assignment; // row index used here instead of SLIV; dci_pdu_rel15[0].time_domain_assignment.val = time_domain_assignment; // row index used here instead of SLIV;
dci_pdu_rel15[0].vrb_to_prb_mapping = 1; dci_pdu_rel15[0].vrb_to_prb_mapping.val = 1;
dci_pdu_rel15[0].mcs = pdsch_pdu_rel15->mcsIndex[0]; dci_pdu_rel15[0].mcs[0].val = pdsch_pdu_rel15->mcsIndex[0];
dci_pdu_rel15[0].tb_scaling = 1; dci_pdu_rel15[0].tb_scaling.val = 1;
dci_pdu_rel15[0].ra_preamble_index = 25; dci_pdu_rel15[0].ra_preamble_index.val = 25;
dci_pdu_rel15[0].format_indicator = 1; dci_pdu_rel15[0].format_indicator.val = 1;
dci_pdu_rel15[0].ndi = 1; dci_pdu_rel15[0].ndi[0].val = 1;
dci_pdu_rel15[0].rv = 0; dci_pdu_rel15[0].rv[0].val = 0;
dci_pdu_rel15[0].harq_pid = 0; dci_pdu_rel15[0].harq_pid.val = 0;
dci_pdu_rel15[0].dai = 2; dci_pdu_rel15[0].dai.val = 2;
dci_pdu_rel15[0].tpc = 2; dci_pdu_rel15[0].tpc.val = 2;
dci_pdu_rel15[0].pucch_resource_indicator = 7; dci_pdu_rel15[0].pucch_resource_indicator.val = 7;
dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator = 7; dci_pdu_rel15[0].pdsch_to_harq_feedback_timing_indicator.val = 7;
LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n", LOG_D(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d (%d,%d,%d), time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d ndi %d rv %d\n",
dci_pdu_rel15[0].frequency_domain_assignment, dci_pdu_rel15[0].frequency_domain_assignment.val,
pdsch_pdu_rel15->rbStart, pdsch_pdu_rel15->rbStart,
pdsch_pdu_rel15->rbSize, pdsch_pdu_rel15->rbSize,
NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275), NRRIV2BW(bwp->bwp_Common->genericParameters.locationAndBandwidth,275),
dci_pdu_rel15[0].time_domain_assignment, dci_pdu_rel15[0].time_domain_assignment.val,
dci_pdu_rel15[0].vrb_to_prb_mapping, dci_pdu_rel15[0].vrb_to_prb_mapping.val,
dci_pdu_rel15[0].mcs, dci_pdu_rel15[0].mcs[0].val,
dci_pdu_rel15[0].tb_scaling, dci_pdu_rel15[0].tb_scaling.val,
dci_pdu_rel15[0].ndi, dci_pdu_rel15[0].ndi[0].val,
dci_pdu_rel15[0].rv); dci_pdu_rel15[0].rv[0].val);
nr_configure_pdcch(pdcch_pdu_rel15, nr_configure_pdcch(pdcch_pdu_rel15,
1, // ue-specific 1, // ue-specific
...@@ -386,8 +386,8 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -386,8 +386,8 @@ int configure_fapi_dl_pdu(int Mod_idP,
dci_formats[0] = NR_DL_DCI_FORMAT_1_0; dci_formats[0] = NR_DL_DCI_FORMAT_1_0;
rnti_types[0] = NR_RNTI_C; rnti_types[0] = NR_RNTI_C;
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(secondaryCellGroup,pdsch_pdu_rel15,pdcch_pdu_rel15,NULL,&dci_pdu_rel15[0],dci_formats,rnti_types); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \ LOG_D(MAC, "DCI params: rnti %d, rnti_type %d, dci_format %d\n \
coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n", coreset params: FreqDomainResource %llx, start_symbol %d n_symb %d\n",
...@@ -419,29 +419,29 @@ int configure_fapi_dl_pdu(int Mod_idP, ...@@ -419,29 +419,29 @@ int configure_fapi_dl_pdu(int Mod_idP,
void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) { void config_uldci(NR_BWP_Uplink_t *ubwp,nfapi_nr_pusch_pdu_t *pusch_pdu,nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15, int *dci_formats, int *rnti_types) {
dci_pdu_rel15->frequency_domain_assignment = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, dci_pdu_rel15->frequency_domain_assignment.val = PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size,
pusch_pdu->rb_start, pusch_pdu->rb_start,
NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275)); NRRIV2BW(ubwp->bwp_Common->genericParameters.locationAndBandwidth,275));
dci_pdu_rel15->time_domain_assignment = 2; // row index used here instead of SLIV; dci_pdu_rel15->time_domain_assignment.val = 2; // row index used here instead of SLIV;
dci_pdu_rel15->frequency_hopping_flag = 0; dci_pdu_rel15->frequency_hopping_flag.val = 0;
dci_pdu_rel15->mcs = 9; dci_pdu_rel15->mcs[0].val = 9;
dci_pdu_rel15->format_indicator = 0; dci_pdu_rel15->format_indicator.val = 0;
dci_pdu_rel15->ndi = 1; dci_pdu_rel15->ndi[0].val = 1;
dci_pdu_rel15->rv = 0; dci_pdu_rel15->rv[0].val = 0;
dci_pdu_rel15->harq_pid = 0; dci_pdu_rel15->harq_pid.val = 0;
dci_pdu_rel15->tpc = 2; dci_pdu_rel15->tpc.val = 2;
LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n", LOG_D(MAC, "[gNB scheduler phytest] ULDCI type 0 payload: PDCCH CCEIndex %d, freq_alloc %d, time_alloc %d, freq_hop_flag %d, mcs %d tpc %d ndi %d rv %d\n",
pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci], pdcch_pdu_rel15->CceIndex[pdcch_pdu_rel15->numDlDci],
dci_pdu_rel15->frequency_domain_assignment, dci_pdu_rel15->frequency_domain_assignment.val,
dci_pdu_rel15->time_domain_assignment, dci_pdu_rel15->time_domain_assignment.val,
dci_pdu_rel15->frequency_hopping_flag, dci_pdu_rel15->frequency_hopping_flag.val,
dci_pdu_rel15->mcs, dci_pdu_rel15->mcs[0].val,
dci_pdu_rel15->tpc, dci_pdu_rel15->tpc.val,
dci_pdu_rel15->ndi, dci_pdu_rel15->ndi[0].val,
dci_pdu_rel15->rv); dci_pdu_rel15->rv[0].val);
dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0; dci_formats[pdcch_pdu_rel15->numDlDci] = NR_UL_DCI_FORMAT_0_0;
rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C; rnti_types[pdcch_pdu_rel15->numDlDci] = NR_RNTI_C;
...@@ -832,8 +832,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP, ...@@ -832,8 +832,8 @@ void nr_schedule_uss_ulsch_phytest(int Mod_idP,
config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types); config_uldci(ubwp,pusch_pdu,pdcch_pdu_rel15, &dci_pdu_rel15[0], dci_formats, rnti_types);
pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize); pdcch_pdu_rel15->PayloadSizeBits[0]=nr_dci_size(secondaryCellGroup,&dci_pdu_rel15[0],dci_formats[0],rnti_types[0],pdcch_pdu_rel15->BWPSize);
fill_dci_pdu_rel15(secondaryCellGroup,NULL,pdcch_pdu_rel15,pusch_pdu,&dci_pdu_rel15[0],dci_formats,rnti_types); fill_dci_pdu_rel15(pdcch_pdu_rel15,&dci_pdu_rel15[0],dci_formats,rnti_types);
} }
...@@ -544,45 +544,12 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, ...@@ -544,45 +544,12 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
} }
} }
// TODO: Move the following 3 functions somewhere that UE can also use void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
// Table 5.1.2.2.1-1 38.214
uint8_t getRBGSize(uint16_t bwp_size, long rbg_size_config) {
AssertFatal(bwp_size<276,"BWP Size > 275\n");
if (bwp_size < 37) return (rbg_size_config ? 4 : 2);
if (bwp_size < 73) return (rbg_size_config ? 8 : 4);
if (bwp_size < 145) return (rbg_size_config ? 16 : 8);
if (bwp_size < 276) return 16;
}
uint8_t getNRBG(uint16_t bwp_size, uint16_t bwp_start, long rbg_size_config) {
uint8_t rbg_size = getRBGSize(bwp_size,rbg_size_config);
return (uint8_t)ceil((bwp_size+(bwp_start % rbg_size))/rbg_size);
}
uint8_t getAntPortBitWidth(NR_SetupRelease_DMRS_DownlinkConfig_t *typeA, NR_SetupRelease_DMRS_DownlinkConfig_t *typeB) {
uint8_t nbitsA, nbitsB, nbits = 0;
if (typeA != NULL) nbitsA = (typeA->choise.setup->maxLength[0]==0) ? 4 : 5;
if (typeB != NULL) nbitsB = (typeB->choise.setup->maxLength[0]==0) ? 5 : 6;
if ((typeA != NULL) && (typeB != NULL)) nbits = (nbitsA > nbitsB) ? nbitsA : nbitsB;
return nbits;
}
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
nfapi_nr_pusch_pdu_t *pusch_pdu,
dci_pdu_rel15_t *dci_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats, int *dci_formats,
int *rnti_types int *rnti_types
) { ) {
NR_PDSCH_Config_t *pdsch_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup;
uint16_t N_RB = pdcch_pdu_rel15->BWPSize; uint16_t N_RB = pdcch_pdu_rel15->BWPSize;
uint8_t fsize=0, pos=0; uint8_t fsize=0, pos=0;
uint8_t nbits=0; uint8_t nbits=0;
...@@ -603,44 +570,44 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -603,44 +570,44 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
// Freq domain assignment // Freq domain assignment
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos=fsize; pos=fsize;
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,N_RB,dci_size-pos,*dci_pdu); LOG_D(MAC,"frequency-domain assignment %d (%d bits) N_RB_BWP %d=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,N_RB,dci_size-pos,*dci_pdu);
// Time domain assignment // Time domain assignment
pos+=4; pos+=4;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,dci_size-pos,*dci_pdu); LOG_D(MAC,"time-domain assignment %d (3 bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,dci_size-pos,*dci_pdu);
// VRB to PRB mapping // VRB to PRB mapping
pos++; pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&0x1)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&0x1)<<(dci_size-pos);
LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,dci_size-pos,*dci_pdu); LOG_D(MAC,"vrb to prb mapping %d (1 bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,dci_size-pos,*dci_pdu);
// MCS // MCS
pos+=5; pos+=5;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos);
LOG_D(MAC,"mcs %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,dci_size-pos,*dci_pdu); LOG_D(MAC,"mcs[0] %d (5 bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,dci_size-pos,*dci_pdu);
// TB scaling // TB scaling
pos+=2; pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling&0x3)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->tb_scaling.val&0x3)<<(dci_size-pos);
LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling,dci_size-pos,*dci_pdu); LOG_D(MAC,"tb_scaling %d (2 bits)=> %d (0x%lx)\n",dci_pdu_rel15->tb_scaling.val,dci_size-pos,*dci_pdu);
break; break;
case NR_RNTI_C: case NR_RNTI_C:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
pos++; pos++;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos);
LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator,1,N_RB,dci_size-pos,*dci_pdu); LOG_D(MAC,"Format indicator %d (%d bits) N_RB_BWP %d => %d (0x%lx)\n",dci_pdu_rel15->format_indicator.val,1,N_RB,dci_size-pos,*dci_pdu);
// Freq domain assignment (275rb >> fsize = 16) // Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
pos+=fsize; pos+=fsize;
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<fsize)-1)) << (dci_size-pos)); *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<fsize)-1)) << (dci_size-pos));
LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment,fsize,dci_size-pos,*dci_pdu); LOG_D(MAC,"Freq domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->frequency_domain_assignment.val,fsize,dci_size-pos,*dci_pdu);
uint16_t is_ra = 1; uint16_t is_ra = 1;
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
if (!((dci_pdu_rel15->frequency_domain_assignment>>i)&1)) { if (!((dci_pdu_rel15->frequency_domain_assignment.val>>i)&1)) {
is_ra = 0; is_ra = 0;
break; break;
} }
...@@ -648,19 +615,19 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -648,19 +615,19 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
{ {
// ra_preamble_index 6 bits // ra_preamble_index 6 bits
pos+=6; pos+=6;
*dci_pdu |= ((dci_pdu_rel15->ra_preamble_index&0x3f)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->ra_preamble_index.val&0x3f)<<(dci_size-pos));
// UL/SUL indicator 1 bit // UL/SUL indicator 1 bit
pos++; pos++;
*dci_pdu |= (dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos);
// SS/PBCH index 6 bits // SS/PBCH index 6 bits
pos+=6; pos+=6;
*dci_pdu |= ((dci_pdu_rel15->ss_pbch_index&0x3f)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->ss_pbch_index.val&0x3f)<<(dci_size-pos));
// prach_mask_index 4 bits // prach_mask_index 4 bits
pos+=4; pos+=4;
*dci_pdu |= ((dci_pdu_rel15->prach_mask_index&0xf)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->prach_mask_index.val&0xf)<<(dci_size-pos));
} //end if } //end if
...@@ -669,53 +636,53 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -669,53 +636,53 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
// Time domain assignment 4bit // Time domain assignment 4bit
pos+=4; pos+=4;
*dci_pdu |= ((dci_pdu_rel15->time_domain_assignment&0xf) << (dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->time_domain_assignment.val&0xf) << (dci_size-pos));
LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment,4,dci_size-pos,*dci_pdu); LOG_D(MAC,"Time domain assignment %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->time_domain_assignment.val,4,dci_size-pos,*dci_pdu);
// VRB to PRB mapping 1bit // VRB to PRB mapping 1bit
pos++; pos++;
*dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos);
LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping,1,dci_size-pos,*dci_pdu); LOG_D(MAC,"VRB to PRB %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->vrb_to_prb_mapping.val,1,dci_size-pos,*dci_pdu);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
pos+=5; pos+=5;
*dci_pdu |= (dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->mcs[0].val&0x1f)<<(dci_size-pos);
LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs,5,dci_size-pos,*dci_pdu); LOG_D(MAC,"MCS %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->mcs[0].val,5,dci_size-pos,*dci_pdu);
// New data indicator 1bit // New data indicator 1bit
pos++; pos++;
*dci_pdu |= (dci_pdu_rel15->ndi&1)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos);
LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi,1,dci_size-pos,*dci_pdu); LOG_D(MAC,"NDI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->ndi[0].val,1,dci_size-pos,*dci_pdu);
// Redundancy version 2bit // Redundancy version 2bit
pos+=2; pos+=2;
*dci_pdu |= (dci_pdu_rel15->rv&0x3)<<(dci_size-pos); *dci_pdu |= (dci_pdu_rel15->rv[0].val&0x3)<<(dci_size-pos);
LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv,2,dci_size-pos,*dci_pdu); LOG_D(MAC,"RV %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->rv[0].val,2,dci_size-pos,*dci_pdu);
// HARQ process number 4bit // HARQ process number 4bit
pos+=4; pos+=4;
*dci_pdu |= ((dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->harq_pid.val&0xf)<<(dci_size-pos));
LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid,4,dci_size-pos,*dci_pdu); LOG_D(MAC,"HARQ_PID %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->harq_pid.val,4,dci_size-pos,*dci_pdu);
// Downlink assignment index 2bit // Downlink assignment index 2bit
pos+=2; pos+=2;
*dci_pdu |= ((dci_pdu_rel15->dai&3)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->dai.val&3)<<(dci_size-pos));
LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai,2,dci_size-pos,*dci_pdu); LOG_D(MAC,"DAI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->dai.val,2,dci_size-pos,*dci_pdu);
// TPC command for scheduled PUCCH 2bit // TPC command for scheduled PUCCH 2bit
pos+=2; pos+=2;
*dci_pdu |= ((dci_pdu_rel15->tpc&3)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->tpc.val&3)<<(dci_size-pos));
LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc,2,dci_size-pos,*dci_pdu); LOG_D(MAC,"TPC %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->tpc.val,2,dci_size-pos,*dci_pdu);
// PUCCH resource indicator 3bit // PUCCH resource indicator 3bit
pos+=3; pos+=3;
*dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->pucch_resource_indicator.val&0x7)<<(dci_size-pos));
LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator,3,dci_size-pos,*dci_pdu); LOG_D(MAC,"PUCCH RI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pucch_resource_indicator.val,3,dci_size-pos,*dci_pdu);
// PDSCH-to-HARQ_feedback timing indicator 3bit // PDSCH-to-HARQ_feedback timing indicator 3bit
pos+=3; pos+=3;
*dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&0x7)<<(dci_size-pos)); *dci_pdu |= ((dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&0x7)<<(dci_size-pos));
LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator,3,dci_size-pos,*dci_pdu); LOG_D(MAC,"PDSCH to HARQ TI %d (%d bits)=> %d (0x%lx)\n",dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val,3,dci_size-pos,*dci_pdu);
} //end else } //end else
break; break;
...@@ -724,26 +691,26 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -724,26 +691,26 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
// Short Messages Indicator – 2 bits // Short Messages Indicator – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages_indicator.val>>(1-i))&1)<<(dci_size-pos++);
// Short Messages – 8 bits // Short Messages – 8 bits
for (int i=0; i<8; i++) for (int i=0; i<8; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages>>(7-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->short_messages.val>>(7-i))&1)<<(dci_size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++);
// TB scaling 2 bit // TB scaling 2 bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tb_scaling.val>>(1-i))&1)<<(dci_size-pos++);
break; break;
...@@ -752,52 +719,52 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -752,52 +719,52 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++);
break; break;
case NR_RNTI_TC: case NR_RNTI_TC:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++);
// Freq domain assignment 0-16 bit // Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4 bit // Time domain assignment 4 bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// VRB to PRB mapping 1 bit // VRB to PRB mapping 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&1)<<(dci_size-pos++);
// MCS 5bit //bit over 32, so dci_pdu ++ // MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++);
// Downlink assignment index – 2 bits // Downlink assignment index – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->dai>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->dai.val>>(1-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUCCH – 2 bits // TPC command for scheduled PUCCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++);
// LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n", // LOG_D(MAC, "DCI PDU: [0]->0x%08llx \t [1]->0x%08llx \t [2]->0x%08llx \t [3]->0x%08llx\n",
...@@ -806,7 +773,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -806,7 +773,7 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
// PDSCH-to-HARQ_feedback timing indicator – 3 bits // PDSCH-to-HARQ_feedback timing indicator – 3 bits
for (int i=0; i<3; i++) for (int i=0; i<3; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val>>(2-i))&1)<<(dci_size-pos++);
break; break;
} }
...@@ -817,81 +784,81 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -817,81 +784,81 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
{ {
case NR_RNTI_C: case NR_RNTI_C:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor /* commented for now (RK): need to get this from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value) if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/ */
break; break;
case NFAPI_NR_RNTI_TC: case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit // indicating a DL DCI format 1bit
*dci_pdu |= (dci_pdu_rel15->format_indicator&1)<<(dci_size-pos++); *dci_pdu |= (dci_pdu_rel15->format_indicator.val&1)<<(dci_size-pos++);
// Freq domain assignment max 16 bit // Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++) for (int i=0; i<fsize; i++)
*dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<(dci_size-pos++); *dci_pdu |= ((dci_pdu_rel15->frequency_domain_assignment.val>>(fsize-i-1))&1)<<(dci_size-pos++);
// Time domain assignment 4bit // Time domain assignment 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->time_domain_assignment.val>>(3-i))&1)<<(dci_size-pos++);
// Frequency hopping flag – 1 bit // Frequency hopping flag – 1 bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_hopping_flag.val&1)<<(dci_size-pos++);
// MCS 5 bit // MCS 5 bit
for (int i=0; i<5; i++) for (int i=0; i<5; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs>>(4-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->mcs[0].val>>(4-i))&1)<<(dci_size-pos++);
// New data indicator 1bit // New data indicator 1bit
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&1)<<(dci_size-pos++);
// Redundancy version 2bit // Redundancy version 2bit
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->rv>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->rv[0].val>>(1-i))&1)<<(dci_size-pos++);
// HARQ process number 4bit // HARQ process number 4bit
for (int i=0; i<4; i++) for (int i=0; i<4; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid>>(3-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->harq_pid.val>>(3-i))&1)<<(dci_size-pos++);
// TPC command for scheduled PUSCH – 2 bits // TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++) for (int i=0; i<2; i++)
*dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc>>(1-i))&1)<<(dci_size-pos++); *dci_pdu |= (((uint64_t)dci_pdu_rel15->tpc.val>>(1-i))&1)<<(dci_size-pos++);
// Padding bits // Padding bits
for(int a = pos;a<32;a++) for(int a = pos;a<32;a++)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->padding&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->padding.val&1)<<(dci_size-pos++);
// UL/SUL indicator – 1 bit // UL/SUL indicator – 1 bit
/* /*
commented for now (RK): need to get this information from BWP descriptor commented for now (RK): need to get this information from BWP descriptor
if (cfg->pucch_config.pucch_GroupHopping.value) if (cfg->pucch_config.pucch_GroupHopping.value)
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator&1)<<(dci_size-pos++); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ul_sul_indicator.val&1)<<(dci_size-pos++);
*/ */
break; break;
...@@ -900,158 +867,110 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, ...@@ -900,158 +867,110 @@ void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup,
case NR_DL_DCI_FORMAT_1_1: case NR_DL_DCI_FORMAT_1_1:
// Indicating a DL DCI format 1bit // Indicating a DL DCI format 1bit
pos=1; pos=dci_pdu_rel15->format_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator&1)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->format_indicator.val&((1<<dci_pdu_rel15->format_indicator.nbits)-1))<<(dci_size-pos);
// Carrier indicator // Carrier indicator
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig != NULL) { pos+=dci_pdu_rel15->carrier_indicator.nbits;
pos+=3; *dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator.val&((1<<dci_pdu_rel15->carrier_indicator.nbits)-1))<<(dci_size-pos);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->carrier_indicator&0x7)<<(dci_size-pos);
}
// BWP indicator // BWP indicator
uint8_t n_dl_bwp = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.count; pos+=dci_pdu_rel15->bwp_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator.val&((1<<dci_pdu_rel15->bwp_indicator.nbits)-1))<<(dci_size-pos);
nbits = (uint8_t)((n_dl_bwp < 4) ? ceil(log2(n_dl_bwp+1)) : ceil(log2(n_dl_bwp)));
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->bwp_indicator&((1<<nbits)-1))<<(dci_size-pos);
// Frequency domain resource assignment // Frequency domain resource assignment
long rbg_size_config = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rbg_Size; pos+=dci_pdu_rel15->frequency_domain_assignment.nbits;
uint16_t numRBG = getNRBG(pdsch_pdu_rel15->BWPSize,pdsch_pdu_rel15->BWPStart,rbg_size_config); *dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment.val&((1<<dci_pdu_rel15->frequency_domain_assignment.nbits)-1)) << (dci_size-pos);
if (pdsch_config->resourceAllocation == 0)
nbits = numRBG;
else if (pdsch_config->resourceAllocation == 1)
nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
else
nbits = ((int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )>numRBG) ? (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) )+1 : numRBG+1;
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->frequency_domain_assignment&((1<<nbits)-1)) << (dci_size-pos);
// Time domain resource assignment // Time domain resource assignment
NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_timeDomList = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
int num_entries;
if (pdsch_timeDomList != NULL)
num_entries = pdsch_timeDomList->list.count;
else
num_entries = 16; // num of entries in default table
nbits = (int)ceil(log2(num_entries));
pos+=nbits; pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment&((1<<nbits)-1)) << (dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->time_domain_assignment.val&((1<<dci_pdu_rel15->time_domain_assignment.nbits)-1)) << (dci_size-pos);
// VRB-to-PRB mapping // VRB-to-PRB mapping
if (pdsch_config->resourceAllocation == 1) { pos+=dci_pdu_rel15->vrb_to_prb_mapping.nbits;
pos++; *dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping.val&((1<<dci_pdu_rel15->vrb_to_prb_mapping.nbits)-1))<<(dci_size-pos);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->vrb_to_prb_mapping&1)<<(dci_size-pos);
}
// PRB bundling size indicator // PRB bundling size indicator
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->prb_BundlingType.present == 2) { pos+=dci_pdu_rel15->prb_bundling_size_indicator.nbits;
pos++; *dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator.val&((1<<dci_pdu_rel15->prb_bundling_size_indicator.nbits)-1))<<(dci_size-pos);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->prb_bundling_size_indicator&1)<<(dci_size-pos);
}
// Rate matching indicator // Rate matching indicator
NR_RateMatchPatternGroup_t *group1 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup1; pos+=dci_pdu_rel15->rate_matching_indicator.nbits;
NR_RateMatchPatternGroup_t *group2 = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->rateMatchPatternGroup2; *dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator.val&((1<<dci_pdu_rel15->rate_matching_indicator.nbits)-1))<<(dci_size-pos);
nbits = 0;
if ((group1 != NULL) && (group2 != NULL))
nbits = 2;
if ((group1 != NULL) != (group2 != NULL))
nbits = 1;
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rate_matching_indicator&((1<<nbits)-1))<<(dci_size-pos);
// ZP CSI-RS trigger // ZP CSI-RS trigger
uint8_t nZP = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->aperiodic_ZP_CSI_RS_ResourceSetsToAddModList->list.count; pos+=dci_pdu_rel15->zp_csi_rs_trigger.nbits;
nbits = (int)ceil(log2(nZP+1)); *dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger.val&((1<<dci_pdu_rel15->zp_csi_rs_trigger.nbits)-1)) << (dci_size-pos);
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->zp_csi_rs_trigger&((1<<nbits)-1)) << (dci_size-pos); //TB1
// MCS 5bit
pos+=dci_pdu_rel15->mcs[0].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[0].val&((1<<dci_pdu_rel15->mcs[0].nbits)-1))<<(dci_size-pos);
// New data indicator 1bit
pos+=dci_pdu_rel15->ndi[0].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[0].val&((1<<dci_pdu_rel15->ndi[0].nbits)-1))<<(dci_size-pos);
// Redundancy version 2bit
pos+=dci_pdu_rel15->rv[0].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[0].val&((1<<dci_pdu_rel15->rv[0].nbits)-1))<<(dci_size-pos);
//TB2
// MCS 5bit // MCS 5bit
pos+=5; pos+=dci_pdu_rel15->mcs[1].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs&0x1f)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->mcs[1].val&((1<<dci_pdu_rel15->mcs[1].nbits)-1))<<(dci_size-pos);
// New data indicator 1bit // New data indicator 1bit
pos++; pos+=dci_pdu_rel15->ndi[1].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi&1)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->ndi[1].val&((1<<dci_pdu_rel15->ndi[1].nbits)-1))<<(dci_size-pos);
// Redundancy version 2bit // Redundancy version 2bit
pos+=2; pos+=dci_pdu_rel15->rv[1].nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->rv&0x3)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->rv[1].val&((1<<dci_pdu_rel15->rv[1].nbits)-1))<<(dci_size-pos);
// HARQ process number 4bit // HARQ process number 4bit
pos+=4; pos+=dci_pdu_rel15->harq_pid.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid&0xf)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->harq_pid.val&((1<<dci_pdu_rel15->harq_pid.nbits)-1))<<(dci_size-pos);
// Downlink assignment index // Downlink assignment index
if (secondaryCellGroup->physicalCellGroupConfig->pdsch_HARQ_ACK_Codebook == 1) { // at this point the UE has multiple serving cells pos+=dci_pdu_rel15->dai.nbits;
pos+=4; *dci_pdu |= ((uint64_t)dci_pdu_rel15->dai.val&((1<<dci_pdu_rel15->dai.nbits)-1))<<(dci_size-pos);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0xf)<<(dci_size-pos);
}
/* else if (0) {
pos+=2;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dai&0x3)<<(dci_size-pos);
}
*/
// TPC command for scheduled PUCCH 2bit // TPC command for scheduled PUCCH 2bit
pos+=2; pos+=dci_pdu_rel15->tpc.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc&0x3)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->tpc.val&((1<<dci_pdu_rel15->tpc.nbits)-1))<<(dci_size-pos);
// PUCCH resource indicator 3bit // PUCCH resource indicator 3bit
pos+=3; pos+=dci_pdu_rel15->pucch_resource_indicator.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator&0x7)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->pucch_resource_indicator.val&((1<<dci_pdu_rel15->pucch_resource_indicator.nbits)-1))<<(dci_size-pos);
// PDSCH-to-HARQ_feedback timing indicator // PDSCH-to-HARQ_feedback timing indicator
uint8_t I = secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pucch_Config->choice.setup->dl_DataToUL_ACK->list.count; pos+=dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits;
nbits = (int)ceil(log2(I)); *dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.val&((1<<dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator.nbits)-1))<<(dci_size-pos);
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->pdsch_to_harq_feedback_timing_indicator&((1<<nbits)-1))<<(dci_size-pos);
// Antenna ports // Antenna ports
NR_SetupRelease_DMRS_DownlinkConfig_t *typeA = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeA; pos+=dci_pdu_rel15->antenna_ports.nbits;
NR_SetupRelease_DMRS_DownlinkConfig_t *typeB = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->dmrs_DownlinkForPDSCH_MappingTypeB; *dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports.val&((1<<dci_pdu_rel15->antenna_ports.nbits)-1))<<(dci_size-pos);
nbits = getAntPortBitWidth(typeA,typeB);
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->antenna_ports&((1<<nbits)-1))<<(dci_size-pos);
// TCI // TCI
long *isTciEnable = secondaryCellGroup->spCellConfig->spCellConfigDedicated->downlinkBWP_ToAddModList->list.array[0]->bwp_Dedicated->pdcch_Config->choice.setup->controlResourceSetToAddModList->list.array[0]->tci_PresentInDCI; pos+=dci_pdu_rel15->transmission_configuration_indication.nbits;
if (isTciEnable != NULL) { *dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication.val&((1<<dci_pdu_rel15->transmission_configuration_indication.nbits)-1))<<(dci_size-pos);
pos+=3;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->transmission_configuration_indication&0x7)<<(dci_size-pos);
}
// SRS request // SRS request
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->crossCarrierSchedulingConfig==NULL) pos+=dci_pdu_rel15->srs_request.nbits;
nbits = 2; *dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request.val&((1<<dci_pdu_rel15->srs_request.nbits)-1))<<(dci_size-pos);
else
nbits = 3;
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->srs_request&((1<<nbits)-1))<<(dci_size-pos);
// CBG transmission information // CBG transmission information
uint8_t maxCBGperTB = (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->maxCodeBlockGroupsPerTransportBlock + 1) * 2; pos+=dci_pdu_rel15->cbgti.nbits;
long *maxCWperDCI_rrc = secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_Config->choice.setup->maxNrofCodeWordsScheduledByDCI; *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti.val&((1<<dci_pdu_rel15->cbgti.nbits)-1))<<(dci_size-pos);
uint8_t maxCWperDCI = (maxCWperDCI_rrc == NULL) ? 1 : *maxCWperDCI_rrc;
nbits = maxCBGperTB * maxCWperDCI;
pos+=nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgti&((1<<nbits)-1))<<(dci_size-pos);
// CBG flushing out information // CBG flushing out information
if (secondaryCellGroup->spCellConfig->spCellConfigDedicated->initialDownlinkBWP->pdsch_ServingCellConfig->choise.setup->codeBlockGroupTransmission->choise.setup->codeBlockGroupFlushIndicator) { pos+=dci_pdu_rel15->cbgfi.nbits;
pos+=1; *dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi.val&((1<<dci_pdu_rel15->cbgfi.nbits)-1))<<(dci_size-pos);
*dci_pdu |= ((uint64_t)dci_pdu_rel15->cbgfi&0x1)<<(dci_size-pos);
}
// DMRS sequence init // DMRS sequence init
pos+=1; pos+=dci_pdu_rel15->dmrs_sequence_initialization.nbits;
*dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization&0x1)<<(dci_size-pos); *dci_pdu |= ((uint64_t)dci_pdu_rel15->dmrs_sequence_initialization.val&((1<<dci_pdu_rel15->dmrs_sequence_initialization.nbits)-1))<<(dci_size-pos);
} }
} }
} }
......
...@@ -130,10 +130,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu, ...@@ -130,10 +130,7 @@ void nr_configure_pdcch(nfapi_nr_dl_tti_pdcch_pdu_rel15_t* pdcch_pdu,
NR_ServingCellConfigCommon_t *scc, NR_ServingCellConfigCommon_t *scc,
NR_BWP_Downlink_t *bwp); NR_BWP_Downlink_t *bwp);
void fill_dci_pdu_rel15(NR_CellGroupConfig_t *secondaryCellGroup, void fill_dci_pdu_rel15(nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
nfapi_nr_dl_tti_pdsch_pdu_rel15_t *pdsch_pdu_rel15,
nfapi_nr_dl_tti_pdcch_pdu_rel15_t *pdcch_pdu_rel15,
nfapi_nr_pusch_pdu_t *pusch_pdu,
dci_pdu_rel15_t *dci_pdu_rel15, dci_pdu_rel15_t *dci_pdu_rel15,
int *dci_formats, int *dci_formats,
int *rnti_types); int *rnti_types);
...@@ -166,9 +163,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP); ...@@ -166,9 +163,11 @@ int add_new_nr_ue(module_id_t mod_idP, rnti_t rntiP);
int get_num_dmrs(uint16_t dmrs_mask ); int get_num_dmrs(uint16_t dmrs_mask );
uint16_t nr_dci_size(nr_dci_format_t format, uint16_t nr_dci_size(NR_CellGroupConfig_t *secondaryCellGroup,
nr_rnti_type_t rnti_type, dci_pdu_rel15_t *dci_pdu,
uint16_t N_RB); nr_dci_format_t format,
nr_rnti_type_t rnti_type,
uint16_t N_RB);
int allocate_nr_CCEs(gNB_MAC_INST *nr_mac, int allocate_nr_CCEs(gNB_MAC_INST *nr_mac,
int bwp_id, int bwp_id,
......
...@@ -190,7 +190,7 @@ typedef struct gNB_MAC_INST_s { ...@@ -190,7 +190,7 @@ typedef struct gNB_MAC_INST_s {
int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE]; int cce_list[MAX_NUM_BWP][MAX_NUM_CORESET][MAX_NUM_CCE];
} gNB_MAC_INST; } gNB_MAC_INST;
typedef struct { /*typedef struct {
uint8_t format_indicator; //1 bit uint8_t format_indicator; //1 bit
...@@ -250,8 +250,74 @@ uint8_t antenna_ports; ...@@ -250,8 +250,74 @@ uint8_t antenna_ports;
uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits uint16_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
uint16_t padding; uint16_t padding;
} dci_pdu_rel15_t; } dci_pdu_rel15_t;*/
typedef struct {
uint16_t val;
uint8_t nbits;
} dci_field_t;
typedef struct {
dci_field_t format_indicator; //1 bit
dci_field_t frequency_domain_assignment; //up to 16 bits
dci_field_t time_domain_assignment; // 4 bits
dci_field_t frequency_hopping_flag; //1 bit
dci_field_t ra_preamble_index; //6 bits
dci_field_t ss_pbch_index; //6 bits
dci_field_t prach_mask_index; //4 bits
dci_field_t vrb_to_prb_mapping; //0 or 1 bit
dci_field_t mcs[2]; //5 bits
dci_field_t ndi[2]; //1 bit
dci_field_t rv[2]; //2 bits
dci_field_t harq_pid; //4 bits
dci_field_t dai; //0, 2 or 4 bits
dci_field_t dai1; //1 or 2 bits
dci_field_t dai2; //0 or 2 bits
dci_field_t tpc; //2 bits
dci_field_t pucch_resource_indicator; //3 bits
dci_field_t pdsch_to_harq_feedback_timing_indicator; //0, 1, 2 or 3 bits
dci_field_t short_messages_indicator; //2 bits
dci_field_t short_messages; //8 bits
dci_field_t tb_scaling; //2 bits
dci_field_t carrier_indicator; //0 or 3 bits
dci_field_t bwp_indicator; //0, 1 or 2 bits
dci_field_t prb_bundling_size_indicator; //0 or 1 bits
dci_field_t rate_matching_indicator; //0, 1 or 2 bits
dci_field_t zp_csi_rs_trigger; //0, 1 or 2 bits
dci_field_t transmission_configuration_indication; //0 or 3 bits
dci_field_t srs_request; //2 bits
dci_field_t cbgti; //CBG Transmission Information: 0, 2, 4, 6 or 8 bits
dci_field_t cbgfi; //CBG Flushing Out Information: 0 or 1 bit
dci_field_t dmrs_sequence_initialization; //0 or 1 bit
dci_field_t srs_resource_indicator;
dci_field_t precoding_information;
dci_field_t csi_request;
dci_field_t ptrs_dmrs_association;
dci_field_t beta_offset_indicator; //0 or 2 bits
dci_field_t slot_format_indicator_count;
dci_field_t *slot_format_indicators;
dci_field_t pre_emption_indication_count;
dci_field_t *pre_emption_indications; //14 bit
dci_field_t block_number_count;
dci_field_t *block_numbers;
dci_field_t ul_sul_indicator; //0 or 1 bit
dci_field_t antenna_ports;
dci_field_t reserved; //1_0/C-RNTI:10 bits, 1_0/P-RNTI: 6 bits, 1_0/SI-&RA-RNTI: 16 bits
dci_field_t padding;
} dci_pdu_rel15_t;
#endif /*__LAYER2_NR_MAC_GNB_H__ */ #endif /*__LAYER2_NR_MAC_GNB_H__ */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment