Commit 53db39b8 authored by laurent's avatar laurent

split 7.3 ready for merge

parent 3d15918c
dev 1 128-ues 256_QAM_demod 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA Fix_SA_SIB1 NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_FR2_initsync_fixes NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_NGAP NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguration_FR2 NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq_b NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_UE_CONFIG_REQ_FIXES NR_UE_MAC_scheduler NR_UE_PUCCH_bugfixes NR_UE_RA_fixes NR_UE_SA NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_multiplexing_HARQ_CSI_PUCCH NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_ue_dlsch_dmrs_cdm PBCHNRTCFIX PUSCH_TA_update RA_CI_test RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC UE_DL_DCI_hotfix add-dmrs-test add-ru-docker-image avxllr bandwidth-testing bch-fixes-bitmap benetel_5g_prach_fix benetel_config_file_fix benetel_dpdk20 benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes benetel_phase_rotation benetel_phase_rotation_old bsr-fix bugfix-free-ra-process bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-fix-module-ul-iperf ci-new-docker-pipeline ci-rd-july-improvements ci-reduce-nb-vms ci-test ci-ul-iperf-from-trf-container ci_benetel_longrun_limits ci_benetel_test ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_phytest ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_vm_resource_fix clean-5G-scope-round2 cleanup_softmodem_main constant_power debug-UL-5GRECORDS debug_UL_signal detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-aw2sori develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop-wf-du develop_inria_ci_deployment develop_inria_ci_deployment_gp develop_integration_2020_w19 develop_stable dfts_alternatives disable_CSI_measrep dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel docker-improvements-2021-april docker-no-cache-option dongzhanyi-zte-develop dongzhanyi-zte-develop1 dongzhanyi-zte-develop2 enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fedora-gen-kernel-fix fembms-enb-ue fft_bench_hotfix finalize-oaicn-integration firas fix-check fix-ci-tun fix-compile fix-itti-segv fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-quectel fix-realtime fix-retransmission-rbg fix-softmodem-restart fix-warnings fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_do_ra_data fix_nr_ulsim fix_pdsch_low_prb fix_rb_corruption fix_reestablishment fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun fixgtpu flexran-apps flexran-repair-mme-mgmt flexran-rtc-repo-is-public fujitsu_lte_contribution fujitsu_lte_contribution-128 git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-only-test gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-bch-no-sched-sf-0 hack-exit-gnb-when-no-enb-nsa harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable hotfix-ue-musim-compilation improve_nr_modulation improve_ue_stability integ-w13-test-rt-issue integration_2020_wk15 integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_w5GC_CBRA_test inter-RRU-final inter-RRU-oairu inter-rru-UE itti-enhancement ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-offload ldpc_offload_t1 ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 migrate-cpp-check-container migrate-vm-pipeline-to-bionic minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu nfapi-bugfix nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-small-bugfixes nr-pdcp-srb-integrity nr-ra-fix nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nr-stats-print nrPBCHTCFix nrPbchTcFix nrUE nrUE-hs nrUE-upper-layer nr_bsr nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_fdd_if_fix nr_improve_chanest nr_polar_decoder_improvement nr_power_measurement_fixes nr_prach_fr2 nr_ue_msg3 nr_ue_pdcp_fix nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oairu oairu-dockerfile-support oc-docker-october-improvements openxg/develop pdcp-benchmark phy-asan-fixes physim-build-deploy physim-deploy-handle-error-cases polar8 prb_based_dl_channel_estimation ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul recursive-cmake remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert_memcpy rh-ci-add-ue-parallelization rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins rh_ci_nsa_test_n310 rh_ci_oc rh_ci_phy_test_improve rh_ci_py rh_ci_ra_fr2 rh_ci_rfsim_ra rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_nsa_wk16 rh_ci_test_nsa_wk17_b rh_ci_test_nsa_wk17b rh_ci_test_rfsim_sa rh_ci_ue_parallel rh_doc_update_3 rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rlc_v2_coverity_fixes rohan_ulsim2RxFix rrc-enb-phy-testmode s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-demo-hs sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz sanitize-address sanitize-v1 sanitize-v1-tmp sarma_pvnp_oai scs_60_iisc sim-channels small-bugfixes-w40 small-config-change small_nr_bugfixes smallcleanup split73 t-gnb-tracer test-5GREC test-nsa-benetel test-panos test_nsa_gtpu_fix test_rt-fix_phy-test testing_2symb_pdcch testing_with_external_txdata tp-ota-test trx_thread_param ue-csi ue-dci-false-detection ue-fixes ue-fixes-ota ue-pdsch-pusch-parallel ue-race-fix ue_beam_selection ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes usrp_fix_adc_shift_and_pps_sync usrp_stop_cleanly usrp_x400 wf-sa-rrc wf_testc wireshark-T-hack-ueid wireshark-log-scheduling-requests wk11-with-phytest x2-endc-processing x2_handle_sctp_shutdown xiangwab xiangwan xw2 yihongzheng_srb zzs 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 2021.w05 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 2020.w26 2020.w25 2020.w24 2020.w23 2020.w22 2020.w19 2020.w17 benetel_phase_rotation benetel_gnb_rel_2.0 benetel_gnb_rel_1.0 benetel_enb_rel_2.0 benetel_enb_rel_1.0
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......@@ -1181,9 +1181,6 @@ set(SCHED_SRC
add_library(SCHED_LIB ${SCHED_SRC})
add_dependencies(SCHED_LIB rrc_flag)
add_library(SCHED_LIB_FS6 ${SCHED_SRC})
target_compile_definitions(SCHED_LIB_FS6 PRIVATE FS6=1)
add_dependencies(SCHED_LIB_FS6 rrc_flag)
set(SCHED_NR_SRC
${OPENAIR1_DIR}/SCHED_NR/fapi_nr_l1.c
${OPENAIR1_DIR}/SCHED_NR/phy_procedures_nr_common.c
......@@ -1563,8 +1560,6 @@ endif ()
add_library(PHY_COMMON ${PHY_SRC_COMMON})
add_dependencies(PHY_COMMON rrc_flag)
add_library(PHY ${PHY_SRC})
add_library(PHY_FS6 ${PHY_SRC})
target_compile_definitions(PHY_FS6 PRIVATE FS6=1)
add_dependencies(PHY rrc_flag)
add_library(PHY_UE ${PHY_SRC_UE})
......@@ -2485,13 +2480,11 @@ target_link_libraries (lte-softmodem ${T_LIB})
add_executable(ocp-softmodem
${OPENAIR_TARGETS}/RT/USER/rt_wrapper.c
${OPENAIR_DIR}/executables/main-ocp.c
${OPENAIR_DIR}/common/utils/threadPool/thread-pool.c
${OPENAIR_DIR}/executables/softmodem-common.c
${OPENAIR_DIR}/executables/main-fs6.c
${OPENAIR_DIR}/executables/transport_split.c
${OPENAIR_TARGETS}/RT/USER/lte-softmodem.c
${OPENAIR2_DIR}/ENB_APP/NB_IoT_interface.c
${OPENAIR1_DIR}/SIMULATION/TOOLS/taus.c
${OPENAIR_TARGETS}/COMMON/create_tasks.c
......@@ -2511,7 +2504,6 @@ add_executable(ocp-softmodem
${CONFIG_SOURCES}
${SHLIB_LOADER_SOURCES}
)
target_compile_definitions(ocp-softmodem PRIVATE FS6=1)
add_dependencies(ocp-softmodem rrc_flag s1ap_flag x2_flag)
target_link_libraries (ocp-softmodem
......
......@@ -243,6 +243,8 @@ void configure_linux(void) {
// Set CPU frequency to it's maximum
if ( 0 != system("for d in /sys/devices/system/cpu/cpu[0-9]*; do cat $d/cpufreq/cpuinfo_max_freq > $d/cpufreq/scaling_min_freq; done"))
LOG_W(HW,"Can't set cpu frequency\n");
LOG_E(HW,"Can't set cpu frequency\n");
mlockall(MCL_CURRENT | MCL_FUTURE);
}
......@@ -258,26 +258,22 @@ lte-softmodem.
The functionality and parameters is the same, enhanced with FS6 mode.
The environment variable “fs6” enables the fs6 mode and decided to be cu
or du from the fs6 variable content.
A example configuration file is: $OPENAIR_DIR/enb.fs6.example.conf
The IP addresses in this file should be updated for each network.
The end line option “--split73” enables the fs6 (also called split 7.3) mode and decided to be cu or du.
Example:
`fs6=cu ./ocp-softmodem -O $OPENAIR_DIR/enb.fs6.example.conf --rfsim --log_config.phy_log_level debug
./ocp-softmodem -O $OPENAIR_DIR/enb.fs6.example.conf --rfsim --log_config.phy_log_level debug --split73 cu:127.0.0.1
`
Run the CU init of the split 6 eNB, that will call du on 127.0.0.1 address
Run the CU init of the split 6 eNB.
./ocp-softmodem -O $OPENAIR_DIR/enb.fs6.example.conf --rfsim --log_config.phy_log_level debug --split73 du:127.0.0.1
`fs6=du ./ocp-softmodem -O $OPENAIR_DIR/enb.fs6.example.conf --rfsim --log_config.phy_log_level debug
will run the du, calling the cu on 127.0.0.1
`
If the CU and the DU are not on the same machine, the remote address of each side need to be specified as per this example
`fs6=du FS6_REMOTE_IP=192.168.2.211 ./ocp-softmodem -O $OPENAIR_DIR/enb.fs6.example.conf --rfsim --log_config.phy_log_level debug
./ocp-softmodem -O $OPENAIR_DIR/enb.fs6.example.conf --rfsim --log_config.phy_log_level debug --split73 du:192.168.1.55
`
runs the functional split 6 DU
`./lte-uesoftmodem -C 2685000000 -r 50 --rfsim --rfsimulator.serveraddr 192.168.1.1 -d
......@@ -285,10 +281,7 @@ runs the functional split 6 DU
Runs the UE (to have the UE signal scope, compile it with make uescope)
CU and DU IP address and port are configurable in the eNB configuration
file (as X2, GTP, … interfaces).
CU+DU+UE can run with option --noS1 to avoid to use a EPC.
CU+DU+UE can run with option --noS1 to avoid to use a EPC and/or with --rfsim to simulate RF board
##5G and F1
......
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......@@ -758,7 +758,7 @@ void tx_rf(RU_t *ru,int frame,int slot, uint64_t timestamp) {
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_FRAME_NUMBER_TX0_RU, frame );
VCD_SIGNAL_DUMPER_DUMP_VARIABLE_BY_NAME( VCD_SIGNAL_DUMPER_VARIABLES_TTI_NUMBER_TX0_RU, slot );
for (i=0; i<ru->nb_tx; i++){
for (i=0; i<ru->nb_tx; i++) {
txp[i] = (void *)&ru->common.txdata[i][(slot*fp->samples_per_slot)-sf_extension];
}
......@@ -1210,7 +1210,7 @@ static void *ru_stats_thread(void *param) {
if (ru->feprx) print_meas(&ru->ofdm_demod_stats,"feprx",NULL,NULL);
if (ru->feptx_ofdm){
if (ru->feptx_ofdm) {
print_meas(&ru->precoding_stats,"feptx_prec",NULL,NULL);
print_meas(&ru->txdataF_copy_stats,"txdataF_copy",NULL,NULL);
print_meas(&ru->ofdm_mod_stats,"feptx_ofdm",NULL,NULL);
......@@ -1371,7 +1371,7 @@ static void *ru_thread( void *param ) {
int print_frame = 8;
int i = 0;
int aa;
// set default return value
// set default return value
ru_thread_status = 0;
// set default return value
......@@ -1499,9 +1499,9 @@ static void *ru_thread( void *param ) {
LOG_D(PHY,"RU proc: frame_rx = %d, tti_rx = %d\n", proc->frame_rx, proc->tti_rx);
LOG_D(PHY,"Copying rxdataF from RU to gNB\n");
for (aa=0;aa<ru->nb_rx;aa++)
memcpy((void*)RC.gNB[0][0]->common_vars.rxdataF[aa],
(void*)ru->common.rxdataF[aa], fp->symbols_per_slot*fp->ofdm_symbol_size*sizeof(int32_t));
for (aa=0; aa<ru->nb_rx; aa++)
memcpy((void *)RC.gNB[0][0]->common_vars.rxdataF[aa],
(void *)ru->common.rxdataF[aa], fp->symbols_per_slot*fp->ofdm_symbol_size*sizeof(int32_t));
// At this point, all information for subframe has been received on FH interface
......
......@@ -176,6 +176,10 @@ uint32_t target_ul_mcs = 20;
uint32_t timing_advance = 0;
uint64_t num_missed_slots=0; // counter for the number of missed slots
int split73=0;
void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_t *data, int dataLen, int r_offset) {
AssertFatal(false, "Must not be called in this context\n");
}
extern void reset_opp_meas(void);
extern void print_opp_meas(void);
......@@ -721,13 +725,9 @@ int restart_L1L2(module_id_t gnb_id) {
memcpy(&ru->nr_frame_parms, &RC.gNB[gnb_id][0]->frame_parms, sizeof(NR_DL_FRAME_PARMS));
set_function_spec_param(RC.ru[gnb_id]);
LOG_I(GNB_APP, "attempting to create ITTI tasks\n");
if (itti_create_task (TASK_RRC_ENB, rrc_enb_task, NULL) < 0) {
LOG_E(RRC, "Create task for RRC eNB failed\n");
return -1;
} else {
LOG_I(RRC, "Re-created task for RRC gNB successfully\n");
}
// No more rrc thread, as many race conditions are hidden behind
rrc_enb_init();
itti_mark_task_ready(TASK_RRC_ENB);
if (itti_create_task (TASK_L2L1, l2l1_task, NULL) < 0) {
LOG_E(PDCP, "Create task for L2L1 failed\n");
......@@ -775,7 +775,7 @@ void init_pdcp(void) {
uint32_t pdcp_initmask = (IS_SOFTMODEM_NOS1) ?
(PDCP_USE_NETLINK_BIT | LINK_ENB_PDCP_TO_IP_DRIVER_BIT) : LINK_ENB_PDCP_TO_GTPV1U_BIT;
if (IS_SOFTMODEM_NOS1){
if (IS_SOFTMODEM_NOS1) {
printf("IS_SOFTMODEM_NOS1 option enabled \n");
pdcp_initmask = pdcp_initmask | ENB_NAS_USE_TUN_BIT | SOFTMODEM_NOKRNMOD_BIT ;
}
......@@ -841,7 +841,7 @@ int main( int argc, char **argv )
MSC_INIT(MSC_E_UTRAN, THREAD_MAX+TASK_MAX);
#endif
init_opt();
init_opt();
#ifdef PDCP_USE_NETLINK
......@@ -883,7 +883,7 @@ init_opt();
mlockall(MCL_CURRENT | MCL_FUTURE);
pthread_cond_init(&sync_cond,NULL);
pthread_mutex_init(&sync_mutex, NULL);
/*#ifdef XFORMS
/*#ifdef XFORMS
int UE_id;
if (do_forms==1) {
......@@ -913,7 +913,7 @@ init_opt();
printf("Scope thread created, ret=%d\n",ret);
}
#endif*/
#endif*/
usleep(10*1000);
if (nfapi_mode) {
......@@ -1018,7 +1018,7 @@ init_opt();
printf("Terminating application - oai_exit=%d\n",oai_exit);
#endif
// stop threads
/*#ifdef XFORMS
/*#ifdef XFORMS
printf("waiting for XFORMS thread\n");
......@@ -1038,7 +1038,7 @@ init_opt();
}
}
#endif*/
#endif*/
printf("stopping MODEM threads\n");
// cleanup
stop_gNB(NB_gNB_INST);
......
......@@ -148,7 +148,7 @@ PHY_VARS_NR_UE *init_nr_ue_vars(NR_DL_FRAME_PARMS *frame_parms,
ue->Mod_id = UE_id;
ue->mac_enabled = 1;
// initialize all signal buffers
// initialize all signal buffers
init_nr_ue_signal(ue,1,abstraction_flag);
// intialize transport
......@@ -380,7 +380,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
scheduled_response.CC_id = 0;
scheduled_response.frame = proc->frame_rx;
scheduled_response.slot = proc->nr_tti_rx;
//--------------------------Temporary configuration-----------------------------//
//--------------------------Temporary configuration-----------------------------//
n_rnti = 0x1234;
nb_rb = 50;
......@@ -416,7 +416,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
LOG_D(PHY,"phy_procedures_nrUE_RX: slot:%d, time %lu\n", proc->nr_tti_rx, (rdtsc()-a)/3500);
//printf(">>> nr_ue_pdcch_procedures ended\n");
#endif
if(IS_SOFTMODEM_NOS1){ //&& proc->nr_tti_rx==1
if(IS_SOFTMODEM_NOS1) { //&& proc->nr_tti_rx==1
//Hardcoded rnti value
protocol_ctxt_t ctxt;
PROTOCOL_CTXT_SET_BY_MODULE_ID(&ctxt, UE->Mod_id, ENB_FLAG_NO,
......@@ -427,7 +427,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
}
}
// no UL for now
// no UL for now
/*
if (UE->mac_enabled==1) {
......@@ -465,7 +465,7 @@ void UE_processing(void *arg) {
PHY_VARS_NR_UE *UE = rxtxD->UE;
processSlotRX(UE, proc);
uint8_t gNB_id = 0;
// params for UL time alignment procedure
// params for UL time alignment procedure
NR_UL_TIME_ALIGNMENT_t *ul_time_alignment = &UE->ul_time_alignment[gNB_id];
uint8_t numerology = UE->frame_parms.numerology_index;
......@@ -475,24 +475,24 @@ void UE_processing(void *arg) {
//printf(">>> mac ended\n");
// Prepare the future Tx data
/*
#ifndef NO_RAT_NR
/*
#ifndef NO_RAT_NR
if (slot_select_nr(&UE->frame_parms, proc->frame_tx, proc->nr_tti_tx) & NR_UPLINK_SLOT)
#else
#else
if ((subframe_select( &UE->frame_parms, proc->subframe_tx) == SF_UL) ||
(UE->frame_parms.frame_type == FDD) )
#endif
*/
#endif
*/
/* UL time alignment
// If the current tx frame and slot match the TA configuration in ul_time_alignment
// then timing advance is processed and set to be applied in the next UL transmission */
if (UE->mac_enabled == 1) {
if (frame_tx == ul_time_alignment->ta_frame && slot_tx == ul_time_alignment->ta_slot){
if (frame_tx == ul_time_alignment->ta_frame && slot_tx == ul_time_alignment->ta_slot) {
LOG_D(PHY,"Applying timing advance -- frame %d -- slot %d\n", frame_tx, slot_tx);
//if (nfapi_mode!=3){
//if (nfapi_mode!=3){
nr_process_timing_advance(UE->Mod_id, UE->CC_id, ul_time_alignment->ta_command, numerology, bwp_ul_NB_RB);
ul_time_alignment->ta_frame = -1;
......@@ -501,7 +501,7 @@ void UE_processing(void *arg) {
}
}
if (proc->nr_tti_tx == NR_UPLINK_SLOT || UE->frame_parms.frame_type == FDD){
if (proc->nr_tti_tx == NR_UPLINK_SLOT || UE->frame_parms.frame_type == FDD) {
thread_id = PHY_vars_UE_g[UE->Mod_id][0]->current_thread_id[proc->nr_tti_tx];
......@@ -763,7 +763,7 @@ void *UE_thread(void *arg) {
readBlockSize,
UE->frame_parms.nb_antennas_rx),"");
if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX - 1)%20)
if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX - 1)%20)
AssertFatal( writeBlockSize ==
UE->rfdevice.trx_write_func(&UE->rfdevice,
timestamp+
......@@ -775,7 +775,7 @@ if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX - 1)%20)
UE->frame_parms.nb_antennas_tx,
2),"");
if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20)
if (slot_nr == (20+NR_UPLINK_SLOT-DURATION_RX_TO_TX)%20)
AssertFatal( writeBlockSize ==
UE->rfdevice.trx_write_func(&UE->rfdevice,
timestamp+
......
......@@ -214,7 +214,7 @@ int emulate_rf = 0;
tpool_t *Tpool;
#ifdef UE_DLSCH_PARALLELISATION
tpool_t *Tpool_dl;
tpool_t *Tpool_dl;
#endif
......@@ -382,9 +382,9 @@ static void get_options(void) {
int tddflag=0, nonbiotflag, vcdflag=0;
char *loopfile=NULL;
int dumpframe=0;
//uint32_t noS1;
//uint32_t nokrnmod;
//uint32_t nokrnmod;
paramdef_t cmdline_params[] =CMDLINE_PARAMS_DESC_UE ;
config_process_cmdline( cmdline_params,sizeof(cmdline_params)/sizeof(paramdef_t),NULL);
......@@ -516,7 +516,7 @@ void init_openair0(void) {
LOG_E(PHY,"Unsupported numerology!\n");
exit(-1);
}
}else if(frame_parms[0]->N_RB_DL == 273) {
} else if(frame_parms[0]->N_RB_DL == 273) {
if (numerology==1) {
if (frame_parms[0]->threequarter_fs) {
AssertFatal(0 == 1,"three quarter sampling not supported for N_RB 273\n");
......@@ -529,7 +529,7 @@ void init_openair0(void) {
LOG_E(PHY,"Unsupported numerology!\n");
exit(-1);
}
}else if(frame_parms[0]->N_RB_DL == 106) {
} else if(frame_parms[0]->N_RB_DL == 106) {
if (numerology==0) {
if (frame_parms[0]->threequarter_fs) {
openair0_cfg[card].sample_rate=23.04e6;
......@@ -668,7 +668,7 @@ int main( int argc, char **argv ) {
#ifdef UE_DLSCH_PARALLELISATION
tpool_t pool_dl;
Tpool_dl = &pool_dl;
char params_dl[]="-1,-1,-1,-1, -1,-1,-1,-1,-1,-1,-1,-1,-1,-1";
char params_dl[]="-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1";
initTpool(params_dl, Tpool_dl, false);
#endif
cpuf=get_cpu_freq_GHz();
......@@ -682,15 +682,15 @@ int main( int argc, char **argv ) {
vcd_signal_dumper_init("/tmp/openair_dump_nrUE.vcd");
}
/*
#ifdef PDCP_USE_NETLINK
/*
#ifdef PDCP_USE_NETLINK
netlink_init();
#if defined(PDCP_USE_NETLINK_QUEUES)
#if defined(PDCP_USE_NETLINK_QUEUES)
pdcp_netlink_init();
#endif
#endif
*/
#ifndef PACKAGE_VERSION
#endif
#endif
*/
#ifndef PACKAGE_VERSION
# define PACKAGE_VERSION "UNKNOWN-EXPERIMENTAL"
#endif
LOG_I(HW, "Version: %s\n", PACKAGE_VERSION);
......
......@@ -37,6 +37,11 @@ extern "C"
#endif
/* help strings definition for command line options, used in CMDLINE_XXX_DESC macros and printed when -h option is used */
#define CONFIG_HLP_RFCFGF "Configuration file for front-end (e.g. LMS7002M)\n"
#define CONFIG_HLP_SPLIT73 "Split 7.3 (below rate matching) option: <cu|du>:<remote ip address>:<remote port>"
#define CONFIG_HLP_TPOOL "Thread pool configuration: \n\
default no pool (runs in calling thread),\n\
list of cores, comma separated (negative value is no core affinity)\n\
example: -1,3 launches two working threads one floating, the second set on core 3"
#define CONFIG_HLP_ULMAXE "set the eNodeB max ULSCH erros\n"
#define CONFIG_HLP_CALUER "set UE RX calibration\n"
#define CONFIG_HLP_CALUERM ""
......@@ -87,6 +92,7 @@ extern "C"
/* optname helpstr paramflags XXXptr defXXXval type numelt */
/*-----------------------------------------------------------------------------------------------------------------------------------------------------*/
#define RF_CONFIG_FILE softmodem_params.rf_config_file
#define SPLIT73 softmodem_params.split73
#define TP_CONFIG softmodem_params.threadPoolConfig
#define PHY_TEST softmodem_params.phy_test
#define WAIT_FOR_SYNC softmodem_params.wait_for_sync
......@@ -103,6 +109,8 @@ extern "C"
#define CMDLINE_PARAMS_DESC { \
{"rf-config-file", CONFIG_HLP_RFCFGF, 0, strptr:(char **)&RF_CONFIG_FILE, defstrval:NULL, TYPE_STRING, sizeof(RF_CONFIG_FILE)},\
{"split73", CONFIG_HLP_SPLIT73, 0, strptr:(char **)&SPLIT73, defstrval:NULL, TYPE_STRING, sizeof(SPLIT73)},\
{"thread-pool", CONFIG_HLP_TPOOL, 0, strptr:(char **)&TP_CONFIG, defstrval:"n", TYPE_STRING, sizeof(TP_CONFIG)}, \
{"phy-test", CONFIG_HLP_PHYTST, PARAMFLAG_BOOL, iptr:&PHY_TEST, defintval:0, TYPE_INT, 0}, \
{"usim-test", CONFIG_HLP_USIM, PARAMFLAG_BOOL, u8ptr:&USIM_TEST, defintval:0, TYPE_UINT8, 0}, \
{"clock", CONFIG_HLP_CLK, 0, uptr:&CLOCK_SOURCE, defintval:0, TYPE_UINT, 0}, \
......@@ -179,6 +187,7 @@ typedef struct {
uint64_t optmask;
THREAD_STRUCT thread_struct;
char rf_config_file[1024];
char split73[1024];
char threadPoolConfig[1024];
int phy_test;
uint8_t usim_test;
......
......@@ -5,10 +5,11 @@
#include <stdbool.h>
#include <openair1/PHY/defs_eNB.h>
#define CU_IP "127.0.0.1"
#define CU_PORT "7878"
#define DU_IP "127.0.0.1"
#define DU_PORT "8787"
#define SPLIT73_CU 1
#define SPLIT73_DU 2
extern int split73;
#define MTU 65536
#define UDP_TIMEOUT 900000L // in micro second (struct timeval, NOT struct timespec)
......
......@@ -310,7 +310,7 @@ static void TPencode(void * arg) {
lte_rate_matching_turbo(hadlsch->RTC[rdata->r],
rdata->G, //G
hadlsch->w[rdata->r],
hadlsch->e+rdata->r_offset,
hadlsch->eDL+rdata->r_offset,
hadlsch->C, // C
rdata->dlsch->Nsoft, // Nsoft,
rdata->dlsch->Mdlharq,
......@@ -389,7 +389,7 @@ int dlsch_encoding(PHY_VARS_eNB *eNB,
for (int r=0, r_offset=0; r<hadlsch->C; r++) {
union turboReqUnion id= {.s={dlsch->rnti,frame,subframe,r,0}};
notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboEncode_t), id.p, &proc->respEncode, TPencode);
notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboEncode_t), id.p, proc->respEncode, TPencode);
turboEncode_t * rdata=(turboEncode_t *) NotifiedFifoData(req);
rdata->input=hadlsch->c[r];
rdata->Kr_bytes= ( r<hadlsch->Cminus ? hadlsch->Kminus : hadlsch->Kplus) >>3;
......@@ -404,8 +404,8 @@ int dlsch_encoding(PHY_VARS_eNB *eNB,
rdata->r_offset=r_offset;
rdata->G=G;
if ( proc->threadPool.activated) {
pushTpool(&proc->threadPool,req);
if ( proc->threadPool->activated ) {
pushTpool(proc->threadPool,req);
proc->nbEncode++;
} else {
TPencode(rdata);
......
......@@ -158,7 +158,7 @@ int allocate_REs_in_RB_no_pilots_QPSK_siso(PHY_VARS_eNB* phy_vars_eNB,
{
LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->frame_parms;
uint8_t *x0 = dlsch0_harq->e;
uint8_t *x0 = dlsch0_harq->eDL;
uint32_t qpsk_table_offset_re = 0;
uint32_t qpsk_table_offset_im = 0;
......@@ -248,7 +248,7 @@ int allocate_REs_in_RB_pilots_QPSK_siso(PHY_VARS_eNB* phy_vars_eNB,
LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_eNB->frame_parms;
uint8_t *x0 = dlsch0_harq->e;
uint8_t *x0 = dlsch0_harq->eDL;
uint32_t qpsk_table_offset_re = 0;
uint32_t qpsk_table_offset_im = 0;
......@@ -343,7 +343,7 @@ int allocate_REs_in_RB_no_pilots_16QAM_siso(PHY_VARS_eNB* phy_vars_eNB,
{
LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->frame_parms;
uint8_t *x0 = dlsch0_harq->e;
uint8_t *x0 = dlsch0_harq->eDL;
uint32_t qam16_table_offset_re = 0;
uint32_t qam16_table_offset_im = 0;
......@@ -439,7 +439,7 @@ int allocate_REs_in_RB_pilots_16QAM_siso(PHY_VARS_eNB* phy_vars_eNB,
LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_eNB->frame_parms;
uint8_t *x0 = dlsch0_harq->e;
uint8_t *x0 = dlsch0_harq->eDL;
uint32_t qam16_table_offset_re = 0;
uint32_t qam16_table_offset_im = 0;
......@@ -542,7 +542,7 @@ int allocate_REs_in_RB_no_pilots_64QAM_siso(PHY_VARS_eNB* phy_vars_eNB,
LTE_DL_FRAME_PARMS *frame_parms = &phy_vars_eNB->frame_parms;
uint8_t *x0 = dlsch0_harq->e;
uint8_t *x0 = dlsch0_harq->eDL;
uint32_t qam64_table_offset_re = 0;
uint32_t qam64_table_offset_im = 0;
......@@ -699,7 +699,7 @@ int allocate_REs_in_RB_pilots_64QAM_siso(PHY_VARS_eNB* phy_vars_eNB,
LTE_DL_FRAME_PARMS *frame_parms=&phy_vars_eNB->frame_parms;
uint8_t *x0 = dlsch0_harq->e;
uint8_t *x0 = dlsch0_harq->eDL;
uint32_t qam64_table_offset_re = 0;
uint32_t qam64_table_offset_im = 0;
......@@ -866,12 +866,12 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB,
if ((dlsch0_harq != NULL) && (dlsch1_harq != NULL)) { //this is for TM3, TM4
x0 = dlsch0_harq->e;
x0 = dlsch0_harq->eDL;
mimo_mode = dlsch0_harq->mimo_mode;
first_layer0 = dlsch0_harq->first_layer;
Nlayers0 = dlsch0_harq->Nlayers;
mod_order0 = dlsch0_harq->Qm;
x1 = dlsch1_harq->e;
x1 = dlsch1_harq->eDL;
// Fill these in later for TM8-10
// Nlayers1 = dlsch1_harq->Nlayers;
// first_layer1 = dlsch1_harq->first_layer;
......@@ -879,7 +879,7 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB,
} else if ((dlsch0_harq != NULL) && (dlsch1_harq == NULL)){ //This is for SIS0 TM1, TM6, etc
x0 = dlsch0_harq->e;
x0 = dlsch0_harq->eDL;
mimo_mode = dlsch0_harq->mimo_mode;
first_layer0 = dlsch0_harq->first_layer;
Nlayers0 = dlsch0_harq->Nlayers;
......@@ -887,7 +887,7 @@ int allocate_REs_in_RB(PHY_VARS_eNB* phy_vars_eNB,
} else if ((dlsch0_harq == NULL) && (dlsch1_harq != NULL)){ // This is for TM4 retransmission
x0 = dlsch1_harq->e;
x0 = dlsch1_harq->eDL;
mimo_mode = dlsch1_harq->mimo_mode;
first_layer0 = dlsch1_harq->first_layer;
Nlayers0 = dlsch1_harq->Nlayers;
......@@ -2692,7 +2692,7 @@ int dlsch_modulation_SIC(int32_t **sic_buffer,
LTE_DL_eNB_HARQ_t *dlsch0_harq = dlsch0->harq_processes[harq_pid];
uint32_t i,jj,re_allocated=0;
uint8_t mod_order0 = dlsch0_harq->Qm;
uint8_t *x0 = dlsch0_harq->e;
uint8_t *x0 = dlsch0_harq->eDL;
uint8_t qam64_table_offset_re = 0;
uint8_t qam64_table_offset_im = 0;
uint8_t qam16_table_offset_re = 0;
......@@ -2883,7 +2883,7 @@ int mch_modulation(int32_t **txdataF,
&jj,
re_offset,
symbol_offset,
dlsch->harq_processes[0]->e,
dlsch->harq_processes[0]->eDL,
l,
mod_order,
amp,
......
......@@ -52,7 +52,7 @@ void dlsch_scrambling(LTE_DL_FRAME_PARMS *frame_parms,
int n;
// uint8_t reset;
uint32_t x1, x2, s=0;
uint8_t *dlsch_e=dlsch->harq_processes[harq_pid]->e;
uint8_t *dlsch_e=dlsch->harq_processes[harq_pid]->eDL;
uint8_t *e=dlsch_e;
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_ENB_DLSCH_SCRAMBLING, VCD_FUNCTION_IN);
// Rule for accumulation of subframes for BL/CE UEs
......
......@@ -100,7 +100,7 @@ typedef struct {
/// start symbold of pdsch
uint8_t pdsch_start;
/// Concatenated "e"-sequences (for definition see 36-212 V8.6 2009-03, p.17-18)
uint8_t e[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32)));
uint8_t eDL[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32)));
/// Turbo-code outputs (36-212 V8.6 2009-03, p.12
uint8_t *d[MAX_NUM_DLSCH_SEGMENTS];//[(96+3+(3*6144))];
/// Sub-block interleaver outputs (36-212 V8.6 2009-03, p.16-17)
......@@ -261,11 +261,11 @@ typedef struct {
/// coded RI bits
int16_t q_RI[MAX_RI_PAYLOAD];
/// Concatenated "e"-sequences (for definition see 36-212 V8.6 2009-03, p.17-18)
int16_t e[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32)));
int16_t eUL[MAX_NUM_CHANNEL_BITS] __attribute__((aligned(32)));
/// Temporary h sequence to flag PUSCH_x/PUSCH_y symbols which are not scrambled
uint8_t h[MAX_NUM_CHANNEL_BITS];
/// Pointer to the payload
uint8_t *b;
uint8_t *decodedBytes;
/// Pointers to transport block segments
//TBD
uint8_t *c[MAX_NUM_ULSCH_SEGMENTS];
......
......@@ -54,9 +54,9 @@ void free_eNB_ulsch(LTE_eNB_ULSCH_t *ulsch) {
if (ulsch) {
for (i=0; i<8; i++) {
if (ulsch->harq_processes[i]) {
if (ulsch->harq_processes[i]->b) {
free16(ulsch->harq_processes[i]->b,MAX_ULSCH_PAYLOAD_BYTES);
ulsch->harq_processes[i]->b = NULL;
if (ulsch->harq_processes[i]->decodedBytes) {
free16(ulsch->harq_processes[i]->decodedBytes,MAX_ULSCH_PAYLOAD_BYTES);
ulsch->harq_processes[i]->decodedBytes = NULL;
}
for (r=0; r<MAX_NUM_ULSCH_SEGMENTS; r++) {
......@@ -115,10 +115,10 @@ LTE_eNB_ULSCH_t *new_eNB_ulsch(uint8_t max_turbo_iterations,uint8_t N_RB_UL, uin
if (ulsch->harq_processes[i]) {
memset(ulsch->harq_processes[i],0,sizeof(LTE_UL_eNB_HARQ_t));
ulsch->harq_processes[i]->b = (uint8_t *)malloc16(MAX_ULSCH_PAYLOAD_BYTES/bw_scaling);
ulsch->harq_processes[i]->decodedBytes = (uint8_t *)malloc16(MAX_ULSCH_PAYLOAD_BYTES/bw_scaling);
if (ulsch->harq_processes[i]->b)
memset(ulsch->harq_processes[i]->b,0,MAX_ULSCH_PAYLOAD_BYTES/bw_scaling);
if (ulsch->harq_processes[i]->decodedBytes)
memset(ulsch->harq_processes[i]->decodedBytes,0,MAX_ULSCH_PAYLOAD_BYTES/bw_scaling);
else
exit_flag=3;
......@@ -229,7 +229,7 @@ void processULSegment(void * arg) {
G,
ulsch_harq->w[r],
(uint8_t *) &dummy_w[0],
ulsch_harq->e+rdata->r_offset,
ulsch_harq->eUL+rdata->r_offset,
ulsch_harq->C,
NSOFT,
0, //Uplink
......@@ -327,19 +327,15 @@ int ulsch_decoding_data(PHY_VARS_eNB *eNB, L1_rxtx_proc_t *proc,
E = ulsch_harq->Qm * (Gp/ulsch_harq->C);
else
E = ulsch_harq->Qm * ((GpmodC==0?0:1) + (Gp/ulsch_harq->C));
#ifdef FS6
if ( getenv("fs6") != NULL && strncasecmp( getenv("fs6"), "du", 2) == 0 ) {
sendFs6Ul(eNB, UE_id, harq_pid, r, ulsch_harq->e+r_offset, E*sizeof(int16_t), r_offset);
if ( split73 == SPLIT73_DU ) {
sendFs6Ul(eNB, UE_id, harq_pid, r, ulsch_harq->eUL+r_offset, E*sizeof(int16_t), r_offset);
r_offset += E;
continue;
}
#endif
union turboReqUnion id= {.s={ulsch->rnti,proc->frame_rx,proc->subframe_rx,0,0}};
notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboDecode_t), id.p, &proc->respDecode, processULSegment);
notifiedFIFO_elt_t *req=newNotifiedFIFO_elt(sizeof(turboDecode_t), id.p, proc->respDecode, processULSegment);
turboDecode_t * rdata=(turboDecode_t *) NotifiedFifoData(req);
rdata->eNB=eNB;
......@@ -359,7 +355,7 @@ int ulsch_decoding_data(PHY_VARS_eNB *eNB, L1_rxtx_proc_t *proc,
rdata->function=td;
int Fbytes=(r==0) ? rdata->Fbits>>3 : 0;
int sz=Kr_bytes - Fbytes - ((ulsch_harq->C>1)?3:0);
pushTpool(&proc->threadPool,req);
pushTpool(proc->threadPool,req);
proc->nbDecode++;
LOG_D(PHY,"Added a block to decode, in pipe: %d\n",proc->nbDecode);
r_offset+=E;
......@@ -892,8 +888,8 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,
j2+=2;
}
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
}
break;
......@@ -905,10 +901,10 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,
j2+=4;
}
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
}
break;
......@@ -920,12 +916,12 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,
j2+=6;
}
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->e[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
ulsch_harq->eUL[iprime++] = y[j2++];
}
break;
......@@ -963,7 +959,7 @@ unsigned int ulsch_decoding(PHY_VARS_eNB *eNB,
*/
int16_t *yp,*ep;
for (iprime=0,yp=&y[j2],ep=&ulsch_harq->e[0];
for (iprime=0,yp=&y[j2],ep=&ulsch_harq->eUL[0];
iprime<G;
iprime+=8,j2+=8,ep+=8,yp+=8) {
ep[0] = yp[0];
......
......@@ -793,7 +793,7 @@ int dlsch_encoding_SIC(PHY_VARS_UE *ue,
r_offset += lte_rate_matching_turbo(dlsch->harq_processes[harq_pid]->RTC[r],
G, //G
dlsch->harq_processes[harq_pid]->w[r],
dlsch->harq_processes[harq_pid]->e+r_offset,
dlsch->harq_processes[harq_pid]->eDL+r_offset,
dlsch->harq_processes[harq_pid]->C, // C
dlsch->Nsoft, // Nsoft,
dlsch->Mdlharq,
......
......@@ -2032,7 +2032,7 @@ uint16_t nr_dci_format_size (PHY_VARS_NR_UE *ue,
ul_res_alloc_type_1 = 1;
}
uint8_t n_bits_freq_dom_res_assign_ul=0,n_ul_RGB_tmp;
uint8_t n_bits_freq_dom_res_assign_ul=0,n_ul_RGB_tmp=0;
if (ul_res_alloc_type_0 == 1) { // implementation of Table 6.1.2.2.1-1 TC 38.214 subclause 6.1.2.2.1
// config1: PUSCH-Config IE contains rbg-Size ENUMERATED {config1 config2}
......
......@@ -320,10 +320,10 @@ bool dlsch_procedures(PHY_VARS_eNB *eNB,
&eNB->dlsch_interleaving_stats);
stop_meas(&eNB->dlsch_encoding_stats);
if ( proc->threadPool.activated ) {
if ( proc->threadPool->activated ) {
// Wait all other threads finish to process
while (proc->nbEncode) {
delNotifiedFIFO_elt(pullTpool(&proc->respEncode, &proc->threadPool));
delNotifiedFIFO_elt(pullTpool(proc->respEncode, proc->threadPool));
proc->nbEncode--;
}
}
......@@ -604,12 +604,11 @@ void srs_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) {
}
void fill_sr_indication(int UEid, PHY_VARS_eNB *eNB,uint16_t rnti,int frame,int subframe,uint32_t stat) {
#ifdef FS6
if ( getenv("fs6") != NULL && strncasecmp( getenv("fs6"), "du", 2) == 0 ) {
if ( split73 == SPLIT73_DU ) {
sendFs6Ulharq(fs6ULindicationSr, UEid, eNB, NULL, frame, subframe, NULL,0,0, rnti, stat);
return;
}
#endif
pthread_mutex_lock(&eNB->UL_INFO_mutex);
nfapi_sr_indication_t *sr_ind = &eNB->UL_INFO.sr_ind;
nfapi_sr_indication_body_t *sr_ind_body = &sr_ind->sr_indication_body;
......@@ -1175,13 +1174,13 @@ void postDecode(L1_rxtx_proc_t *proc, notifiedFIFO_elt_t *req) {
if (decodeSucess) {
int Fbytes=(rdata->segment_r==0) ? rdata->Fbits>>3 : 0;
int sz=(rdata->Kr>>3) - Fbytes - ((ulsch_harq->C>1)?3:0);
memcpy(ulsch_harq->b+rdata->offset,
memcpy(ulsch_harq->decodedBytes+rdata->offset,
rdata->decoded_bytes+Fbytes,
sz);
} else {
if ( rdata->nbSegments != ulsch_harq->processedSegments ) {
int nb=abortTpool(&proc->threadPool, req->key);
nb+=abortNotifiedFIFO(&proc->respDecode, req->key);
int nb=abortTpool(proc->threadPool, req->key);
nb+=abortNotifiedFIFO(proc->respDecode, req->key);
proc->nbDecode-=nb;
LOG_I(PHY,"uplink segment error %d/%d, aborted %d segments\n",rdata->segment_r,rdata->nbSegments, nb);
AssertFatal(ulsch_harq->processedSegments+nb == rdata->nbSegments,"processed: %d, aborted: %d, total %d\n",
......@@ -1329,7 +1328,7 @@ void pusch_procedures(PHY_VARS_eNB *eNB,L1_rxtx_proc_t *proc) {
} // for (i=0; i<NUMBER_OF_UE_MAX; i++)
while (proc->nbDecode > 0) {
notifiedFIFO_elt_t *req=pullTpool(&proc->respDecode, &proc->threadPool);
notifiedFIFO_elt_t *req=pullTpool(proc->respDecode, proc->threadPool);
postDecode(proc, req);
delNotifiedFIFO_elt(req);
}
......@@ -1415,7 +1414,7 @@ void fill_rx_indication(PHY_VARS_eNB *eNB,
pdu->rx_indication_rel8.tl.tag = NFAPI_RX_INDICATION_REL8_TAG;
pdu->rx_indication_rel8.length = eNB->ulsch[UE_id]->harq_processes[harq_pid]->TBS>>3;
pdu->rx_indication_rel8.offset = 1; // DJP - I dont understand - but broken unless 1 ???? 0; // filled in at the end of the UL_INFO formation
pdu->data = eNB->ulsch[UE_id]->harq_processes[harq_pid]->b;
pdu->data = eNB->ulsch[UE_id]->harq_processes[harq_pid]->decodedBytes;
// estimate timing advance for MAC
sync_pos = lte_est_timing_advance_pusch(eNB,UE_id);
timing_advance_update = sync_pos; // - eNB->frame_parms.nb_prefix_samples/4; //to check
......@@ -1749,12 +1748,10 @@ void fill_ulsch_harq_indication (PHY_VARS_eNB *eNB, LTE_UL_eNB_HARQ_t *ulsch_har
}
void fill_uci_harq_indication (int UEid, PHY_VARS_eNB *eNB, LTE_eNB_UCI *uci, int frame, int subframe, uint8_t *harq_ack, uint8_t tdd_mapping_mode, uint16_t tdd_multiplexing_mask) {
#ifdef FS6
if ( getenv("fs6") != NULL && strncasecmp( getenv("fs6"), "du", 2) == 0 ) {
if ( split73 == SPLIT73_DU ) {
sendFs6Ulharq(fs6ULindicationHarq, UEid, eNB, uci, frame, subframe, harq_ack, tdd_mapping_mode, tdd_multiplexing_mask, 0, 0);
return;
}
#endif
int UE_id=find_dlsch(uci->rnti,eNB,SEARCH_EXIST);
......
......@@ -1266,9 +1266,12 @@ int main(int argc, char **argv) {
}
L1_rxtx_proc_t *proc_eNB = &eNB->proc.L1_proc;
initTpool("n", &proc_eNB->threadPool, true);
initNotifiedFIFO(&proc_eNB->respEncode);
initNotifiedFIFO(&proc_eNB->respDecode);
proc_eNB->threadPool=(tpool_t*)malloc(sizeof(tpool_t));
proc_eNB->respEncode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t));
proc_eNB->respDecode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t));
initTpool("n", proc_eNB->threadPool, true);
initNotifiedFIFO(proc_eNB->respEncode);
initNotifiedFIFO(proc_eNB->respDecode);
proc_eNB->frame_tx=0;
......
......@@ -793,9 +793,12 @@ int main(int argc, char **argv) {
proc_rxtx_ue->frame_rx = (subframe<4)?(proc_rxtx->frame_tx-1):(proc_rxtx->frame_tx);
proc_rxtx_ue->subframe_tx = proc_rxtx->subframe_rx;
proc_rxtx_ue->subframe_rx = (proc_rxtx->subframe_tx+6)%10;
initTpool("n", &proc_rxtx->threadPool, true);
initNotifiedFIFO(&proc_rxtx->respEncode);
initNotifiedFIFO(&proc_rxtx->respDecode);
proc_rxtx->threadPool=(tpool_t*)malloc(sizeof(tpool_t));
proc_rxtx->respEncode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t));
proc_rxtx->respDecode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t));
initTpool("n",proc_rxtx->threadPool, true);
initNotifiedFIFO(proc_rxtx->respEncode);
initNotifiedFIFO(proc_rxtx->respDecode);
printf("Init UL hopping UE\n");
init_ul_hopping(&UE->frame_parms);
......
......@@ -176,11 +176,11 @@ typedef struct {
pthread_cond_t cond_RUs;
/// mutex for RXn-TXnp4 processing thread
pthread_mutex_t mutex_RUs;
tpool_t threadPool;
tpool_t *threadPool;
int nbEncode;
int nbDecode;
notifiedFIFO_t respEncode;
notifiedFIFO_t respDecode;
notifiedFIFO_t *respEncode;
notifiedFIFO_t *respDecode;
pthread_mutex_t mutex_emulateRF;
int instance_cnt_emulateRF;
pthread_t pthread_emulateRF;
......
......@@ -346,7 +346,7 @@ static int rfsimulator_write_internal(rfsimulator_state_t *t, openair0_timestamp
if ( t->lastWroteTS != 0 && abs((double)t->lastWroteTS-timestamp) > (double)CirSize)
LOG_E(HW,"Discontinuous TX gap too large Tx:%lu, %lu\n", t->lastWroteTS, timestamp);
if (t->lastWroteTS >= timestamp+1)
if (t->lastWroteTS > timestamp+nsamps)
LOG_E(HW,"Not supported to send Tx out of order (same in USRP) %lu, %lu\n",
t->lastWroteTS, timestamp);
t->lastWroteTS=timestamp+nsamps;
......@@ -468,8 +468,8 @@ static bool flushInput(rfsimulator_state_t *t, int timeout, int nsamps_for_initi
} else if ( b->lastReceivedTS == b->th.timestamp ) {
// normal case
} else {
abort();
AssertFatal(false, "received data in past: current is %lu, new reception: %lu!\n", b->lastReceivedTS, b->th.timestamp);
LOG_E(HW, "received data in past: current is %lu, new reception: %lu!\n", b->lastReceivedTS, b->th.timestamp);
b->trashingPacket=true;
}
pthread_mutex_lock(&Sockmutex);
......
......@@ -41,6 +41,7 @@
# include "f1ap_du_task.h"
# include "enb_app.h"
# include "openair2/LAYER2/MAC/mac_proto.h"
#include <executables/split_headers.h>
extern RAN_CONTEXT_t RC;
......@@ -50,25 +51,21 @@ int create_tasks(uint32_t enb_nb) {
int rc;
if (enb_nb == 0) return 0;
bool fs6Du=false;
if ( getenv("fs6") != NULL && strncasecmp( getenv("fs6"), "du", 2) == 0 )
fs6Du=true;
LOG_I(ENB_APP, "Creating ENB_APP eNB Task\n");
rc = itti_create_task (TASK_ENB_APP, eNB_app_task, NULL);
AssertFatal(rc >= 0, "Create task for eNB APP failed\n");
LOG_I(RRC,"Creating RRC eNB Task\n");
rc = itti_create_task (TASK_RRC_ENB, rrc_enb_task, NULL);
AssertFatal(rc >= 0, "Create task for RRC eNB failed\n");
// No more rrc thread, as many race conditions are hidden behind
rrc_enb_init();
itti_mark_task_ready(TASK_RRC_ENB);
if (EPC_MODE_ENABLED && !fs6Du ) {
if (EPC_MODE_ENABLED && ! ( split73==SPLIT73_DU ) ) {
rc = itti_create_task(TASK_SCTP, sctp_eNB_task, NULL);
AssertFatal(rc >= 0, "Create task for SCTP failed\n");
}
if (EPC_MODE_ENABLED && !NODE_IS_DU(type) && !fs6Du ) {
if (EPC_MODE_ENABLED && !NODE_IS_DU(type) && ! ( split73==SPLIT73_DU ) ) {
rc = itti_create_task(TASK_S1AP, s1ap_eNB_task, NULL);
AssertFatal(rc >= 0, "Create task for S1AP failed\n");
if (!(get_softmodem_params()->emulate_rf)){
......
......@@ -93,6 +93,7 @@ unsigned short config_frames[4] = {2,9,11,13};
#include "lte-softmodem.h"
#include "NB_IoT_interface.h"
#include <executables/split_headers.h>
pthread_cond_t nfapi_sync_cond;
......@@ -152,6 +153,13 @@ int otg_enabled;
uint64_t num_missed_slots=0; // counter for the number of missed slots
int split73=0;
void sendFs6Ul(PHY_VARS_eNB *eNB, int UE_id, int harq_pid, int segmentID, int16_t *data, int dataLen, int r_offset) {
AssertFatal(false, "Must not be called in this context\n");
}
void sendFs6Ulharq(enum pckType type, int UEid, PHY_VARS_eNB *eNB, LTE_eNB_UCI *uci, int frame, int subframe, uint8_t *harq_ack, uint8_t tdd_mapping_mode, uint16_t tdd_multiplexing_mask, uint16_t rnti, int32_t stat) {
AssertFatal(false, "Must not be called in this context\n");
}
extern void reset_opp_meas(void);
extern void print_opp_meas(void);
......@@ -438,12 +446,9 @@ int restart_L1L2(module_id_t enb_id) {
init_UE_list(&RC.mac[enb_id]->UE_list);
LOG_I(ENB_APP, "attempting to create ITTI tasks\n");
if (itti_create_task (TASK_RRC_ENB, rrc_enb_task, NULL) < 0) {
LOG_E(RRC, "Create task for RRC eNB failed\n");
return -1;
} else {
LOG_I(RRC, "Re-created task for RRC eNB successfully\n");
}
// No more rrc thread, as many race conditions are hidden behind
rrc_enb_init();
itti_mark_task_ready(TASK_RRC_ENB);
/* pass a reconfiguration request which will configure everything down to
* RC.eNB[i][j]->frame_parms, too */
......@@ -477,7 +482,6 @@ void init_pdcp(void) {
pdcp_initmask = pdcp_initmask | ENB_NAS_USE_TUN_W_MBMS_BIT;
if ( getenv("fs6") != NULL && strncasecmp( getenv("fs6"), "du", 2) == 0 )
pdcp_module_init(pdcp_initmask);
if (NODE_IS_CU(RC.rrc[0]->node_type)) {
......@@ -643,12 +647,15 @@ int main ( int argc, char **argv )
for (int x=0; x < RC.nb_L1_inst; x++)
for (int CC_id=0; CC_id<RC.nb_L1_CC[x]; CC_id++) {
L1_rxtx_proc_t *L1proc= &RC.eNB[x][CC_id]->proc.L1_proc;
L1proc->threadPool=(tpool_t*)malloc(sizeof(tpool_t));
L1proc->respEncode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t));
L1proc->respDecode=(notifiedFIFO_t*) malloc(sizeof(notifiedFIFO_t));
if ( strlen(get_softmodem_params()->threadPoolConfig) > 0 )
initTpool(get_softmodem_params()->threadPoolConfig, &L1proc->threadPool, true);
initTpool(get_softmodem_params()->threadPoolConfig, L1proc->threadPool, true);
else
initTpool("n", &L1proc->threadPool, true);
initNotifiedFIFO(&L1proc->respEncode);
initNotifiedFIFO(&L1proc->respDecode);
initTpool("n", L1proc->threadPool, true);
initNotifiedFIFO(L1proc->respEncode);
initNotifiedFIFO(L1proc->respDecode);
}
......
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