Commit ac0dc9d3 authored by rmagueta's avatar rmagueta

Transmission of SIB1

parent 4f525854
dev 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA Fix_SA_SIB1 NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_DLUL_PF NR_DLUL_PF_4UL NR_DL_MIMO NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_initsync_fixes NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_RA_cleanup NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_itti_sim_wk48 NR_SA_w5GCN_new_gtpu NR_UE_CONFIG_REQ_FIXES NR_UE_PUCCH_bugfixes NR_UE_SA NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_UL_SCFDMA_100MHz NR_Wireshark NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_multiplexing_HARQ_CSI_PUCCH NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request3 PBCHNRTCFIX RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC add-dmrs-test add-ru-docker-image avxllr bandwidth-testing benetel_config_file_fix benetel_dpdk20 benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes bsr-fix bugfix-free-ra-process bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html ci-fix-module-ul-iperf ci-new-docker-pipeline ci-reduce-nb-vms ci_benetel_longrun_limits ci_benetel_test ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_phytest ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_vm_resource_fix debug-UL-5GRECORDS debug_UL_signal detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-aw2sori develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop-wf-du disable_CSI_measrep docker-improvements-2021-april docker-no-cache-option dongzhanyi-zte-develop1 enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development fedora-gen-kernel-fix fft_bench_hotfix fix-check fix-compile fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-quectel fix-realtime fix-retransmission-rbg fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_nr_ulsim fix_rb_corruption fix_reestablishment fixgtpu flexran-rtc-repo-is-public git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-bch-no-sched-sf-0 hack-exit-gnb-when-no-enb-nsa integ-w13-test-rt-issue integration_2020_wk15 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_w5GC_CBRA_test inter-RRU-final ldpc_offload_t1 lte-ulsch-bugfix migrate-cpp-check-container migrate-vm-pipeline-to-bionic msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-small-bugfixes nr-pdcp-srb-integrity nr-ra-fix nr-stats-print nrPBCHTCFix nrPbchTcFix nr_improve_chanest nr_power_measurement_fixes nr_ue_pdcp_fix nr_ul_scfdma oairu oairu-dockerfile-support phy-asan-fixes physim-build-deploy physim-deploy-handle-error-cases prb_based_dl_channel_estimation ptrs_rrc_config recursive-cmake rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins rh_ci_nsa_test_n310 rh_ci_phy_test_improve rh_ci_ra_fr2 rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_nsa_wk16 rh_ci_test_nsa_wk17_b rh_ci_test_nsa_wk17b rh_ci_test_rfsim_sa rh_ci_ue_parallel rohan_ulsim2RxFix s1_subnormal sanitize-address sanitize-v1 sanitize-v1-tmp sarma_pvnp_oai scs_60_iisc sim-channels small_nr_bugfixes t-gnb-tracer test-5GREC test-nsa-benetel test-panos test_nsa_gtpu_fix test_rt-fix_phy-test ue-dci-false-detection ue-fixes ue-pdsch-pusch-parallel ue-race-fix usrp_stop_cleanly usrp_x400 wf-sa-rrc wf_testc wireshark-T-hack-ueid wk11-with-phytest x2_handle_sctp_shutdown xw2 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 2021.w05 2021.w04 2021.w02 benetel_gnb_rel_2.0 benetel_gnb_rel_1.0 benetel_enb_rel_2.0 benetel_enb_rel_1.0
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......@@ -240,13 +240,7 @@ uint8_t nr_generate_dci_top(PHY_VARS_gNB *gNB,
} // m
} // reg_idx
printf("polar_encoder_fast: pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d] = %i, pdcch_pdu_rel15->dci_pdu.AggregationLevel[d] = %i, n_RNTI = %i\n",
pdcch_pdu_rel15->dci_pdu.PayloadSizeBits[d], pdcch_pdu_rel15->dci_pdu.AggregationLevel[d], n_RNTI);
printf("nr_pdcch_scrambling: encoded_length = %i, Nid = %i, scrambling_RNTI = %i\n\n",encoded_length, Nid, scrambling_RNTI);
printf("\n>> DCI: payloadSize = %d | payload = %llx\n\n",
printf(">> DCI: payloadSize = %d | payload = %llx\n\n",
*pdcch_pdu_rel15->dci_pdu.PayloadSizeBits,*(unsigned long long*)pdcch_pdu_rel15->dci_pdu.Payload);
} // for (int d=0;d<pdcch_pdu_rel15->numDlDci;d++)
......
......@@ -590,9 +590,18 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
// Fixme: correct type is unsigned, but nrLDPC_decoder and all called behind use signed int
if (check_crc((uint8_t*)llrProcBuf,length_dec,harq_process->F,crc_type)) {
LOG_D(PHY,"Segment %u CRC OK\n\033[0m",r);
if (r==0)
if (r==0) {
for (int i=0;i<10;i++) LOG_D(PHY,"byte %d : %x\n",i,((uint8_t*)llrProcBuf)[i]);
printf("\n");
printf("==== CRC OK ====\n");
for (int i=0;i<10;i++) printf("byte %d : %x\n",i,((uint8_t*)llrProcBuf)[i]);
printf("\n");
getchar();
}
//Temporary hack
no_iteration_ldpc = dlsch->max_ldpc_iterations;
ret = no_iteration_ldpc;
......@@ -600,6 +609,13 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
else {
LOG_D(PHY,"CRC NOK\n\033[0m");
ret = 1 + dlsch->max_ldpc_iterations;
printf("\n");
printf("==== CRC NOT OK ====\n");
for (int i=0;i<10;i++) printf("byte %d : %x\n",i,((uint8_t*)llrProcBuf)[i]);
printf("\n");
getchar();
}
......
......@@ -2234,8 +2234,13 @@ uint16_t nr_dci_size(NR_ServingCellConfigCommon_t *scc,
case NR_DL_DCI_FORMAT_1_0:
/// fixed: Format identifier 1, VRB2PRB 1, MCS 5, NDI 1, RV 2, HARQ PID 4, DAI 2, PUCCH TPC 2, PUCCH RInd 3, PDSCH to HARQ TInd 3 Time Domain assgnmt 4 -- 28
size += 28;
size = 28;
size += (uint8_t)ceil( log2( (N_RB*(N_RB+1))>>1 ) ); // Freq domain assignment
dci_pdu->frequency_domain_assignment.nbits = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
dci_pdu->time_domain_assignment.nbits = 4;
dci_pdu->vrb_to_prb_mapping.nbits = 1;
break;
case NR_DL_DCI_FORMAT_1_1:
......
......@@ -163,10 +163,8 @@ void config_dci_pdu(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_dci_dl_pdu_rel15_t
rel15->dci_length_options[i] = nr_dci_size(scc, mac->scg, def_dci_pdu_rel15, rel15->dci_format_options[i], NR_RNTI_SI, rel15->BWPSize, bwp_id);
}
printf("bwp_Common->genericParameters.locationAndBandwidth = %li\n", bwp_Common->genericParameters.locationAndBandwidth);
printf("rel15->BWPSize = %i\n", rel15->BWPSize);
break;
case NR_RNTI_SFI:
break;
case NR_RNTI_INT:
......@@ -253,23 +251,12 @@ void ue_dci_configuration(NR_UE_MAC_INST_t *mac, fapi_nr_dl_config_request_t *dl
}
}
}
/*if (pdcch_ConfigCommon->choice.setup->searchSpaceSIB1){
printf("*pdcch_ConfigCommon->choice.setup->searchSpaceSIB1 = %li\n", *pdcch_ConfigCommon->choice.setup->searchSpaceSIB1);
printf("ss->searchSpaceId = %li\n", ss->searchSpaceId);
// FIXME:
//if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->searchSpaceSIB1){
if (pdcch_ConfigCommon->choice.setup->searchSpaceSIB1){
if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->searchSpaceSIB1){
if( (frame%2 == mac->type0_PDCCH_CSS_config.sfn_c) && (slot == mac->type0_PDCCH_CSS_config.n_0) ){
rel15->num_dci_options = 1;
rel15->dci_format_options[0] = NR_DL_DCI_FORMAT_1_0;
config_dci_pdu(mac, rel15, dl_config, NR_RNTI_SI, ss_id);
fill_dci_search_candidates(ss, rel15);
// Configure monitoring of PDCCH candidates in Type0-PDCCH common search space on the MCG
LOG_W(MAC, "[DCI_CONFIG] This seach space should not be configured yet...");
}
}
}*/
if (pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation){
if (ss->searchSpaceId == *pdcch_ConfigCommon->choice.setup->searchSpaceOtherSystemInformation){
// Configure monitoring of PDCCH candidates in Type0-PDCCH common search space on the MCG
......
......@@ -204,12 +204,6 @@ int8_t mac_rrc_nr_data_req(const module_id_t Mod_idP,
/* TODO BCCH SIB1 SIBs */
if ((Srb_id & RAB_OFFSET ) == BCCH) {
// memcpy(&buffer_pP[0],
// RC.rrc[Mod_idP]->carrier[CC_id].SIB1_MBMS,
// RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB1_MBMS);
//
// return RC.rrc[Mod_idP]->carrier[CC_id].sizeof_SIB1_MBMS;
memcpy(&buffer_pP[0],
RC.nrrrc[Mod_idP]->carrier.SIB1,
RC.nrrrc[Mod_idP]->carrier.sizeof_SIB1);
......
......@@ -182,44 +182,22 @@ static void init_NR_SI(gNB_RRC_INST *rrc) {
LOG_D(RRC,"%s()\n\n\n\n",__FUNCTION__);
// MIB
rrc->carrier.MIB = (uint8_t *) malloc16(4);
rrc->carrier.sizeof_MIB = do_MIB_NR(rrc,0);
printf("rrc->carrier.sizeof_MIB = %i\n", rrc->carrier.sizeof_MIB);
// SIB 1
gNB_RrcConfigurationReq *configuration;
configuration = CALLOC(1,sizeof(gNB_RrcConfigurationReq));
configuration->cell_identity = 3;
configuration->ssb_SubcarrierOffset = rrc->carrier.ssb_SubcarrierOffset;
configuration->pdsch_AntennaPorts = rrc->carrier.pdsch_AntennaPorts;
configuration->pusch_TargetSNRx10 = rrc->carrier.pusch_TargetSNRx10;
configuration->pucch_TargetSNRx10 = rrc->carrier.pucch_TargetSNRx10;
configuration->scc = rrc->carrier.servingcellconfigcommon;
rrc->carrier.SIB1 = (uint8_t *) malloc16(100);
if(rrc->carrier.SIB1 == NULL) rrc->carrier.SIB1 = (uint8_t *) malloc16(100);
rrc->carrier.sizeof_SIB1 = do_SIB1_NR(&rrc->carrier, configuration);
printf("\n");
printf("rrc->carrier.sizeof_SIB1 = %i\n", rrc->carrier.sizeof_SIB1);
for(int i = 0; i<20; i++) {
printf("%i ", rrc->carrier.SIB1[i]);
}
printf("\n\n");
LOG_I(NR_RRC,"Done init_NR_SI\n");
rrc_mac_config_req_gNB(rrc->module_id,
rrc->carrier.ssb_SubcarrierOffset,
......
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