From d908779c388fafa787618e4d8fb9cfccbf0bb82e Mon Sep 17 00:00:00 2001 From: francescomani <email@francescomani.it> Date: Thu, 4 Aug 2022 11:34:25 +0200 Subject: [PATCH] lowercase bwp --- openair1/SIMULATION/NR_PHY/dlsim.c | 12 +- openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c | 66 +++++----- .../LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c | 42 +++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c | 34 ++--- .../NR_MAC_gNB/gNB_scheduler_primitives.c | 120 ++++++++---------- .../LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c | 39 +++--- .../LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c | 38 +++--- openair2/LAYER2/NR_MAC_gNB/mac_proto.h | 10 +- 8 files changed, 176 insertions(+), 185 deletions(-) diff --git a/openair1/SIMULATION/NR_PHY/dlsim.c b/openair1/SIMULATION/NR_PHY/dlsim.c index e2449d21da..0fe5315d4e 100644 --- a/openair1/SIMULATION/NR_PHY/dlsim.c +++ b/openair1/SIMULATION/NR_PHY/dlsim.c @@ -280,7 +280,7 @@ void nr_dlsim_preprocessor(module_id_t module_id, NR_UE_info_t *UE_info = RC.nrmac[module_id]->UE_info.list[0]; AssertFatal(RC.nrmac[module_id]->UE_info.list[1]==NULL, "can have only a single UE\n"); NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl; - NR_UE_DL_BWP_t *BWP = &UE_info->current_DL_BWP; + NR_UE_DL_BWP_t *current_BWP = &UE_info->current_DL_BWP; NR_ServingCellConfigCommon_t *scc = RC.nrmac[0]->common_channels[0].ServingCellConfigCommon; uint8_t nr_of_candidates = 0; @@ -307,7 +307,7 @@ void nr_dlsim_preprocessor(module_id_t module_id, NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static; - nr_set_pdsch_semi_static(BWP, + nr_set_pdsch_semi_static(current_BWP, scc, /* tda = */ 0, g_nrOfLayers, @@ -320,10 +320,10 @@ void nr_dlsim_preprocessor(module_id_t module_id, sched_pdsch->mcs = g_mcsIndex; /* the following might override the table that is mandated by RRC * configuration */ - BWP->mcsTableIdx = g_mcsTableIdx; + current_BWP->mcsTableIdx = g_mcsTableIdx; - sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx); - sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx); + sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx); + sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx); sched_pdsch->tb_size = nr_compute_tbs(sched_pdsch->Qm, sched_pdsch->R, sched_pdsch->rbSize, @@ -351,7 +351,7 @@ void nr_dlsim_preprocessor(module_id_t module_id, AssertFatal(sched_pdsch->rbStart >= 0, "invalid rbStart %d\n", sched_pdsch->rbStart); AssertFatal(sched_pdsch->rbSize > 0, "invalid rbSize %d\n", sched_pdsch->rbSize); AssertFatal(sched_pdsch->mcs >= 0, "invalid mcs %d\n", sched_pdsch->mcs); - AssertFatal(BWP->mcsTableIdx >= 0 && BWP->mcsTableIdx <= 2, "invalid mcsTableIdx %d\n", BWP->mcsTableIdx); + AssertFatal(current_BWP->mcsTableIdx >= 0 && current_BWP->mcsTableIdx <= 2, "invalid mcsTableIdx %d\n", current_BWP->mcsTableIdx); } typedef struct { diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c index cafa2c02d9..745fc1ae2b 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c @@ -694,10 +694,10 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - NR_UE_UL_BWP_t *UL_BWP = &ra->UL_BWP; + NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP; - NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = UL_BWP->tdaList; - int mu = UL_BWP->scs; + NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = ul_bwp->tdaList; + int mu = ul_bwp->scs; uint8_t K2 = *pusch_TimeDomainAllocationList->list.array[ra->Msg3_tda_id]->k2; const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]); const int sched_slot = (slot + K2) % nr_slots_per_frame[mu]; @@ -841,7 +841,7 @@ void nr_generate_Msg3_retransmission(module_id_t module_idP, int CC_id, frame_t NR_UL_DCI_FORMAT_0_0, NR_RNTI_TC, pusch_pdu->bwp_size, - UL_BWP->bwp_id, + ul_bwp->bwp_id, coreset, nr_mac->cset0_bwp_size); @@ -878,16 +878,16 @@ void nr_get_Msg3alloc(module_id_t module_id, uint16_t msg3_nb_rb = 8; // sdu has 6 or 8 bytes frame_type_t frame_type = RC.nrmac[module_id]->common_channels->frame_type; - NR_UE_UL_BWP_t *UL_BWP = &ra->UL_BWP; + NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP; - int mu = UL_BWP->scs; + int mu = ul_bwp->scs; int StartSymbolIndex = 0; int NrOfSymbols = 0; int startSymbolAndLength = 0; int temp_slot = 0; ra->Msg3_tda_id = 16; // initialization to a value above limit - NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = UL_BWP->tdaList; + NR_PUSCH_TimeDomainResourceAllocationList_t *pusch_TimeDomainAllocationList = ul_bwp->tdaList; const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL; const int n_slots_frame = nr_slots_per_frame[mu]; @@ -951,9 +951,9 @@ void nr_get_Msg3alloc(module_id_t module_id, int bwpSize = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); int bwpStart = NRRIV2PRBOFFSET(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); - if (bwpSize != UL_BWP->BWPSize || bwpStart != UL_BWP->BWPStart) { - int act_bwp_start = UL_BWP->BWPStart; - int act_bwp_size = UL_BWP->BWPSize; + if (bwpSize != ul_bwp->BWPSize || bwpStart != ul_bwp->BWPStart) { + int act_bwp_start = ul_bwp->BWPStart; + int act_bwp_size = ul_bwp->BWPSize; if (!((bwpStart >= act_bwp_start) && ((bwpStart+bwpSize) <= (act_bwp_start+act_bwp_size)))) bwpStart = act_bwp_start; } @@ -1065,7 +1065,7 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t gNB_MAC_INST *mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &mac->common_channels[CC_id]; NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; - NR_UE_UL_BWP_t *UL_BWP = &ra->UL_BWP; + NR_UE_UL_BWP_t *ul_bwp = &ra->UL_BWP; if (ra->state == RA_IDLE) { LOG_W(NR_MAC,"RA is not active for RA %X. skipping msg3 scheduling\n", ra->rnti); @@ -1098,11 +1098,11 @@ void nr_add_msg3(module_id_t module_idP, int CC_id, frame_t frameP, sub_frame_t nfapi_nr_pusch_pdu_t *pusch_pdu = &future_ul_tti_req->pdus_list[future_ul_tti_req->n_pdus].pusch_pdu; memset(pusch_pdu, 0, sizeof(nfapi_nr_pusch_pdu_t)); - int ibwp_size = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); - int scs = UL_BWP->scs; - int fh = (UL_BWP->pusch_Config && UL_BWP->pusch_Config->frequencyHopping) ? 1 : 0; - int startSymbolAndLength = UL_BWP->tdaList->list.array[ra->Msg3_tda_id]->startSymbolAndLength; - int mappingtype = UL_BWP->tdaList->list.array[ra->Msg3_tda_id]->mappingType; + const int ibwp_size = NRRIV2BW(scc->uplinkConfigCommon->initialUplinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); + const int scs = ul_bwp->scs; + const int fh = (ul_bwp->pusch_Config && ul_bwp->pusch_Config->frequencyHopping) ? 1 : 0; + const int startSymbolAndLength = ul_bwp->tdaList->list.array[ra->Msg3_tda_id]->startSymbolAndLength; + const int mappingtype = ul_bwp->tdaList->list.array[ra->Msg3_tda_id]->mappingType; LOG_D(NR_MAC, "Frame %d, Slot %d Adding Msg3 UL Config Request for (%d,%d) : (%d,%d,%d) for rnti: %d\n", frameP, @@ -1131,7 +1131,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; - NR_UE_DL_BWP_t *DL_BWP = &ra->DL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &ra->DL_BWP; if ((ra->Msg2_frame == frameP) && (ra->Msg2_slot == slotP)) { @@ -1142,13 +1142,13 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra NR_ServingCellConfigCommon_t *scc = cc->ServingCellConfigCommon; NR_SearchSpace_t *ss = ra->ra_ss; - NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = DL_BWP->tdaList; + NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = dl_bwp->tdaList; long BWPStart = 0; long BWPSize = 0; NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL; if(*ss->controlResourceSetId!=0) { - BWPStart = DL_BWP->BWPStart; + BWPStart = dl_bwp->BWPStart; BWPSize = NRRIV2BW(scc->downlinkConfigCommon->initialDownlinkBWP->genericParameters.locationAndBandwidth, MAX_BWP_SIZE); } else { type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id]; @@ -1242,8 +1242,8 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra // information to data and is reset every slot. const int pduindex = nr_mac->pdu_index[CC_id]++; - NR_PDSCH_Config_t *pdsch_Config = DL_BWP->pdsch_Config; - uint8_t mcsTableIdx = DL_BWP->mcsTableIdx; + NR_PDSCH_Config_t *pdsch_Config = dl_bwp->pdsch_Config; + uint8_t mcsTableIdx = dl_bwp->mcsTableIdx; int dmrsConfigType=0; if (pdsch_Config && @@ -1257,7 +1257,7 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra pdsch_pdu_rel15->pduIndex = pduindex; pdsch_pdu_rel15->BWPSize = BWPSize; pdsch_pdu_rel15->BWPStart = BWPStart; - pdsch_pdu_rel15->SubcarrierSpacing = DL_BWP->scs; + pdsch_pdu_rel15->SubcarrierSpacing = dl_bwp->scs; pdsch_pdu_rel15->CyclicPrefix = 0; pdsch_pdu_rel15->NrOfCodewords = 1; pdsch_pdu_rel15->mcsTable[0] = mcsTableIdx; @@ -1370,13 +1370,13 @@ void nr_generate_Msg2(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra fill_dci_pdu_rel15(scc, ra->CellGroup, - DL_BWP, + dl_bwp, &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1], &dci_payload, NR_DL_DCI_FORMAT_1_0, NR_RNTI_RA, BWPSize, - DL_BWP->bwp_id, + dl_bwp->bwp_id, coreset, nr_mac->cset0_bwp_size); @@ -1422,7 +1422,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra gNB_MAC_INST *nr_mac = RC.nrmac[module_idP]; NR_COMMON_channels_t *cc = &nr_mac->common_channels[CC_id]; - NR_UE_DL_BWP_t *DL_BWP = &ra->DL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &ra->DL_BWP; if (ra->Msg4_frame == frameP && ra->Msg4_slot == slotP ) { @@ -1433,7 +1433,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra NR_SearchSpace_t *ss = ra->ra_ss; NR_ControlResourceSet_t *coreset = ra->coreset; - NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = DL_BWP->tdaList; + NR_PDSCH_TimeDomainResourceAllocationList_t *pdsch_TimeDomainAllocationList = dl_bwp->tdaList; AssertFatal(coreset!=NULL,"Coreset cannot be null for RA-Msg4\n"); @@ -1456,8 +1456,8 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra long BWPSize = 0; NR_Type0_PDCCH_CSS_config_t *type0_PDCCH_CSS_config = NULL; if(*ss->controlResourceSetId!=0) { - BWPStart = DL_BWP->BWPStart; - BWPSize = DL_BWP->BWPSize; + BWPStart = dl_bwp->BWPStart; + BWPSize = dl_bwp->BWPSize; } else { type0_PDCCH_CSS_config = &nr_mac->type0_PDCCH_CSS_config[ra->beam_id]; BWPStart = type0_PDCCH_CSS_config->cset_start_rb; @@ -1567,7 +1567,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra uint16_t N_DMRS_SLOT = get_num_dmrs(dlDmrsSymbPos); - NR_PDSCH_Config_t *pdsch_Config = DL_BWP->pdsch_Config; + NR_PDSCH_Config_t *pdsch_Config = dl_bwp->pdsch_Config; int dmrsConfigType=0; if (pdsch_Config && pdsch_Config->dmrs_DownlinkForPDSCH_MappingTypeA && @@ -1593,7 +1593,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra N_PRB_DMRS = nr_mac->sched_ctrlCommon->pdsch_semi_static.numDmrsCdmGrpsNoData * 4; } - uint8_t mcsTableIdx = DL_BWP->mcsTableIdx; + uint8_t mcsTableIdx = dl_bwp->mcsTableIdx; int rbStart = 0; int rbSize = 0; @@ -1669,7 +1669,7 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra pdsch_pdu_rel15->pduIndex = pduindex; pdsch_pdu_rel15->BWPSize = BWPSize; pdsch_pdu_rel15->BWPStart = BWPStart; - pdsch_pdu_rel15->SubcarrierSpacing = DL_BWP->scs; + pdsch_pdu_rel15->SubcarrierSpacing = dl_bwp->scs; pdsch_pdu_rel15->CyclicPrefix = 0; pdsch_pdu_rel15->NrOfCodewords = 1; int R = nr_get_code_rate_dl(mcsIndex,mcsTableIdx); @@ -1764,13 +1764,13 @@ void nr_generate_Msg4(module_id_t module_idP, int CC_id, frame_t frameP, sub_fra fill_dci_pdu_rel15(scc, ra->CellGroup, - DL_BWP, + dl_bwp, &pdcch_pdu_rel15->dci_pdu[pdcch_pdu_rel15->numDlDci - 1], &dci_payload, NR_DL_DCI_FORMAT_1_0, NR_RNTI_TC, pdsch_pdu_rel15->BWPSize, - DL_BWP->bwp_id, + dl_bwp->bwp_id, coreset, nr_mac->cset0_bwp_size); diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c index 3e80fd104b..6aee81fa67 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c @@ -388,8 +388,8 @@ bool allocate_dl_retransmission(module_id_t module_id, gNB_MAC_INST *nr_mac = RC.nrmac[module_id]; const NR_ServingCellConfigCommon_t *scc = nr_mac->common_channels->ServingCellConfigCommon; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP; - NR_UE_UL_BWP_t *UBWP = &UE->current_UL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; NR_sched_pdsch_t *retInfo = &sched_ctrl->harq_processes[current_harq_pid].sched_pdsch; NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static; @@ -404,7 +404,7 @@ bool allocate_dl_retransmission(module_id_t module_id, } const int coresetid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : BWP->BWPSize; + const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : dl_bwp->BWPSize; int rbStart = 0; // start wrt BWPstart int rbSize = 0; @@ -435,7 +435,7 @@ bool allocate_dl_retransmission(module_id_t module_id, /* check whether we need to switch the TDA allocation since the last * (re-)transmission */ if (ps->time_domain_allocation != tda) { - nr_set_pdsch_semi_static(BWP, + nr_set_pdsch_semi_static(dl_bwp, scc, tda, ps->nrOfLayers, @@ -447,7 +447,7 @@ bool allocate_dl_retransmission(module_id_t module_id, * that we have enough resources */ NR_pdsch_semi_static_t temp_ps = *ps; - nr_set_pdsch_semi_static(BWP, + nr_set_pdsch_semi_static(dl_bwp, scc, tda, ps->nrOfLayers, @@ -519,7 +519,7 @@ bool allocate_dl_retransmission(module_id_t module_id, /* Find PUCCH occasion: if it fails, undo CCE allocation (undoing PUCCH * allocation after CCE alloc fail would be more complex) */ - int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, UBWP->pucch_Config, CCEIndex); + int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex); const int alloc = nr_acknack_scheduling(module_id, UE, frame, slot, r_pucch, 0); if (alloc<0) { LOG_D(MAC, @@ -579,7 +579,7 @@ void pf_dl(module_id_t module_id, continue; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP; + NR_UE_DL_BWP_t *current_BWP = &UE->current_DL_BWP; if (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0) continue; @@ -619,15 +619,15 @@ void pf_dl(module_id_t module_id, /* Calculate coeff */ const NR_bler_options_t *bo = &mac->dl_bler; - const int max_mcs_table = BWP->mcsTableIdx == 1 ? 27 : 28; + const int max_mcs_table = current_BWP->mcsTableIdx == 1 ? 27 : 28; const int max_mcs = min(sched_ctrl->dl_max_mcs, max_mcs_table); if (bo->harq_round_max == 1) sched_pdsch->mcs = max_mcs; else sched_pdsch->mcs = get_mcs_from_bler(bo, stats, &sched_ctrl->dl_bler_stats, max_mcs, frame); UE->layers = set_dl_nrOfLayers(sched_ctrl); - const uint8_t Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx); - const uint16_t R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx); + const uint8_t Qm = nr_get_Qm_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx); + const uint16_t R = nr_get_code_rate_dl(sched_pdsch->mcs, current_BWP->mcsTableIdx); uint32_t tbs = nr_compute_tbs(Qm, R, 1, /* rbSize */ @@ -657,13 +657,13 @@ void pf_dl(module_id_t module_id, NR_UE_sched_ctrl_t *sched_ctrl = &iterator->UE->UE_sched_ctrl; const uint16_t rnti = iterator->UE->rnti; - NR_UE_DL_BWP_t *BWP = &iterator->UE->current_DL_BWP; - NR_UE_UL_BWP_t *UBWP = &iterator->UE->current_UL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &iterator->UE->current_DL_BWP; + NR_UE_UL_BWP_t *ul_bwp = &iterator->UE->current_UL_BWP; const int coresetid = sched_ctrl->coreset->controlResourceSetId; const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : - BWP->BWPSize; + dl_bwp->BWPSize; int rbStart = 0; // start wrt BWPstart if (sched_ctrl->available_dl_harq.head < 0) { @@ -703,7 +703,7 @@ void pf_dl(module_id_t module_id, /* Find PUCCH occasion: if it fails, undo CCE allocation (undoing PUCCH * allocation after CCE alloc fail would be more complex) */ - int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, UBWP->pucch_Config, CCEIndex); + int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, ul_bwp->pucch_Config, CCEIndex); const int alloc = nr_acknack_scheduling(module_id, iterator->UE, frame, slot, r_pucch, 0); if (alloc<0) { @@ -730,7 +730,7 @@ void pf_dl(module_id_t module_id, NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static; if (ps->nrOfLayers != iterator->UE->layers || ps->time_domain_allocation != tda ) { - nr_set_pdsch_semi_static(BWP, + nr_set_pdsch_semi_static(dl_bwp, scc, tda, iterator->UE->layers, @@ -749,8 +749,8 @@ void pf_dl(module_id_t module_id, while (rbStart + max_rbSize < bwpSize && (rballoc_mask[rbStart + max_rbSize] & slbitmap) == slbitmap) max_rbSize++; - sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx); - sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx); + sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, dl_bwp->mcsTableIdx); + sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, dl_bwp->mcsTableIdx); sched_pdsch->pucch_allocation = alloc; uint32_t TBS = 0; uint16_t rbSize; @@ -796,18 +796,18 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t /* This is temporary and it assumes all UEs have the same BWP and TDA*/ NR_UE_info_t *UE=UE_info->list[0]; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP; + NR_UE_DL_BWP_t *current_BWP = &UE->current_DL_BWP; const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot); int startSymbolIndex, nrOfSymbols; - const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = BWP->tdaList; + const struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList = current_BWP->tdaList; AssertFatal(tda < tdaList->list.count, "time_domain_allocation %d>=%d\n", tda, tdaList->list.count); const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength; SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols); const int coresetid = sched_ctrl->coreset->controlResourceSetId; - const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : BWP->BWPSize; - const uint16_t BWPStart = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_start : BWP->BWPStart; + const uint16_t bwpSize = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_size : current_BWP->BWPSize; + const uint16_t BWPStart = coresetid == 0 ? RC.nrmac[module_id]->cset0_bwp_start : current_BWP->BWPStart; const uint16_t slbitmap = SL_to_bitmap(startSymbolIndex, nrOfSymbols); uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c index 5926b61f4c..e474315de7 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c @@ -195,18 +195,18 @@ void nr_preprocessor_phytest(module_id_t module_id, NR_UE_info_t *UE = RC.nrmac[module_id]->UE_info.list[0]; NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; const int CC_id = 0; const int tda = get_dl_tda(RC.nrmac[module_id], scc, slot); NR_pdsch_semi_static_t *ps = &sched_ctrl->pdsch_semi_static; ps->nrOfLayers = target_dl_Nl; if (ps->time_domain_allocation != tda || ps->nrOfLayers != target_dl_Nl) - nr_set_pdsch_semi_static(BWP, scc, tda, target_dl_Nl,sched_ctrl , ps); + nr_set_pdsch_semi_static(dl_bwp, scc, tda, target_dl_Nl,sched_ctrl , ps); /* find largest unallocated chunk */ - const int bwpSize = BWP->BWPSize; - const int BWPStart = BWP->BWPStart; + const int bwpSize = dl_bwp->BWPSize; + const int BWPStart = dl_bwp->BWPStart; int rbStart = 0; int rbSize = 0; @@ -309,8 +309,8 @@ void nr_preprocessor_phytest(module_id_t module_id, sched_pdsch->rbSize = rbSize; sched_pdsch->mcs = target_dl_mcs; - sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, BWP->mcsTableIdx); - sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, BWP->mcsTableIdx); + sched_pdsch->Qm = nr_get_Qm_dl(sched_pdsch->mcs, dl_bwp->mcsTableIdx); + sched_pdsch->R = nr_get_code_rate_dl(sched_pdsch->mcs, dl_bwp->mcsTableIdx); sched_ctrl->dl_bler_stats.mcs = target_dl_mcs; /* for logging output */ sched_pdsch->tb_size = nr_compute_tbs(sched_pdsch->Qm, sched_pdsch->R, @@ -351,10 +351,10 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ const int CC_id = 0; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP; - const int mu = BWP->scs; + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; + const int mu = ul_bwp->scs; - const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList = BWP->tdaList; + const struct NR_PUSCH_TimeDomainResourceAllocationList *tdaList = ul_bwp->tdaList; const int temp_tda = get_ul_tda(nr_mac, scc, slot); if (temp_tda < 0) return false; @@ -362,7 +362,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ "time domain assignment %d >= %d\n", temp_tda, tdaList->list.count); - int K2 = get_K2(BWP->tdaList, temp_tda, mu); + int K2 = get_K2(ul_bwp->tdaList, temp_tda, mu); const int sched_frame = frame + (slot + K2 >= nr_slots_per_frame[mu]); const int sched_slot = (slot + K2) % nr_slots_per_frame[mu]; const int tda = get_ul_tda(nr_mac, scc, sched_slot); @@ -384,13 +384,13 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ NR_pusch_semi_static_t *ps = &sched_ctrl->pusch_semi_static; if (ps->time_domain_allocation != tda || ps->nrOfLayers != target_ul_Nl) - nr_set_pusch_semi_static(BWP, scc, tda, target_ul_Nl,ps); + nr_set_pusch_semi_static(ul_bwp, scc, tda, target_ul_Nl,ps); uint16_t rbStart = 0; uint16_t rbSize; - const int bw = BWP->BWPSize; - const int BWPStart = BWP->BWPStart; + const int bw = ul_bwp->BWPSize; + const int BWPStart = ul_bwp->BWPStart; if (target_ul_bw>bw) rbSize = bw; @@ -453,10 +453,10 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ /* Calculate TBS from MCS */ ps->nrOfLayers = target_ul_Nl; - sched_pusch->R = nr_get_code_rate_ul(mcs, BWP->mcs_table); - sched_pusch->Qm = nr_get_Qm_ul(mcs, BWP->mcs_table); - if (BWP->pusch_Config->tp_pi2BPSK - && ((BWP->mcs_table == 3 && mcs < 2) || (BWP->mcs_table == 4 && mcs < 6))) { + sched_pusch->R = nr_get_code_rate_ul(mcs, ul_bwp->mcs_table); + sched_pusch->Qm = nr_get_Qm_ul(mcs, ul_bwp->mcs_table); + if (ul_bwp->pusch_Config->tp_pi2BPSK + && ((ul_bwp->mcs_table == 3 && mcs < 2) || (ul_bwp->mcs_table == 4 && mcs < 6))) { sched_pusch->R >>= 1; sched_pusch->Qm <<= 1; } diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c index 1dafff4635..497546184f 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c @@ -508,7 +508,7 @@ bool nr_find_nb_rb(uint16_t Qm, return *tbs >= bytes && *nb_rb <= nb_rb_max; } -void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *BWP, +void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *dl_bwp, const NR_ServingCellConfigCommon_t *scc, int tda, uint8_t layers, @@ -517,11 +517,11 @@ void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *BWP, { bool reset_dmrs = false; - NR_PDSCH_Config_t *pdsch_Config = BWP->pdsch_Config; + NR_PDSCH_Config_t *pdsch_Config = dl_bwp->pdsch_Config; LOG_D(NR_MAC,"tda %d, ps->time_domain_allocation %d,layers %d, ps->nrOfLayers %d, pdsch_config %p\n",tda,ps->time_domain_allocation,layers,ps->nrOfLayers,pdsch_Config); reset_dmrs = true; ps->time_domain_allocation = tda; - NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList = BWP->tdaList; + NR_PDSCH_TimeDomainResourceAllocationList_t *tdaList = dl_bwp->tdaList; AssertFatal(tda < tdaList->list.count, "time_domain_allocation %d>=%d\n", tda, tdaList->list.count); ps->mapping_type = tdaList->list.array[tda]->mappingType; if (pdsch_Config) { @@ -535,7 +535,7 @@ void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *BWP, const int startSymbolAndLength = tdaList->list.array[tda]->startSymbolAndLength; SLIV2SL(startSymbolAndLength, &ps->startSymbolIndex, &ps->nrOfSymbols); - if (BWP->dci_format == NR_DL_DCI_FORMAT_1_0) { + if (dl_bwp->dci_format == NR_DL_DCI_FORMAT_1_0) { if (ps->nrOfSymbols == 2) ps->numDmrsCdmGrpsNoData = 1; else @@ -562,7 +562,7 @@ void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *BWP, LOG_D(NR_MAC,"Filling dmrs info, ps->N_PRB_DMRS %d, ps->dl_dmrs_symb_pos %x, ps->N_DMRS_SLOT %d\n",ps->N_PRB_DMRS,ps->dl_dmrs_symb_pos,ps->N_DMRS_SLOT); } -void nr_set_pusch_semi_static(const NR_UE_UL_BWP_t *BWP, +void nr_set_pusch_semi_static(const NR_UE_UL_BWP_t *ul_bwp, const NR_ServingCellConfigCommon_t *scc, int tda, uint8_t nrOfLayers, @@ -570,24 +570,24 @@ void nr_set_pusch_semi_static(const NR_UE_UL_BWP_t *BWP, ps->time_domain_allocation = tda; - const int startSymbolAndLength = BWP->tdaList->list.array[tda]->startSymbolAndLength; + const int startSymbolAndLength = ul_bwp->tdaList->list.array[tda]->startSymbolAndLength; SLIV2SL(startSymbolAndLength, &ps->startSymbolIndex, &ps->nrOfSymbols); ps->nrOfLayers = nrOfLayers; // TODO setting of cdm groups with no data to be redone for MIMO - if (BWP->transform_precoding || nrOfLayers<3) - ps->num_dmrs_cdm_grps_no_data = (BWP->dci_format == NR_UL_DCI_FORMAT_0_1) ? 1 : (ps->nrOfSymbols == 2 ? 1 : 2); + if (ul_bwp->transform_precoding || nrOfLayers<3) + ps->num_dmrs_cdm_grps_no_data = (ul_bwp->dci_format == NR_UL_DCI_FORMAT_0_1) ? 1 : (ps->nrOfSymbols == 2 ? 1 : 2); else ps->num_dmrs_cdm_grps_no_data = 2; /* DMRS calculations */ - ps->mapping_type = BWP->tdaList->list.array[tda]->mappingType; - ps->NR_DMRS_UplinkConfig = BWP->pusch_Config ? + ps->mapping_type = ul_bwp->tdaList->list.array[tda]->mappingType; + ps->NR_DMRS_UplinkConfig = ul_bwp->pusch_Config ? (ps->mapping_type == NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeA ? - BWP->pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup : - BWP->pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup) : NULL; + ul_bwp->pusch_Config->dmrs_UplinkForPUSCH_MappingTypeA->choice.setup : + ul_bwp->pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup) : NULL; ps->dmrs_config_type = ps->NR_DMRS_UplinkConfig ? ((ps->NR_DMRS_UplinkConfig->dmrs_Type == NULL ? 0 : 1)) : 0; const pusch_dmrs_AdditionalPosition_t additional_pos = ps->NR_DMRS_UplinkConfig ? (ps->NR_DMRS_UplinkConfig->dmrs_AdditionalPosition == NULL @@ -882,13 +882,13 @@ void config_uldci(const NR_SIB1_t *sib1, dci_pdu_rel15_t *dci_pdu_rel15, int time_domain_assignment, uint8_t tpc, - NR_UE_UL_BWP_t *UBWP) { + NR_UE_UL_BWP_t *ul_bwp) { - int bwp_id = UBWP->bwp_id; - nr_dci_format_t dci_format = UBWP->dci_format; + int bwp_id = ul_bwp->bwp_id; + nr_dci_format_t dci_format = ul_bwp->dci_format; dci_pdu_rel15->frequency_domain_assignment.val = - PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, UBWP->BWPSize); + PRBalloc_to_locationandbandwidth0(pusch_pdu->rb_size, pusch_pdu->rb_start, ul_bwp->BWPSize); dci_pdu_rel15->time_domain_assignment.val = time_domain_assignment; dci_pdu_rel15->frequency_hopping_flag.val = pusch_pdu->frequency_hopping; dci_pdu_rel15->mcs = pusch_pdu->mcs_index; @@ -896,7 +896,7 @@ void config_uldci(const NR_SIB1_t *sib1, dci_pdu_rel15->rv = pusch_pdu->pusch_data.rv_index; dci_pdu_rel15->harq_pid = pusch_pdu->pusch_data.harq_process_id; dci_pdu_rel15->tpc = tpc; - NR_PUSCH_Config_t *pusch_Config = UBWP->pusch_Config; + NR_PUSCH_Config_t *pusch_Config = ul_bwp->pusch_Config; if (pusch_Config) AssertFatal(pusch_Config->resourceAllocation == NR_PUSCH_Config__resourceAllocation_resourceAllocationType1, "Only frequency resource allocation type 1 is currently supported\n"); @@ -908,7 +908,7 @@ void config_uldci(const NR_SIB1_t *sib1, LOG_D(NR_MAC,"Configuring DCI Format 0_1\n"); dci_pdu_rel15->dai[0].val = 0; //TODO // bwp indicator as per table 7.3.1.1.2-1 in 38.212 - dci_pdu_rel15->bwp_indicator.val = UBWP->n_ul_bwp < 4 ? bwp_id : bwp_id - 1; + dci_pdu_rel15->bwp_indicator.val = ul_bwp->n_ul_bwp < 4 ? bwp_id : bwp_id - 1; // SRS resource indicator if (pusch_Config && pusch_Config->txConfig != NULL) { @@ -1027,7 +1027,7 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, NR_PUCCH_ResourceSet_t *pucchresset; NR_PUCCH_FormatConfig_t *pucchfmt; NR_PUCCH_ResourceId_t *resource_id = NULL; - NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP; + NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP; long *id0 = NULL; int n_list, n_set; @@ -1039,7 +1039,7 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, uint16_t O_uci = O_csi + O_ack; - NR_PUSCH_Config_t *pusch_Config = BWP->pusch_Config; + NR_PUSCH_Config_t *pusch_Config = current_BWP->pusch_Config; long *pusch_id = pusch_Config ? pusch_Config->dataScramblingIdentityPUSCH : NULL; @@ -1049,7 +1049,7 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, id0 = pusch_Config->dmrs_UplinkForPUSCH_MappingTypeB->choice.setup->transformPrecodingDisabled->scramblingID0; else id0 = scc->physCellId; - NR_PUCCH_ConfigCommon_t *pucch_ConfigCommon = BWP->pucch_ConfigCommon; + NR_PUCCH_ConfigCommon_t *pucch_ConfigCommon = current_BWP->pucch_ConfigCommon; // hop flags and hopping id are valid for any BWP switch (pucch_ConfigCommon->pucch_GroupHopping){ @@ -1077,12 +1077,12 @@ void nr_configure_pucch(nfapi_nr_pucch_pdu_t* pucch_pdu, else pucch_pdu->hopping_id = *scc->physCellId; - pucch_pdu->bwp_size = BWP->BWPSize; - pucch_pdu->bwp_start = BWP->BWPStart; - pucch_pdu->subcarrier_spacing = BWP->scs; - pucch_pdu->cyclic_prefix = (BWP->cyclicprefix==NULL) ? 0 : *BWP->cyclicprefix; + pucch_pdu->bwp_size = current_BWP->BWPSize; + pucch_pdu->bwp_start = current_BWP->BWPStart; + pucch_pdu->subcarrier_spacing = current_BWP->scs; + pucch_pdu->cyclic_prefix = (current_BWP->cyclicprefix==NULL) ? 0 : *current_BWP->cyclicprefix; - NR_PUCCH_Config_t *pucch_Config = BWP->pucch_Config; + NR_PUCCH_Config_t *pucch_Config = current_BWP->pucch_Config; if (r_pucch<0 || pucch_Config){ LOG_D(NR_MAC,"pucch_acknak: Filling dedicated configuration for PUCCH\n"); @@ -1281,14 +1281,14 @@ void set_r_pucch_parms(int rsetindex, } void prepare_dci(const NR_CellGroupConfig_t *CellGroup, - const NR_UE_DL_BWP_t *BWP, + const NR_UE_DL_BWP_t *current_BWP, const NR_ControlResourceSet_t *coreset, dci_pdu_rel15_t *dci_pdu_rel15, nr_dci_format_t format) { AssertFatal(CellGroup!=NULL,"CellGroup shouldn't be null here\n"); - const NR_PDSCH_Config_t *pdsch_Config = BWP ? BWP->pdsch_Config : NULL; + const NR_PDSCH_Config_t *pdsch_Config = current_BWP ? current_BWP->pdsch_Config : NULL; switch(format) { case NR_UL_DCI_FORMAT_0_1: @@ -1350,8 +1350,8 @@ void prepare_dci(const NR_CellGroupConfig_t *CellGroup, else dci_pdu_rel15->srs_request.val = 0; // CBGTI and CBGFI - if (BWP->pdsch_servingcellconfig && - BWP->pdsch_servingcellconfig->codeBlockGroupTransmission != NULL) + if (current_BWP->pdsch_servingcellconfig && + current_BWP->pdsch_servingcellconfig->codeBlockGroupTransmission != NULL) AssertFatal(1==0,"CBG transmission currently not supported\n"); break; default : @@ -1362,7 +1362,7 @@ void prepare_dci(const NR_CellGroupConfig_t *CellGroup, void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc, const NR_CellGroupConfig_t *CellGroup, - const NR_UE_DL_BWP_t *BWP, + const NR_UE_DL_BWP_t *current_BWP, nfapi_nr_dl_dci_pdu_t *pdcch_dci_pdu, dci_pdu_rel15_t *dci_pdu_rel15, int dci_format, @@ -1383,7 +1383,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc, pdcch_dci_pdu->PayloadSizeBits = dci_size; AssertFatal(dci_size <= 64, "DCI sizes above 64 bits not yet supported"); if (dci_format == NR_DL_DCI_FORMAT_1_1 || dci_format == NR_UL_DCI_FORMAT_0_1) - prepare_dci(CellGroup, BWP, coreset, dci_pdu_rel15, dci_format); + prepare_dci(CellGroup, current_BWP, coreset, dci_pdu_rel15, dci_format); /// Payload generation switch (dci_format) { @@ -2251,7 +2251,7 @@ void configure_UE_BWP(gNB_MAC_INST *nr_mac, if(ul_bwp->bwp_Id == UL_BWP->bwp_id) break; } - AssertFatal(ul_bwp!=NULL,"Couldn't find DLBWP corresponding to BWP ID %ld\n",UL_BWP->bwp_id); + AssertFatal(ul_bwp!=NULL,"Couldn't find ULBWP corresponding to BWP ID %ld\n",UL_BWP->bwp_id); } // selection of dedicated BWPs @@ -2447,23 +2447,15 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; memset(sched_ctrl, 0, sizeof(*sched_ctrl)); sched_ctrl->dl_max_mcs = 28; /* do not limit MCS for individual UEs */ - sched_ctrl->set_pmi = false; - sched_ctrl->ta_frame = 0; sched_ctrl->ta_update = 31; - sched_ctrl->ta_apply = false; - sched_ctrl->ul_rssi = 0; - sched_ctrl->pucch_consecutive_dtx_cnt = 0; - sched_ctrl->pusch_consecutive_dtx_cnt = 0; - sched_ctrl->ul_failure = 0; sched_ctrl->sched_srs.frame = -1; sched_ctrl->sched_srs.slot = -1; - sched_ctrl->sched_srs.srs_scheduled = false; // initialize UE BWP information - NR_UE_DL_BWP_t *DL_BWP = &UE->current_DL_BWP; - memset(DL_BWP, 0, sizeof(*DL_BWP)); - NR_UE_UL_BWP_t *UL_BWP = &UE->current_UL_BWP; - memset(UL_BWP, 0, sizeof(*UL_BWP)); + NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; + memset(dl_bwp, 0, sizeof(*dl_bwp)); + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; + memset(ul_bwp, 0, sizeof(*ul_bwp)); configure_UE_BWP(nr_mac, scc, sched_ctrl, NULL, UE); /* set illegal time domain allocation to force recomputation of all fields */ @@ -2473,13 +2465,13 @@ NR_UE_info_t *add_new_nr_ue(gNB_MAC_INST *nr_mac, rnti_t rntiP, NR_CellGroupConf /* Set default BWPs */ sched_ctrl->next_dl_bwp_id = -1; sched_ctrl->next_ul_bwp_id = -1; - AssertFatal(UL_BWP->n_ul_bwp <= NR_MAX_NUM_BWP, + AssertFatal(ul_bwp->n_ul_bwp <= NR_MAX_NUM_BWP, "uplinkBWP_ToAddModList has %d BWP!\n", - UL_BWP->n_ul_bwp); + ul_bwp->n_ul_bwp); /* get Number of HARQ processes for this UE */ // pdsch_servingcellconfig == NULL in SA -> will create default (8) number of HARQ processes - create_dl_harq_list(sched_ctrl, DL_BWP->pdsch_servingcellconfig); + create_dl_harq_list(sched_ctrl, dl_bwp->pdsch_servingcellconfig); // add all available UL HARQ processes for this UE // nb of ul harq processes not configurable create_nr_list(&sched_ctrl->available_ul_harq, 16); @@ -2671,12 +2663,12 @@ void nr_csirs_scheduling(int Mod_idP, continue; } - NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP; - NR_UE_UL_BWP_t *UBWP = &UE->current_UL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; - if (!UBWP->csi_MeasConfig) continue; + if (!ul_bwp->csi_MeasConfig) continue; - NR_CSI_MeasConfig_t *csi_measconfig = UBWP->csi_MeasConfig; + NR_CSI_MeasConfig_t *csi_measconfig = ul_bwp->csi_MeasConfig; if (csi_measconfig->nzp_CSI_RS_ResourceToAddModList != NULL) { @@ -2702,20 +2694,20 @@ void nr_csirs_scheduling(int Mod_idP, nfapi_nr_dl_tti_csi_rs_pdu_rel15_t *csirs_pdu_rel15 = &dl_tti_csirs_pdu->csi_rs_pdu.csi_rs_pdu_rel15; - csirs_pdu_rel15->subcarrier_spacing = BWP->scs; - if (BWP->cyclicprefix) - csirs_pdu_rel15->cyclic_prefix = *BWP->cyclicprefix; + csirs_pdu_rel15->subcarrier_spacing = dl_bwp->scs; + if (dl_bwp->cyclicprefix) + csirs_pdu_rel15->cyclic_prefix = *dl_bwp->cyclicprefix; else csirs_pdu_rel15->cyclic_prefix = 0; // According to last paragraph of TS 38.214 5.2.2.3.1 - if (resourceMapping.freqBand.startingRB < BWP->BWPStart) { - csirs_pdu_rel15->start_rb = BWP->BWPStart; + if (resourceMapping.freqBand.startingRB < dl_bwp->BWPStart) { + csirs_pdu_rel15->start_rb = dl_bwp->BWPStart; } else { csirs_pdu_rel15->start_rb = resourceMapping.freqBand.startingRB; } - if (resourceMapping.freqBand.nrofRBs > (BWP->BWPStart + BWP->BWPSize - csirs_pdu_rel15->start_rb)) { - csirs_pdu_rel15->nr_of_rbs = BWP->BWPStart + BWP->BWPSize - csirs_pdu_rel15->start_rb; + if (resourceMapping.freqBand.nrofRBs > (dl_bwp->BWPStart + dl_bwp->BWPSize - csirs_pdu_rel15->start_rb)) { + csirs_pdu_rel15->nr_of_rbs = dl_bwp->BWPStart + dl_bwp->BWPSize - csirs_pdu_rel15->start_rb; } else { csirs_pdu_rel15->nr_of_rbs = resourceMapping.freqBand.nrofRBs; } @@ -2942,23 +2934,23 @@ void schedule_nr_bwp_switch(module_id_t module_id, UE_iterator(UE_info->list, UE) { NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_DL_BWP_t *DLBWP = &UE->current_DL_BWP; - NR_UE_UL_BWP_t *ULBWP = &UE->current_UL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; if (sched_ctrl->rrc_processing_timer == 0 && UE->Msg4_ACKed && sched_ctrl->next_dl_bwp_id >= 0) { int schedule_bwp_switching = false; - if (DLBWP->bwp_id == 0) { + if (dl_bwp->bwp_id == 0) { // Switching from Initial BWP to Dedicated BWP if (sched_ctrl->next_dl_bwp_id > 0 && sched_ctrl->next_ul_bwp_id > 0) { schedule_bwp_switching = true; LOG_W(NR_MAC,"%4d.%2d UE %04x Schedule BWP switch from Initial DL BWP to %ld and from Initial UL BWP to %ld\n", frame, slot, UE->rnti, sched_ctrl->next_dl_bwp_id, sched_ctrl->next_ul_bwp_id); } - } else if (DLBWP->bwp_id != sched_ctrl->next_dl_bwp_id && ULBWP->bwp_id != sched_ctrl->next_ul_bwp_id) { + } else if (dl_bwp->bwp_id != sched_ctrl->next_dl_bwp_id && ul_bwp->bwp_id != sched_ctrl->next_ul_bwp_id) { // Switching between Dedicated BWPs schedule_bwp_switching = true; LOG_W(NR_MAC,"%4d.%2d UE %04x Schedule BWP switch from dl_bwp_id %ld to %ld and from ul_bwp_id %ld to %ld\n", - frame, slot, UE->rnti, DLBWP->bwp_id, sched_ctrl->next_dl_bwp_id, ULBWP->bwp_id, sched_ctrl->next_ul_bwp_id); + frame, slot, UE->rnti, dl_bwp->bwp_id, sched_ctrl->next_dl_bwp_id, ul_bwp->bwp_id, sched_ctrl->next_ul_bwp_id); } if (schedule_bwp_switching) { diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c index 7b1c2fe01d..9987feb558 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_uci.c @@ -165,16 +165,16 @@ void nr_csi_meas_reporting(int Mod_idP, UE_iterator(RC.nrmac[Mod_idP]->UE_info.list, UE ) { NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_UL_BWP_t *UL_BWP = &UE->current_UL_BWP; - const int n_slots_frame = nr_slots_per_frame[UL_BWP->scs]; + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; + const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; if ((sched_ctrl->rrc_processing_timer > 0) || (sched_ctrl->ul_failure==1 && get_softmodem_params()->phy_test==0)) { continue; } - const NR_CSI_MeasConfig_t *csi_measconfig = UL_BWP->csi_MeasConfig; + const NR_CSI_MeasConfig_t *csi_measconfig = ul_bwp->csi_MeasConfig; if (!csi_measconfig) continue; AssertFatal(csi_measconfig->csi_ReportConfigToAddModList->list.count > 0, "NO CSI report configuration available"); - NR_PUCCH_Config_t *pucch_Config = UL_BWP->pucch_Config; + NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config; for (int csi_report_id = 0; csi_report_id < csi_measconfig->csi_ReportConfigToAddModList->list.count; csi_report_id++){ NR_CSI_ReportConfig_t *csirep = csi_measconfig->csi_ReportConfigToAddModList->list.array[csi_report_id]; @@ -214,7 +214,7 @@ void nr_csi_meas_reporting(int Mod_idP, curr_pucch->resource_indicator = res_index; curr_pucch->csi_bits += nr_get_csi_bitlen(UE->csi_report_template, csi_report_id); - int bwp_start = UL_BWP->BWPStart; + int bwp_start = ul_bwp->BWPStart; // going through the list of PUCCH resources to find the one indexed by resource_id uint16_t *vrb_map_UL = &RC.nrmac[Mod_idP]->common_channels[0].vrb_map_UL[sched_slot * MAX_BWP_SIZE]; @@ -378,7 +378,7 @@ void tci_handling(NR_UE_info_t *UE, frame_t frame, slot_t slot) { int ssb_index[MAX_NUM_SSB] = {0}; int ssb_rsrp[MAX_NUM_SSB] = {0}; uint8_t idx = 0; - NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP; + NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; uint8_t nr_ssbri_cri = 0; @@ -388,8 +388,8 @@ void tci_handling(NR_UE_info_t *UE, frame_t frame, slot_t slot) { uint8_t i, j; //bwp indicator - int n_dl_bwp = BWP->n_dl_bwp; - const int bwp_id = BWP->bwp_id; + int n_dl_bwp = dl_bwp->n_dl_bwp; + const int bwp_id = dl_bwp->bwp_id; if (n_dl_bwp < 4) pdsch_bwp_id = bwp_id; else @@ -655,7 +655,6 @@ void evaluate_cqi_report(uint8_t *payload, long *cqi_Table){ NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_DL_BWP_t *BWP = &UE->current_DL_BWP; //TODO sub-band CQI report not yet implemented int cqi_bitlen = csi_report->csi_meas_bitlen.cqi_bitlen[ri]; @@ -679,7 +678,7 @@ void evaluate_cqi_report(uint8_t *payload, // TODO for wideband case and multiple TB const int cqi_idx = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.wb_cqi_1tb; - const int mcs_table = BWP->mcsTableIdx; + const int mcs_table = UE->current_DL_BWP.mcsTableIdx; const int cqi_table = sched_ctrl->CSI_report.cri_ri_li_pmi_cqi_report.cqi_table; sched_ctrl->dl_max_mcs = get_mcs_from_cqi(mcs_table, cqi_table, cqi_idx); } @@ -758,8 +757,8 @@ void extract_pucch_csi_report(NR_CSI_MeasConfig_t *csi_MeasConfig, uint16_t bitlen = uci_pdu->csi_part1.csi_part1_bit_len; NR_CSI_ReportConfig__reportQuantity_PR reportQuantity_type = NR_CSI_ReportConfig__reportQuantity_PR_NOTHING; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP; - const int n_slots_frame = nr_slots_per_frame[BWP->scs]; + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; + const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; int cumul_bits = 0; int r_index = -1; for (int csi_report_id = 0; csi_report_id < csi_MeasConfig->csi_ReportConfigToAddModList->list.count; csi_report_id++ ) { @@ -1043,8 +1042,8 @@ int nr_acknack_scheduling(int mod_id, const int CC_id = 0; const int minfbtime = RC.nrmac[mod_id]->minRXTXTIMEpdsch; const NR_ServingCellConfigCommon_t *scc = RC.nrmac[mod_id]->common_channels[CC_id].ServingCellConfigCommon; - const NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP; - const int n_slots_frame = nr_slots_per_frame[BWP->scs]; + const NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; + const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; const NR_TDD_UL_DL_Pattern_t *tdd = scc->tdd_UL_DL_ConfigurationCommon ? &scc->tdd_UL_DL_ConfigurationCommon->pattern1 : NULL; AssertFatal(tdd || RC.nrmac[mod_id]->common_channels[CC_id].frame_type == FDD, "Dynamic TDD not handled yet\n"); const int nr_slots_period = tdd ? n_slots_frame / get_nb_periods_per_frame(tdd->dl_UL_TransmissionPeriodicity) : n_slots_frame; @@ -1059,10 +1058,10 @@ int nr_acknack_scheduling(int mod_id, * later) * * each UE has dedicated PUCCH Format 0 resources, and we use index 0! */ NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_PUCCH_Config_t *pucch_Config = BWP->pucch_Config; + NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config; - int bwp_start = BWP->BWPStart; - int bwp_size = BWP->BWPSize; + int bwp_start = ul_bwp->BWPStart; + int bwp_size = ul_bwp->BWPSize; NR_sched_pucch_t *pucch = &sched_ctrl->sched_pucch[0]; LOG_D(NR_MAC, "In %s: %4d.%2d Trying to allocate pucch, current DAI %d\n", __FUNCTION__, frame, slot, pucch->dai_c); @@ -1308,10 +1307,10 @@ void nr_sr_reporting(gNB_MAC_INST *nrmac, frame_t SFN, sub_frame_t slot) UE_iterator(nrmac->UE_info.list, UE) { NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP; - const int n_slots_frame = nr_slots_per_frame[BWP->scs]; + NR_UE_UL_BWP_t *ul_bwp = &UE->current_UL_BWP; + const int n_slots_frame = nr_slots_per_frame[ul_bwp->scs]; if (sched_ctrl->ul_failure==1 || sched_ctrl->rrc_processing_timer>0) continue; - NR_PUCCH_Config_t *pucch_Config = BWP->pucch_Config; + NR_PUCCH_Config_t *pucch_Config = ul_bwp->pucch_Config; if (!pucch_Config || !pucch_Config->schedulingRequestResourceToAddModList) continue; diff --git a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c index 81d2e1e201..27af724c20 100644 --- a/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c +++ b/openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c @@ -1052,11 +1052,11 @@ void pf_ul(module_id_t module_id, LOG_D(NR_MAC,"pf_ul: preparing UL scheduling for UE %04x\n",UE->rnti); NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; - NR_UE_UL_BWP_t *BWP = &UE->current_UL_BWP; + NR_UE_UL_BWP_t *current_BWP = &UE->current_UL_BWP; int rbStart = 0; // wrt BWP start - const uint16_t bwpSize = BWP->BWPSize; + const uint16_t bwpSize = current_BWP->BWPSize; NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch; NR_pusch_semi_static_t *ps = &sched_ctrl->pusch_semi_static; const NR_mac_dir_stats_t *stats = &UE->mac_stats.ul; @@ -1149,7 +1149,7 @@ void pf_ul(module_id_t module_id, const int tda = get_ul_tda(nrmac, scc, sched_pusch->slot); if (ps->time_domain_allocation != tda || ps->nrOfLayers != nrOfLayers) { - nr_set_pusch_semi_static(BWP, + nr_set_pusch_semi_static(current_BWP, scc, tda, nrOfLayers, @@ -1176,7 +1176,7 @@ void pf_ul(module_id_t module_id, NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch; sched_pusch->mcs = min(nrmac->min_grant_mcs, sched_pusch->mcs); - update_ul_ue_R_Qm(sched_pusch, BWP->pusch_Config, BWP->mcs_table); + update_ul_ue_R_Qm(sched_pusch, current_BWP->pusch_Config, current_BWP->mcs_table); sched_pusch->rbStart = rbStart; sched_pusch->rbSize = min_rb; sched_pusch->tb_size = nr_compute_tbs(sched_pusch->Qm, @@ -1199,7 +1199,7 @@ void pf_ul(module_id_t module_id, /* Create UE_sched for UEs eligibale for new data transmission*/ /* Calculate coefficient*/ - const uint32_t tbs = ul_pf_tbs[BWP->mcs_table][sched_pusch->mcs]; + const uint32_t tbs = ul_pf_tbs[current_BWP->mcs_table][sched_pusch->mcs]; float coeff_ue = (float) tbs / UE->ul_thr_ue; LOG_D(NR_MAC,"rnti %04x b %d, ul_thr_ue %f, tbs %d, coeff_ue %f\n", UE->rnti, b, UE->ul_thr_ue, tbs, coeff_ue); @@ -1242,9 +1242,9 @@ void pf_ul(module_id_t module_id, } else LOG_D(NR_MAC, "%4d.%2d free CCE for UL DCI UE %04x\n",frame,slot, iterator->UE->rnti); - NR_UE_UL_BWP_t *BWP = &iterator->UE->current_UL_BWP; + NR_UE_UL_BWP_t *current_BWP = &iterator->UE->current_UL_BWP; - const uint16_t bwpSize = BWP->BWPSize; + const uint16_t bwpSize = current_BWP->BWPSize; NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch; NR_pusch_semi_static_t *ps = &sched_ctrl->pusch_semi_static; @@ -1256,13 +1256,13 @@ void pf_ul(module_id_t module_id, const int tda = get_ul_tda(nrmac, scc, sched_pusch->slot); if (ps->time_domain_allocation != tda || ps->nrOfLayers != nrOfLayers) { - nr_set_pusch_semi_static(BWP, + nr_set_pusch_semi_static(current_BWP, scc, tda, nrOfLayers, ps); } - update_ul_ue_R_Qm(sched_pusch, BWP->pusch_Config, BWP->mcs_table); + update_ul_ue_R_Qm(sched_pusch, current_BWP->pusch_Config, current_BWP->mcs_table); int rbStart = 0; const uint16_t slbitmap = SL_to_bitmap(ps->startSymbolIndex, ps->nrOfSymbols); @@ -1341,16 +1341,16 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t * TDAs yet). If the TDA is negative, it means that there is no UL slot to * schedule now (slot + k2 is not UL slot) */ NR_UE_sched_ctrl_t *sched_ctrl = &nr_mac->UE_info.list[0]->UE_sched_ctrl; - NR_UE_UL_BWP_t *BWP = &nr_mac->UE_info.list[0]->current_UL_BWP; - int mu = BWP->scs; + NR_UE_UL_BWP_t *current_BWP = &nr_mac->UE_info.list[0]->current_UL_BWP; + int mu = current_BWP->scs; const int temp_tda = get_ul_tda(nr_mac, scc, slot); - int K2 = get_K2(BWP->tdaList, temp_tda, mu); + int K2 = get_K2(current_BWP->tdaList, temp_tda, mu); const int sched_frame = (frame + (slot + K2 >= nr_slots_per_frame[mu])) & 1023; const int sched_slot = (slot + K2) % nr_slots_per_frame[mu]; const int tda = get_ul_tda(nr_mac, scc, sched_slot); if (tda < 0) return false; - DevAssert(K2 == get_K2(BWP->tdaList, tda, mu)); + DevAssert(K2 == get_K2(current_BWP->tdaList, tda, mu)); if (!is_xlsch_in_slot(nr_mac->ulsch_slot_bitmap[sched_slot / 64], sched_slot)) return false; @@ -1364,7 +1364,7 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t is_xlsch_in_slot(nr_mac->ulsch_slot_bitmap[sched_slot / 64], sched_slot); // FIXME: Avoid mixed slots for initialUplinkBWP - if (BWP->bwp_id==0 && is_mixed_slot) + if (current_BWP->bwp_id==0 && is_mixed_slot) return false; // Avoid slots with the SRS @@ -1379,9 +1379,9 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t sched_ctrl->sched_pusch.frame = sched_frame; UE_iterator(nr_mac->UE_info.list, UE2) { NR_UE_sched_ctrl_t *sched_ctrl = &UE2->UE_sched_ctrl; - AssertFatal(K2 == get_K2(BWP->tdaList, tda, mu), + AssertFatal(K2 == get_K2(current_BWP->tdaList, tda, mu), "Different K2, %d(UE%d) != %ld(UE%04x)\n", - K2, 0, get_K2(BWP->tdaList, tda, mu), UE2->rnti); + K2, 0, get_K2(current_BWP->tdaList, tda, mu), UE2->rnti); sched_ctrl->sched_pusch.slot = sched_slot; sched_ctrl->sched_pusch.frame = sched_frame; } @@ -1392,10 +1392,10 @@ bool nr_fr1_ulsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t uint16_t *vrb_map_UL = &RC.nrmac[module_id]->common_channels[CC_id].vrb_map_UL[sched_slot * MAX_BWP_SIZE]; - const uint16_t bwpSize = BWP->BWPSize; - const uint16_t bwpStart = BWP->BWPStart; + const uint16_t bwpSize = current_BWP->BWPSize; + const uint16_t bwpStart = current_BWP->BWPStart; - const int startSymbolAndLength = BWP->tdaList->list.array[tda]->startSymbolAndLength; + const int startSymbolAndLength = current_BWP->tdaList->list.array[tda]->startSymbolAndLength; int startSymbolIndex, nrOfSymbols; SLIV2SL(startSymbolAndLength, &startSymbolIndex, &nrOfSymbols); const uint16_t symb = SL_to_bitmap(startSymbolIndex, nrOfSymbols); diff --git a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h index b6149e9090..fe5affbf38 100644 --- a/openair2/LAYER2/NR_MAC_gNB/mac_proto.h +++ b/openair2/LAYER2/NR_MAC_gNB/mac_proto.h @@ -192,7 +192,7 @@ void config_uldci(const NR_SIB1_t *sib1, dci_pdu_rel15_t *dci_pdu_rel15, int time_domain_assignment, uint8_t tpc, - NR_UE_UL_BWP_t *BWP); + NR_UE_UL_BWP_t *ul_bwp); void nr_schedule_pucch(gNB_MAC_INST *nrmac, frame_t frameP, @@ -285,7 +285,7 @@ void fill_pdcch_vrb_map(gNB_MAC_INST *mac, void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc, const NR_CellGroupConfig_t *CellGroup, - const NR_UE_DL_BWP_t *BWP, + const NR_UE_DL_BWP_t *dl_bwp, nfapi_nr_dl_dci_pdu_t *pdcch_dci_pdu, dci_pdu_rel15_t *dci_pdu_rel15, int dci_formats, @@ -296,7 +296,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc, uint16_t cset0_bwp_size); void prepare_dci(const NR_CellGroupConfig_t *CellGroup, - const NR_UE_DL_BWP_t *BWP, + const NR_UE_DL_BWP_t *dl_bwp, const NR_ControlResourceSet_t *coreset, dci_pdu_rel15_t *dci_pdu_rel15, nr_dci_format_t format); @@ -325,14 +325,14 @@ long get_K2(NR_PUSCH_TimeDomainResourceAllocationList_t *tdaList, int time_domain_assignment, int mu); -void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *BWP, +void nr_set_pdsch_semi_static(const NR_UE_DL_BWP_t *dl_bwp, const NR_ServingCellConfigCommon_t *scc, int tda, uint8_t layers, NR_UE_sched_ctrl_t *sched_ctrl, NR_pdsch_semi_static_t *ps); -void nr_set_pusch_semi_static(const NR_UE_UL_BWP_t *BWP, +void nr_set_pusch_semi_static(const NR_UE_UL_BWP_t *ul_bwp, const NR_ServingCellConfigCommon_t *scc, int tda, uint8_t nrOfLayers, -- 2.26.2