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zzha zzha
OpenXG-RAN
Commits
c0aea206
Commit
c0aea206
authored
Dec 13, 2022
by
francescomani
Browse files
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fixes in RAR and DCI for initial BWP larger than 180PRBs
parent
a97dfedb
Changes
4
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Showing
4 changed files
with
20 additions
and
28 deletions
+20
-28
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+8
-3
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+2
-2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+7
-20
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+3
-3
No files found.
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
View file @
c0aea206
...
...
@@ -3158,10 +3158,15 @@ uint16_t nr_dci_size(const NR_BWP_DownlinkCommon_t *initialDownlinkBWP,
case
NR_UL_DCI_FORMAT_0_0
:
/// fixed: Format identifier 1, Hop flag 1, MCS 5, NDI 1, RV 2, HARQ PID 4, PUSCH TPC 2 Time Domain assgnmt 4 --20
size
+=
20
;
size
+=
(
uint8_t
)
ceil
(
log2
(
(
N_RB
*
(
N_RB
+
1
))
>>
1
)
);
// Freq domain assignment -- hopping scenario to be updated
dci_pdu
->
frequency_domain_assignment
.
nbits
=
(
uint8_t
)
ceil
(
log2
((
N_RB
*
(
N_RB
+
1
))
>>
1
));
// Freq domain assignment -- hopping scenario to be updated
size
+=
dci_pdu
->
frequency_domain_assignment
.
nbits
;
int
dci_10_size
=
nr_dci_size
(
initialDownlinkBWP
,
initialUplinkBWP
,
cg
,
dci_pdu
,
NR_DL_DCI_FORMAT_1_0
,
rnti_type
,
N_RB
,
bwp_id
,
coreset_id
,
cset0_bwp_size
);
AssertFatal
(
dci_10_size
>=
size
,
"NR_UL_DCI_FORMAT_0_0 size is bigger than NR_DL_DCI_FORMAT_1_0! 3GPP TS 38.212 Section 7.3.1.0: DCI size alignment is not fully implemented"
);
if
(
dci_10_size
>=
size
)
size
+=
dci_10_size
-
size
;
// Padding to match 1_0 size
else
{
dci_pdu
->
frequency_domain_assignment
.
nbits
-=
(
size
-
dci_10_size
);
size
=
dci_10_size
;
}
// UL/SUL indicator assumed to be 0
break
;
...
...
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @
c0aea206
...
...
@@ -3248,7 +3248,7 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
#endif
if
(
dci_pdu_rel15
->
format_indicator
==
1
)
return
1
;
// discard dci, format indicator not corresponding to dci_format
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB_UL
*
(
N_RB_UL
+
1
))
>>
1
)
)
;
fsize
=
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
;
pos
+=
fsize
;
dci_pdu_rel15
->
frequency_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
fsize
)
-
1
);
#ifdef DEBUG_EXTRACT_DCI
...
...
@@ -3312,7 +3312,7 @@ static uint8_t nr_extract_dci_info(NR_UE_MAC_INST_t *mac,
#endif
if
(
dci_pdu_rel15
->
format_indicator
==
1
)
return
1
;
// discard dci, format indicator not corresponding to dci_format
fsize
=
(
int
)
ceil
(
log2
(
(
N_RB_UL
*
(
N_RB_UL
+
1
))
>>
1
)
)
;
fsize
=
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
;
pos
+=
fsize
;
dci_pdu_rel15
->
frequency_domain_assignment
.
val
=
(
*
dci_pdu
>>
(
dci_size
-
pos
))
&
((
1
<<
fsize
)
-
1
);
#ifdef DEBUG_EXTRACT_DCI
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
View file @
c0aea206
...
...
@@ -1923,10 +1923,6 @@ void nr_fill_rar(uint8_t Mod_idP,
NR_RA_HEADER_RAPID
*
rarh
=
(
NR_RA_HEADER_RAPID
*
)
(
dlsch_buffer
+
1
);
NR_MAC_RAR
*
rar
=
(
NR_MAC_RAR
*
)
(
dlsch_buffer
+
2
);
unsigned
char
csi_req
=
0
,
tpc_command
;
//uint8_t N_UL_Hop;
uint8_t
valid_bits
;
uint32_t
ul_grant
;
uint16_t
f_alloc
,
prb_alloc
,
bwp_size
,
truncation
=
0
;
tpc_command
=
3
;
// this is 0 dB
...
...
@@ -1962,24 +1958,15 @@ void nr_fill_rar(uint8_t Mod_idP,
ra
->
msg3_TPC
=
tpc_command
;
bwp_size
=
pusch_pdu
->
bwp_size
;
prb_alloc
=
PRBalloc_to_locationandbandwidth0
(
ra
->
msg3_nb_rb
,
ra
->
msg3_first_rb
,
bwp_size
);
if
(
bwp_size
>
180
)
{
AssertFatal
(
1
==
0
,
"Initial UBWP larger than 180 currently not supported"
);
}
else
{
valid_bits
=
(
uint8_t
)
ceil
(
log2
(
bwp_size
*
(
bwp_size
+
1
)
>>
1
));
}
if
(
pusch_pdu
->
frequency_hopping
){
if
(
pusch_pdu
->
frequency_hopping
)
AssertFatal
(
1
==
0
,
"PUSCH with frequency hopping currently not supported"
);
}
else
{
for
(
int
i
=
0
;
i
<
valid_bits
;
i
++
)
truncation
|=
(
1
<<
i
);
f_alloc
=
(
prb_alloc
&
truncation
);
}
ul_grant
=
csi_req
|
(
tpc_command
<<
1
)
|
(
pusch_pdu
->
mcs_index
<<
4
)
|
(
ra
->
Msg3_tda_id
<<
8
)
|
(
f_alloc
<<
12
)
|
(
pusch_pdu
->
frequency_hopping
<<
26
);
int
bwp_size
=
pusch_pdu
->
bwp_size
;
int
prb_alloc
=
PRBalloc_to_locationandbandwidth0
(
ra
->
msg3_nb_rb
,
ra
->
msg3_first_rb
,
bwp_size
);
int
valid_bits
=
14
;
int
f_alloc
=
prb_alloc
&
((
1
<<
valid_bits
)
-
1
);
uint32_t
ul_grant
=
csi_req
|
(
tpc_command
<<
1
)
|
(
pusch_pdu
->
mcs_index
<<
4
)
|
(
ra
->
Msg3_tda_id
<<
8
)
|
(
f_alloc
<<
12
)
|
(
pusch_pdu
->
frequency_hopping
<<
26
);
rar
->
UL_GRANT_1
=
(
uint8_t
)
(
ul_grant
>>
24
)
&
0x07
;
rar
->
UL_GRANT_2
=
(
uint8_t
)
(
ul_grant
>>
16
)
&
0xff
;
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
c0aea206
...
...
@@ -1670,7 +1670,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
pos
=
1
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
format_indicator
&
1
)
<<
(
dci_size
-
pos
);
// Freq domain assignment max 16 bit
fsize
=
(
int
)
ceil
(
log2
((
N_RB
*
(
N_RB
+
1
))
>>
1
))
;
fsize
=
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
;
pos
+=
fsize
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
frequency_domain_assignment
.
val
&
((
1
<<
fsize
)
-
1
))
<<
(
dci_size
-
pos
);
// Time domain assignment 4bit
...
...
@@ -1695,7 +1695,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
pos
+=
2
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
tpc
&
0x3
)
<<
(
dci_size
-
pos
);
// Padding bits
for
(
int
a
=
pos
;
a
<
32
;
a
++
)
for
(
int
a
=
pos
;
a
<
dci_size
;
a
++
)
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
padding
&
1
)
<<
(
dci_size
-
pos
++
);
// UL/SUL indicator – 1 bit
/* commented for now (RK): need to get this from BWP descriptor
...
...
@@ -1723,7 +1723,7 @@ void fill_dci_pdu_rel15(const NR_ServingCellConfigCommon_t *scc,
pos
=
1
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
format_indicator
&
1
)
<<
(
dci_size
-
pos
);
// Freq domain assignment max 16 bit
fsize
=
(
int
)
ceil
(
log2
((
N_RB
*
(
N_RB
+
1
))
>>
1
))
;
fsize
=
dci_pdu_rel15
->
frequency_domain_assignment
.
nbits
;
pos
+=
fsize
;
*
dci_pdu
|=
((
uint64_t
)
dci_pdu_rel15
->
frequency_domain_assignment
.
val
&
((
1
<<
fsize
)
-
1
))
<<
(
dci_size
-
pos
);
// Time domain assignment 4bit
...
...
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