syntax = "proto2";
package protocol;

//
// Message containing the DL DCI info
//

message flex_dl_dci {
	optional uint32 rnti = 1;
	optional uint32 res_alloc = 2;		// Type of resource allocation
	optional uint32 rb_bitmap = 3;		// Bitmap for RB allocation
	optional uint32 rb_shift = 4;		// See TS 36.214, section 7.1.6.2
	repeated uint32 tbs_size = 5;		// The size of each TBS
	repeated uint32 mcs = 6;   		// The MCS of each TB
	repeated uint32 ndi = 7;		// New data indicator of each TB
	repeated uint32 rv = 8;			// Redundancy version of each TB
	optional uint32 cce_index = 9;		// CCE index used to send the DCI
	optional uint32 aggr_level = 10;
	optional uint32 precoding_info = 11;	// 2 antenna ports:0..6,
		 			 	// 4 antenna ports:0..50
	optional uint32 format = 12;		// DCI format. A FLDCIF_* value
	optional uint32 tpc = 13;		// TS 36.213, sec 5.1.1.1
	optional uint32 harq_process = 14; 	// HARQ process ID
	optional uint32 dai = 15;      		// TDD only
	optional uint32 vrb_format = 16; 	// One of the FLVRBF_* values
	optional uint32 tb_swap = 17;	 	// Boolean. TB to codeword swap flag
	optional uint32 sps_release = 18;   	// Flag value
	optional uint32 pdcch_order = 19;
	optional uint32 preamble_index = 20;	// Only valid if pdcch_order = 1
	optional uint32 prach_mask_index = 21;	// Only valid if pdcch_order = 1
	optional uint32 n_gap = 22;	   	// One of the FLNGV_* values
	optional uint32 tbs_idx = 23;		// The TBS index for Format 1A
	optional uint32 dl_power_offset = 24;	// For format 1D
	optional uint32 pdcch_power_offset = 25; // DL PDCCH power boosting in dB
	optional uint32 cif_present = 26;    	// Boolean. Indication of CIF field
	optional uint32 cif = 27;     		// CIF for cross-carrier scheduling
}

message flex_ul_dci {
        optional uint32 rnti = 1;
        optional uint32 rb_start = 2;           // The start RB allocated to the UE 
        optional uint32 rb_len = 3;             // The number of RBs allocated to the UE
        optional uint32 mcs = 4;                // Modulation and coding scheme
        optional uint32 cyclic_shift2 = 5;      //  match DCI format 0/4 PDU 
        optional uint32 freq_hop_flag = 6;      // 0 no hopping, 1 hoppping
        optional uint32 freq_hop_map = 7;       // Frequency hopping bits (0..4) 
        optional uint32 ndi = 8;                // New data indicator
        optional uint32 rv = 9;                 // Redundancy version
        optional uint32 harq_pid = 10;          //  The harq process id
        optional uint32 ultx_mode = 11;         //  A FLULM_* value
        optional uint32 tbs_size = 12;          // The size of each TBS
        optional uint32 n_srs = 13;             // Overlap indication with srs
        optional uint32 res_alloc = 14;         // Type of resource allocation
        optional uint32 size = 15;    // Size of the ULSCH PDU in bytes for UL Grant.

        optional uint32 dai = 16;               // TDD only

//      optional uint32 tb_swap = 17;           // Boolean. TB to codeword swap flag

//      optional uint32 pdcch_order = 19;
//      optional uint32 preamble_index = 20;    // Only valid if pdcch_order = 1
//      optional uint32 prach_mask_index = 21;  // Only valid if pdcch_order = 1

//      optional uint32 tbs_idx = 23;           // The TBS index for Format 1A




}


//
// Messages related to the creation of RLC PDUs
//

message flex_rlc_pdu {
	repeated flex_rlc_pdu_tb rlc_pdu_tb = 1; // list of parameters for the creation of RLC PDUs. One for each TB
}

message flex_rlc_pdu_tb {
	optional uint32 logical_channel_id = 1;
	optional uint32 size = 2;	   // Maximum RLC PDU to be created in bytes
}

//
// MAC content types related enums
//

enum flex_dci_format {
     FLDCIF_1 = 0;
     FLDCIF_1A = 1;
     FLDCIF_1B = 2;
     FLDCIF_1C = 3;
     FLDCIF_1D = 4;
     FLDCIF_2 = 5;
     FLDCIF_2A = 6;
     FLDCIF_2B = 7;
     FLDCIF_3 = 8;
     FLDCIF_3A = 9;
}

enum flex_vrb_format {
     FLVRBF_LOCALIZED = 0;
     FLVRBF_DISTRIBUTED = 1;
}

enum flex_ngap_val {
     FLNGV_1 = 0;
     FLNGV_2 = 1;
}
