Commit c35ab1a2 authored by ISIP CS/NCTU's avatar ISIP CS/NCTU

add 1_0 rnti and test pdu bit

parent 23dbc2ad
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2024.w06 2024.w05 2024.w04 2024.w03 2024.w02 2024.w01 2023.w51 2023.w50 2023.w49 2023.w48 2023.w47 2023.w45 2023.w43 2023.w42 2023.w41 2023.w40 2023.w39 2023.w38 2023.w37 2023.w36 2023.w34 2023.w33 2023.w32 2023.w31 2023.w30 2023.w29 2023.w28 2023.w27 2023.w26 2023.w25 2023.w24 2023.w23 2023.w22 2023.w21 2023.w20 2023.w19 2023.w18 2023.w18b 2023.w16 2023.w15 2023.w14 2023.w13 2023.w12 2023.w11 2023.w11b 2023.w10 2023.w10b 2023.w09 2023.w08 2023.w08b 2023.w07 2023.w06 2023.w05 2023.w03 2023.w02 2022.42 2022.41 2022.w51 2022.w50 2022.w49 2022.w48 2022.w47 2022.w46 2022.w45 2022.w43 2022.w42 2022.w42b 2022.w41 2022.w40 2022.w39 2022.w38 2022.w37 2022.w37b 2022.w36 2022.w35 2022.w33 2022.w32 2022.w31 2022.w31b 2022.w30 2022.w29 2022.w26 2022.w25 2022.w24 2022.w24b 2022.w23 2022.w22 2022.w21 2022.w20 2022.w19 2022.w18 2022.w17 2022.w15 2022.w15b 2022.w14a 2022.w13 2022.w13b 2022.w13a 2022.w12 2022.w10 2022.w09 2022.w09b 2022.w08 2022.w08b 2022.w07 2022.w07b 2022.w06 2022.w06a 2022.w05 2022.w05b 2022.w03_hotfix 2022.w03_b 2022.w02 2022.w01 2021.wk46 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w51_c 2021.w51_a 2021.w50_a 2021.w49_b 2021.w49_a 2021.w48 2021.w47 2021.w46 2021.w46-powder 2021.w45 2021.w45_b 2021.w44 2021.w43 2021.w42 2021.w37 2021.w36 2021.w35 2021.w34 2021.w33 2021.w32 2021.w31 2021.w30 2021.w29 2021.w28 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 2021.w05 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 2020.w26 2020.w25 2020.w24 2020.w23 2020.w22 2020.w19 2020.w17 2020.w16 2020.w15 2020.w11 2020.w09 2020.w06 2020.w05 2020.w04 2020.w03 v2.1.0 v2.0.0 setparam osa-etsi-ws-ue osa-etsi-ws-try2 osa-etsi-ws-try1 osa-etsi-ws-gNB nr-ip-over-lte nr-ip-over-lte-v.1.5 nr-ip-over-lte-v.1.4 nr-ip-over-lte-v.1.3 nr-ip-over-lte-v.1.2 nr-ip-over-lte-v.1.1 nr-ip-over-lte-v.1.0 flexran-eol develop-nr-pdcch develop-nr-2020w03 develop-nr-2020w02 develop-nr-2019w51 develop-nr-2019w50 develop-nr-2019w48 develop-nr-2019w47 develop-nr-2019w45 develop-nr-2019w43 develop-nr-2019w42 develop-nr-2019w40 develop-nr-2019w28 develop-nr-2019w23 benetel_phase_rotation benetel_gnb_rel_2.0 benetel_gnb_rel_1.0 benetel_enb_rel_2.0 benetel_enb_rel_1.0
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......@@ -121,7 +121,8 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
nfapi_nr_config_request_t *cfg = &gNB->gNB_config;
uint16_t N_RB = fp->initial_bwp_dl.N_RB;
uint8_t fsize=0, pos=0, cand_idx=0;
uint16_t N_RB_UL = fp->initial_bwp_ul.N_RB;
uint8_t fsize=0, pos=0, pos2=0,cand_idx=0;
/// Payload generation
switch(params_rel15->dci_format) {
......@@ -131,6 +132,7 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
case NFAPI_NR_RNTI_RA:
// Freq domain assignment
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
printf("fsize = %d\n",fsize);
for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<pos++;
// Time domain assignment
......@@ -144,14 +146,375 @@ void nr_fill_dci_and_dlsch(PHY_VARS_gNB *gNB,
// TB scaling
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<pos++;
printf("***************************\n");
break;
case NFAPI_NR_RNTI_C:
// indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<pos++;
// Freq domain assignment (275rb >> fsize = 16)
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<pos++;
printf("fsize = %d\n",fsize);
printf("NFAPI_NR_RNTI_C\n");
if ((pdu_rel15->frequency_domain_assignment+1)&1 ==0) //fsize are all 1 38.212 p86
{
printf("***************************\n");
// ra_preamble_index 6bit
for (int i=0; i<6; i++)
*dci_pdu |= ((pdu_rel15->ra_preamble_index>>(5-i-1))&1)<<pos++;
// UL/SUL indicator 1bit
*dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<pos++;
// SS/PBCH index 6bit
for (int i=0; i<6; i++)
*dci_pdu |= ((pdu_rel15->ss_pbch_index>>(5-i))&1)<<pos++;
// prach_mask_index "2"+2bit // cause it 32bit and bit over 32 ,so dci_pdu ++
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->prach_mask_index>>(3-i))&1)<<pos++;
//--------------------------dci_pdu ++------------------------------
// prach_mask_index 2+"2"bit //
for (int i=2; i<4; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->prach_mask_index>>(3-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->prach_mask_index>>(3-i))&1)<<pos++;
}
} //end if
else
{
// Time domain assignment 4bit
for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<pos++;
// VRB to PRB mapping 1bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<pos++;
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<pos++;
// New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<pos++;
// Redundancy version 2bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<pos++;
// HARQ process number 4bit "2"+2
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
//--------------------------dci_pdu ++------------------------------
// HARQ process number 4bit 2+"2"
for (int i=2; i<4; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
}
// Downlink assignment index 2bit
for (int i=0; i<2; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->dai>>(1-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<pos++;
}
// TPC command for scheduled PUCCH 2bit
for (int i=0; i<2; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->tpc>>(1-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<pos++;
}
// PUCCH resource indicator 3bit
for (int i=0; i<3; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<pos++;
}
// PDSCH-to-HARQ_feedback timing indicator 3bit
for (int i=0; i<3; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<pos++;
}
} //end else
break;
case NFAPI_NR_RNTI_P:
// Short Messages Indicator – 2 bits
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->short_messages_indicator>>(1-i))&1)<<pos++;
// Short Messages – 8 bits
for (int i=0; i<8; i++)
*dci_pdu |= ((pdu_rel15->short_messages>>(7-i))&1)<<pos++;
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<pos++;
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<pos++;
// VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<pos++;
// MCS "1"+4 = 5 bit
for (int i=0; i<1; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<pos++;
// MCS 1+"4" = 5 bit
for (int i=1; i<4; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->mcs>>(4-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<pos++;
}
// TB scaling 2 bit
for (int i=0; i<2; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->tb_scaling>>(1-i))&1)<<pos++;
}
break;
case NFAPI_NR_RNTI_SI:
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<pos++;
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<pos++;
// VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<pos++;
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<pos++;
// Redundancy version 2bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<pos++;
break;
case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<pos++;
// Freq domain assignment 0-16 bit
fsize = (int)ceil( log2( (N_RB*(N_RB+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<pos++;
// Time domain assignment 4 bit
for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<pos++;
// VRB to PRB mapping 1 bit
*dci_pdu |= (pdu_rel15->vrb_to_prb_mapping&1)<<pos++;
// MCS 5bit //bit over 32, so dci_pdu ++
for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<pos++;
// New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<pos++;
// Redundancy version 2bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<pos++;
// HARQ process number 4bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
// HARQ process number 4bit
for (int i=2; i<4; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
}
// Downlink assignment index – 2 bits
for (int i=0; i<2; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->dai>>(1-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->dai>>(1-i))&1)<<pos++;
}
// TPC command for scheduled PUCCH – 2 bits
for (int i=0; i<2; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->tpc>>(1-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<pos++;
}
// PUCCH resource indicator – 3 bits
for (int i=0; i<3; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->pucch_resource_indicator>>(2-i))&1)<<pos++;
}
// PDSCH-to-HARQ_feedback timing indicator – 3 bits
for (int i=0; i<3; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->pdsch_to_harq_feedback_timing_indicator>>(2-i))&1)<<pos++;
}
///-----------------------------------?????????????????????------------------------
break;
}
break;
case NFAPI_NR_UL_DCI_FORMAT_0_0:
switch(params_rel15->rnti_type)
{
case NFAPI_NR_RNTI_C:
// indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<pos++;
// Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<pos++;
// Time domain assignment 4bit
for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<pos++;
// Frequency hopping flag – 1 bit
*dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<pos++;
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<pos++;
// New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<pos++;
// Redundancy version 2bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<pos++;
// HARQ process number 4bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
// HARQ process number 4bit
for (int i=2; i<4; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
}
// TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->tpc>>(1-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<pos++;
}
// Padding bits
if (pos<32)
{
for(int a = pos;a<32;a++)
*dci_pdu |= (pdu_rel15->padding&1)<<pos++;
}
// UL/SUL indicator – 1 bit
if (cfg->pucch_config.pucch_GroupHopping.value)
{
if (pos>31)
*(dci_pdu+1) |= (pdu_rel15->ul_sul_indicator&1)<<pos2++;
else
*dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<pos++;
}
break;
case NFAPI_NR_RNTI_TC:
// indicating a DL DCI format 1bit
*dci_pdu |= (pdu_rel15->format_indicator&1)<<pos++;
// Freq domain assignment max 16 bit
fsize = (int)ceil( log2( (N_RB_UL*(N_RB_UL+1))>>1 ) );
for (int i=0; i<fsize; i++)
*dci_pdu |= ((pdu_rel15->frequency_domain_assignment>>(fsize-i-1))&1)<<pos++;
// Time domain assignment 4bit
for (int i=0; i<4; i++)
*dci_pdu |= ((pdu_rel15->time_domain_assignment>>(3-i))&1)<<pos++;
// Frequency hopping flag – 1 bit
*dci_pdu |= (pdu_rel15->frequency_hopping_flag&1)<<pos++;
// MCS 5 bit
for (int i=0; i<5; i++)
*dci_pdu |= ((pdu_rel15->mcs>>(4-i))&1)<<pos++;
// New data indicator 1bit
*dci_pdu |= (pdu_rel15->ndi&1)<<pos++;
// Redundancy version 2bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->rv>>(1-i))&1)<<pos++;
// HARQ process number 4bit
for (int i=0; i<2; i++)
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
// HARQ process number 4bit
for (int i=2; i<4; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->harq_pid>>(3-i))&1)<<pos++;
}
// TPC command for scheduled PUSCH – 2 bits
for (int i=0; i<2; i++)
{
if (pos>31)
*(dci_pdu+1) |= ((pdu_rel15->tpc>>(1-i))&1)<<pos2++;
else
*dci_pdu |= ((pdu_rel15->tpc>>(1-i))&1)<<pos++;
}
// Padding bits
if (pos<32)
{
for(int a = pos;a<32;a++)
*dci_pdu |= (pdu_rel15->padding&1)<<pos++;
}
// UL/SUL indicator – 1 bit
if (cfg->pucch_config.pucch_GroupHopping.value)
{
if (pos>31)
*(dci_pdu+1) |= (pdu_rel15->ul_sul_indicator&1)<<pos2++;
else
*dci_pdu |= (pdu_rel15->ul_sul_indicator&1)<<pos++;
}
break;
}
break;
}
LOG_I(PHY, "DCI PDU: [0]->0x%08x \t [1]->0x%08x \t [2]->0x%08x \t [3]->0x%08x\n",
dci_pdu[0], dci_pdu[1], dci_pdu[2], dci_pdu[3]);
......
......@@ -71,10 +71,32 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
memcpy((void*)params_rel15, (void*)&gNB->pdcch_type0_params, sizeof(nfapi_nr_dl_config_pdcch_parameters_rel15_t));
pdu_rel15->frequency_domain_assignment = 5;
pdu_rel15->time_domain_assignment = 2;
pdu_rel15->vrb_to_prb_mapping = 0;
pdu_rel15->time_domain_assignment = 3;
pdu_rel15->vrb_to_prb_mapping = 1;
pdu_rel15->mcs = 12;
pdu_rel15->tb_scaling = 1;
pdu_rel15->ra_preamble_index = 25;
pdu_rel15->format_indicator = 1;
pdu_rel15->ul_sul_indicator = 1;
pdu_rel15->ss_pbch_index = 21;
pdu_rel15->prach_mask_index = 3;
pdu_rel15->ndi = 1;
pdu_rel15->rv = 2;
pdu_rel15->harq_pid = 7;
pdu_rel15->dai = 2;
pdu_rel15->tpc = 2;
pdu_rel15->pucch_resource_indicator = 7;
pdu_rel15->pdsch_to_harq_feedback_timing_indicator = 7;
pdu_rel15->tb_scaling = 1;
pdu_rel15->tb_scaling = 1;
pdu_rel15->tb_scaling = 1;
pdu_rel15->tb_scaling = 1;
LOG_I(MAC, "[gNB scheduler phytest] DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, mcs %d tb_scaling %d\n",
pdu_rel15->frequency_domain_assignment,
pdu_rel15->time_domain_assignment,
......@@ -83,7 +105,7 @@ void nr_schedule_css_dlsch_phytest(module_id_t module_idP,
pdu_rel15->tb_scaling);
params_rel15->rnti = 0x03;
params_rel15->rnti_type = NFAPI_NR_RNTI_RA;
params_rel15->rnti_type = NFAPI_NR_RNTI_C;
params_rel15->dci_format = NFAPI_NR_DL_DCI_FORMAT_1_0;
//params_rel15->aggregation_level = 1;
LOG_I(MAC, "DCI type 1 params: rmsi_pdcch_config %d, rnti %d, rnti_type %d, dci_format %d\n \
......
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