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ZhouShuya
OpenXG-RAN
Commits
3858af32
Commit
3858af32
authored
4 years ago
by
Sakthivel Velumani
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Write to USRP only when needed in TDD
parent
951fdfef
dev
Fix_SA_SIB1
NRPRACH_highSpeed_saankhya
NRUE_usedlschparallel
NR_10MHz
NR_DL_MIMO
NR_FAPI_beamindex_SSB_RO
NR_FAPI_beamindex_SSB_RO_SEMPROJ
NR_FDD_FIX
NR_FR2_initsync_fixes
NR_MAC_Multi_Rach_GlobalEdge
NR_MAC_SSB
NR_MAC_TCI_UCI_GlobalEdge
NR_MCS_BLER
NR_SA_F1AP_5GRECORDS
NR_SA_F1AP_5GRECORDS_lts
NR_SA_F1AP_RFSIMULATOR3
NR_SA_F1AP_RFSIMULATOR3_tmp
NR_SA_F1AP_RFSIMULATOR_w5GCN
NR_SA_w5GCN_new_gtpu
NR_UE_CONFIG_REQ_FIXES
NR_UE_SA
NR_cleanup_PUCCH_resources
NR_multiplexing_HARQ_CSI_PUCCH
NR_scheduling_CSIRS
NR_scheduling_request
PBCHNRTCFIX
RFquality
Saankhya_NRPRACH_HighSpeed
add-dmrs-test
benetel_config_file_fix
benetel_driver_update
benetel_fixes
bsr-fix
bugfix-free-ra-process
bugfix-nr-t-reordering
bugfix_gnb_rt_stats_html
ci-new-docker-pipeline
ci-reduce-nb-vms
ci_benetel_test
ci_phytest
ci_quectel_support
ci_test_nsa_fix_quectel_nic
ci_test_ra_fr2
ci_vm_resource_fix
detached-w16-test
develop
develop-CBRA-v3
develop-CCE
develop-NR_SA_F1AP_5GRECORDS
develop-NR_SA_F1AP_5GRECORDS-hs
develop-NR_SA_F1AP_5GRECORDS-v3
develop-SA-CBRA
develop-SA-CBRA-CUDU
develop-SA-CBRA-Msg5
develop-SA-CBRA-lts
develop-SA-CBRA-ulsch-lts
develop-SA-RA
disable_CSI_measrep
docker-improvements-2021-april
docker-no-cache-option
enhance-rfsim
episys-merge
episys/nsa_baseline
episys/nsa_development
fft_bench_hotfix
fix-nr-pdcp-timer
fix-nr-rlc-range-nack
fix-physim-deploy
fix-quectel
fix-realtime
fix-x2-without-gnb
fix_NR_DLUL_PF
fix_NR_DLUL_PF_benchmark
fix_coreset_dmrs_idx
fix_nr_ulsim
fix_rb_corruption
fix_reestablishment
fixgtpu
git-dashboard
gnb-freerun-txru
gnb-n300-fixes
gnb-realtime-hotfix
gnb-realtime-quickfix
gnb-threadpool
hack-exit-gnb-when-no-enb-nsa
integ-w13-test-rt-issue
integration_2020_wk15
integration_2021_wk06_MR978
integration_2021_wk06_b
integration_2021_wk06_c
integration_2021_wk08
integration_2021_wk08_2
integration_2021_wk08_MR963
integration_2021_wk09
integration_2021_wk09_b
integration_2021_wk10
integration_2021_wk10_b
integration_2021_wk11
integration_2021_wk12
integration_2021_wk12_b
integration_2021_wk13_a
integration_2021_wk13_b
integration_2021_wk13_b_fix_tdas
integration_2021_wk13_b_fixed
integration_2021_wk13_c
integration_2021_wk14_a
integration_2021_wk15_a
integration_2021_wk16
integration_2021_wk17_a
integration_2021_wk17_b
integration_2021_wk18_a
integration_2021_wk18_b
integration_2021_wk19
integration_w5GC_CBRA_test
inter-RRU-final
migrate-cpp-check-container
msg4_phy_0303_lfq
multiple_ssb_sib1_bugfix
new-gtpu
nfapi_nr_arch_mod
nfapi_nr_develop_new
nr-bsr-fix
nr-dl-mimo-2layer
nr-dmrs-fixes
nr-pdcp-improvements
nr-pdcp-nea2-security
nr-pdcp-nia2-integrity
nr-pdcp-srb-integrity
nr-ra-fix
nr-stats-print
nrPBCHTCFix
nrPbchTcFix
nr_power_measurement_fixes
nr_ue_pdcp_fix
oairu
physim-build-deploy
physim-deploy-handle-error-cases
prb_based_dl_channel_estimation
ptrs_rrc_config
recursive-cmake
rh_ci_add_runtime_stats
rh_ci_add_uldlharq_stats
rh_ci_gsheet_rt_monitoring
rh_ci_nsa2jenkins
rh_ci_nsa_test_n310
rh_ci_phy_test_improve
rh_ci_test_benetel
rh_ci_test_nsa
rh_ci_test_nsa_wk16
rh_ci_test_nsa_wk17_b
rh_ci_test_nsa_wk17b
rohan_ulsim2RxFix
s1_subnormal
sanitize-address
sanitize-v1
sanitize-v1-tmp
sarma_pvnp_oai
sim-channels
small_nr_bugfixes
t-gnb-tracer
test-panos
test_nsa_gtpu_fix
test_rt-fix_phy-test
ue-dci-false-detection
ue-fixes
ue-pdsch-pusch-parallel
ue-race-fix
usrp_stop_cleanly
usrp_x400
wf-sa-rrc
wk11-with-phytest
xw2
2021.wk14_a
2021.wk13_d
2021.wk13_c
2021.w18_b
2021.w18_a
2021.w17_b
2021.w16
2021.w15
2021.w14
2021.w13_a
2021.w12
2021.w11
2021.w10
2021.w09
2021.w08
2021.w06
benetel_gnb_rel_2.0
benetel_gnb_rel_1.0
benetel_enb_rel_2.0
benetel_enb_rel_1.0
No related merge requests found
Changes
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23 additions
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10 deletions
+23
-10
executables/nr-ue.c
executables/nr-ue.c
+23
-10
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executables/nr-ue.c
View file @
3858af32
...
...
@@ -705,8 +705,7 @@ void *UE_thread(void *arg) {
UE
->
rx_offset_diff
=
computeSamplesShift
(
UE
);
readBlockSize
=
get_readBlockSize
(
slot_nr
,
&
UE
->
frame_parms
)
-
UE
->
rx_offset_diff
;
writeBlockSize
=
UE
->
frame_parms
.
get_samples_per_slot
((
slot_nr
+
DURATION_RX_TO_TX
-
RX_NB_TH
)
%
nb_slot_frame
,
&
UE
->
frame_parms
)
-
UE
->
rx_offset_diff
;
writeBlockSize
=
UE
->
frame_parms
.
get_samples_per_slot
((
slot_nr
+
DURATION_RX_TO_TX
-
RX_NB_TH
)
%
nb_slot_frame
,
&
UE
->
frame_parms
)
-
UE
->
rx_offset_diff
;
}
AssertFatal
(
readBlockSize
==
...
...
@@ -765,14 +764,28 @@ void *UE_thread(void *arg) {
timing_advance
=
UE
->
timing_advance
;
}
AssertFatal
(
writeBlockSize
==
int
flags
=
0
;
int
slot_tx_usrp
=
slot_nr
+
DURATION_RX_TO_TX
-
RX_NB_TH
;
uint8_t
tdd_period
=
mac
->
phy_config
.
config_req
.
tdd_table
.
tdd_period_in_slots
;
uint8_t
num_UL_slots
=
mac
->
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
nrofUplinkSlots
+
(
mac
->
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
nrofUplinkSymbols
!=
0
);
uint8_t
first_tx_slot
=
tdd_period
-
num_UL_slots
;
if
(
slot_tx_usrp
%
tdd_period
==
first_tx_slot
)
flags
=
2
;
else
if
(
slot_tx_usrp
%
tdd_period
==
first_tx_slot
+
num_UL_slots
-
1
)
flags
=
3
;
else
if
(
slot_tx_usrp
%
tdd_period
>
first_tx_slot
)
flags
=
1
;
if
(
flags
||
IS_SOFTMODEM_RFSIM
)
AssertFatal
(
writeBlockSize
==
UE
->
rfdevice
.
trx_write_func
(
&
UE
->
rfdevice
,
writeTimestamp
,
txp
,
writeBlockSize
,
UE
->
frame_parms
.
nb_antennas_tx
,
1
),
""
);
writeTimestamp
,
txp
,
writeBlockSize
,
UE
->
frame_parms
.
nb_antennas_tx
,
flags
),
""
);
for
(
int
i
=
0
;
i
<
UE
->
frame_parms
.
nb_antennas_tx
;
i
++
)
memset
(
txp
[
i
],
0
,
writeBlockSize
);
...
...
@@ -780,7 +793,7 @@ void *UE_thread(void *arg) {
msgToPush
->
key
=
slot_nr
;
pushTpool
(
&
(
get_nrUE_params
()
->
Tpool
),
msgToPush
);
if
(
IS_SOFTMODEM_RFSIM
||
IS_SOFTMODEM_NOS1
)
{
//getenv("RFSIMULATOR")
if
(
IS_SOFTMODEM_RFSIM
)
{
//getenv("RFSIMULATOR")
// FixMe: Wait previous thread is done, because race conditions seems too bad
// in case of actual RF board, the overlap between threads mitigate the issue
// We must receive one message, that proves the slot processing is done
...
...
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