Commit b16d7b2e authored by hardy's avatar hardy

Merge remote-tracking branch 'origin/NR_mac_uci_functions_rework' into integration_2020_wk48_2

parents 28559707 82c4380a
dev 256_QAM_demod Fix_SA_SIB1 NR-PHY-MAC-IF-multi-UE NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_FR2_initsync_fixes NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_PUCCH_MultiUE NR_RA_cleanup NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_UE_CONFIG_REQ_FIXES NR_UE_SA NR_UE_dlsch_bugfix NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_Wireshark NR_beam_simulation NR_cleanup_PUCCH_resources NR_multiplexing_HARQ_CSI_PUCCH NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 PBCHNRTCFIX RFquality Saankhya_NRPRACH_HighSpeed add-dmrs-test benetel_config_file_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes bsr-fix bugfix-free-ra-process bugfix-nr-pdcp-sn-size bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge ci-deploy-asterix ci-deploy-docker-compose ci-new-docker-pipeline ci-reduce-nb-vms ci-test ci_benetel_test ci_phytest ci_quectel_support ci_test_nsa_fix_quectel_nic ci_test_ra_fr2 ci_vm_resource_fix cleanup_softmodem_main constant_power detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-v3 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop_stable disable_CSI_measrep docker-improvements-2021-april docker-no-cache-option enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development fft_bench_hotfix fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-quectel fix-realtime fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_do_ra_data fix_nr_ulsim fix_rb_corruption fix_reestablishment fixes-CE-RLC-PDU-size fixgtpu flexran-repair-mme-mgmt git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-only-test gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-exit-gnb-when-no-enb-nsa integ-w13-test-rt-issue integration_2020_wk15 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_w5GC_CBRA_test inter-RRU-final itti-enhancement ldpc_short_codeword_fixes lte-ulsch-bugfix lte_uplink_improvement migrate-cpp-check-container minor-fix-doc-basic-sim mosaic5g-oai-ran msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-srb-integrity nr-ra-fix nr-stats-print nrPBCHTCFix nrPbchTcFix nr_dl_pf nr_power_measurement_fixes nr_ue_pdcp_fix nr_ul_pf nr_ul_scfdma oairu oairu-dockerfile-support openxg/develop physim-build-deploy physim-deploy-handle-error-cases prb_based_dl_channel_estimation ptrs_rrc_config pusch-retrans-fix-ue recursive-cmake remove_nos1_hack_pdcp rh-ci-add-ue-parallelization rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins rh_ci_nsa_test_n310 rh_ci_phy_test_improve rh_ci_ra_fr2 rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_nsa_wk16 rh_ci_test_nsa_wk17_b rh_ci_test_nsa_wk17b rh_ci_ue_parallel rh_fr1_newjenkins rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rohan_ulsim2RxFix s1-subnormal_rewrite s1_subnormal s1_subnormal-robert sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz sanitize-address sanitize-v1 sanitize-v1-tmp sarma_pvnp_oai sim-channels small-config-change small_nr_bugfixes t-gnb-tracer test-panos test_nsa_gtpu_fix test_rt-fix_phy-test ue-dci-false-detection ue-fixes ue-pdsch-pusch-parallel ue-race-fix ue_beam_selection usrp_stop_cleanly usrp_x400 wf-sa-rrc wireshark-T-hack-ueid wireshark-log-scheduling-requests wk11-with-phytest xiangwab xiangwan xw2 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 2021.w05 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 benetel_gnb_rel_2.0 benetel_gnb_rel_1.0 benetel_enb_rel_2.0 benetel_enb_rel_1.0
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......@@ -2087,6 +2087,7 @@ set (MAC_NR_SRC
${NR_GNB_MAC_DIR}/gNB_scheduler_ulsch.c
${NR_GNB_MAC_DIR}/gNB_scheduler_primitives.c
${NR_GNB_MAC_DIR}/gNB_scheduler_phytest.c
${NR_GNB_MAC_DIR}/gNB_scheduler_uci.c
${NR_GNB_MAC_DIR}/gNB_scheduler_RA.c
)
......
......@@ -337,61 +337,6 @@ void nr_schedule_pusch(int Mod_idP,
}
}
void nr_schedule_pucch(int Mod_idP,
int UE_id,
int nr_ulmix_slots,
frame_t frameP,
sub_frame_t slotP) {
uint16_t O_csi, O_ack, O_uci;
uint8_t O_sr = 0; // no SR in PUCCH implemented for now
NR_ServingCellConfigCommon_t *scc = RC.nrmac[Mod_idP]->common_channels->ServingCellConfigCommon;
NR_UE_info_t *UE_info = &RC.nrmac[Mod_idP]->UE_info;
AssertFatal(UE_info->active[UE_id],"Cannot find UE_id %d is not active\n",UE_id);
NR_CellGroupConfig_t *secondaryCellGroup = UE_info->secondaryCellGroup[UE_id];
int bwp_id=1;
NR_BWP_Uplink_t *ubwp=secondaryCellGroup->spCellConfig->spCellConfigDedicated->uplinkConfig->uplinkBWP_ToAddModList->list.array[bwp_id-1];
nfapi_nr_ul_tti_request_t *UL_tti_req = &RC.nrmac[Mod_idP]->UL_tti_req[0];
NR_sched_pucch *curr_pucch;
for (int k=0; k<nr_ulmix_slots; k++) {
for (int l=0; l<2; l++) {
curr_pucch = &UE_info->UE_sched_ctrl[UE_id].sched_pucch[k][l];
O_ack = curr_pucch->dai_c;
O_csi = curr_pucch->csi_bits;
O_uci = O_ack + O_csi + O_sr;
if ((O_uci>0) && (frameP == curr_pucch->frame) && (slotP == curr_pucch->ul_slot)) {
UL_tti_req->SFN = curr_pucch->frame;
UL_tti_req->Slot = curr_pucch->ul_slot;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_type = NFAPI_NR_UL_CONFIG_PUCCH_PDU_TYPE;
UL_tti_req->pdus_list[UL_tti_req->n_pdus].pdu_size = sizeof(nfapi_nr_pucch_pdu_t);
nfapi_nr_pucch_pdu_t *pucch_pdu = &UL_tti_req->pdus_list[UL_tti_req->n_pdus].pucch_pdu;
memset(pucch_pdu,0,sizeof(nfapi_nr_pucch_pdu_t));
UL_tti_req->n_pdus+=1;
LOG_D(MAC,"Scheduling pucch reception for frame %d slot %d with (%d, %d, %d) (SR ACK, CSI) bits\n",
frameP,slotP,O_sr,O_ack,curr_pucch->csi_bits);
nr_configure_pucch(pucch_pdu,
scc,
ubwp,
UE_info->rnti[UE_id],
curr_pucch->resource_indicator,
O_csi,
O_ack,
O_sr);
memset((void *) &UE_info->UE_sched_ctrl[UE_id].sched_pucch[k][l],
0,
sizeof(NR_sched_pucch));
}
}
}
}
bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot) {
return (bitmap >> slot) & 0x01;
}
......
......@@ -344,106 +344,6 @@ int nr_generate_dlsch_pdu(module_id_t module_idP,
return offset;
}
void nr_rx_acknack(nfapi_nr_uci_pusch_pdu_t *uci_pusch,
nfapi_nr_uci_pucch_pdu_format_0_1_t *uci_01,
nfapi_nr_uci_pucch_pdu_format_2_3_4_t *uci_234,
NR_UL_IND_t *UL_info, NR_UE_sched_ctrl_t *sched_ctrl, NR_mac_stats_t *stats) {
// TODO
int max_harq_rounds = 4; // TODO define macro
if (uci_01 != NULL) {
// handle harq
int harq_idx_s = 0;
// iterate over received harq bits
for (int harq_bit = 0; harq_bit < uci_01->harq->num_harq; harq_bit++) {
// search for the right harq process
for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES; harq_idx++) {
// if the gNB received ack with a good confidence
if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) {
sched_ctrl->harq_processes[harq_idx].feedback_slot = -1;
if ((uci_01->harq->harq_list[harq_bit].harq_value == 1) &&
(uci_01->harq->harq_confidence_level == 0)) {
// toggle NDI and reset round
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
else
sched_ctrl->harq_processes[harq_idx].round++;
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
harq_idx_s = harq_idx + 1;
// if the max harq rounds was reached
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
stats->dlsch_errors++;
}
break;
}
// if feedback slot processing is aborted
else if (sched_ctrl->harq_processes[harq_idx].feedback_slot != -1
&& (UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot
&& sched_ctrl->harq_processes[harq_idx].is_waiting) {
sched_ctrl->harq_processes[harq_idx].feedback_slot = -1;
sched_ctrl->harq_processes[harq_idx].round++;
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
}
}
}
}
if (uci_234 != NULL) {
int harq_idx_s = 0;
int acknack;
// iterate over received harq bits
for (int harq_bit = 0; harq_bit < uci_234->harq.harq_bit_len; harq_bit++) {
acknack = ((uci_234->harq.harq_payload[harq_bit>>3])>>harq_bit)&0x01;
for (int harq_idx = harq_idx_s; harq_idx < NR_MAX_NB_HARQ_PROCESSES-1; harq_idx++) {
// if the gNB received ack with a good confidence or if the max harq rounds was reached
if ((UL_info->slot-1) == sched_ctrl->harq_processes[harq_idx].feedback_slot) {
// TODO add some confidence level for when there is no CRC
sched_ctrl->harq_processes[harq_idx].feedback_slot = -1;
if ((uci_234->harq.harq_crc != 1) && acknack) {
// toggle NDI and reset round
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
else
sched_ctrl->harq_processes[harq_idx].round++;
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
harq_idx_s = harq_idx + 1;
// if the max harq rounds was reached
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
stats->dlsch_errors++;
}
break;
}
// if feedback slot processing is aborted
else if (sched_ctrl->harq_processes[harq_idx].feedback_slot != -1
&& (UL_info->slot-1) > sched_ctrl->harq_processes[harq_idx].feedback_slot
&& sched_ctrl->harq_processes[harq_idx].is_waiting) {
sched_ctrl->harq_processes[harq_idx].feedback_slot = -1;
sched_ctrl->harq_processes[harq_idx].round++;
if (sched_ctrl->harq_processes[harq_idx].round == max_harq_rounds) {
sched_ctrl->harq_processes[harq_idx].ndi ^= 1;
sched_ctrl->harq_processes[harq_idx].round = 0;
}
sched_ctrl->harq_processes[harq_idx].is_waiting = 0;
}
}
}
}
}
int getNrOfSymbols(NR_BWP_Downlink_t *bwp, int tda) {
struct NR_PDSCH_TimeDomainResourceAllocationList *tdaList =
bwp->bwp_Common->pdsch_ConfigCommon->choice.setup->pdsch_TimeDomainAllocationList;
......
This diff is collapsed.
......@@ -183,6 +183,9 @@ void nr_schedule_pucch(int Mod_idP,
frame_t frameP,
sub_frame_t slotP);
void csi_period_offset(NR_CSI_ReportConfig_t *csirep,
int *period, int *offset);
void nr_csi_meas_reporting(int Mod_idP,
int UE_id,
frame_t frameP,
......
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