Commit 6fcc4f59 authored by Robert Schmidt's avatar Robert Schmidt

Format to dynamically handle UL SCHED

parent af89a6b7
dev 1 128-ues 256_QAM_demod Fix_SA_SIB1 NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_CSI_reporting NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_FR2_initsync_fixes NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_NGAP NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguration_FR2 NR_RRC_config_simplified NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_UE_CONFIG_REQ_FIXES NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_SA NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_UL_scheduler_rebased NR_Wireshark NR_beam_simulation NR_mac_uci_functions_rework NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 PBCHNRTCFIX PUSCH_TA_update RA_CI_test RFquality Saankhya_NRPRACH_HighSpeed UE_DL_DCI_hotfix add-dmrs-test bch-fixes-bitmap benetel_5g_prach_fix benetel_config_file_fix benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes benetel_phase_rotation benetel_phase_rotation_old bsr-fix bugfix-free-ra-process bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-deploy-asterix ci-deploy-docker-compose ci-new-docker-pipeline ci-reduce-nb-vms ci-test ci-ul-iperf-from-trf-container ci_benetel_test ci_phytest ci_quectel_support ci_test_ra_fr2 ci_vm_resource_fix cleanup_softmodem_main constant_power develop develop-CBRA-v3 develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-v3 develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop_stable dfts_alternatives disable_CSI_measrep dlsch_encode_mthread dlsch_parallel docker-improvements-2021-april docker-no-cache-option dongzhanyi-zte-develop2 enhance-rfsim episys-merge episys/nsa_development feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fembms-enb-ue fft_bench_hotfix finalize-oaicn-integration firas fix-ci-tun fix-itti-segv fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-quectel fix-realtime fix-softmodem-restart fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_do_ra_data fix_pdsch_low_prb fix_rb_corruption fix_reestablishment fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun fixgtpu flexran-apps flexran-repair-mme-mgmt fujitsu_lte_contribution fujitsu_lte_contribution-128 git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-only-test gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-exit-gnb-when-no-enb-nsa harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable improve_nr_modulation integ-w13-test-rt-issue integration_2020_wk15 integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_w5GC_CBRA_test inter-RRU-final itti-enhancement ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 migrate-cpp-check-container minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-srb-integrity nr-ra-fix nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nr-stats-print nrPBCHTCFix nrPbchTcFix nrUE nrUE-hs nrUE-upper-layer nr_bsr nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_fdd_if_fix nr_power_measurement_fixes nr_prach_fr2 nr_ue_msg3 nr_ue_pdcp_fix nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oairu oairu-dockerfile-support oc-docker-october-improvements openxg/develop physim-build-deploy prb_based_dl_channel_estimation ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul recursive-cmake remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert_memcpy rh-ci-add-ue-parallelization rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins rh_ci_nsa_test_n310 rh_ci_oc rh_ci_phy_test_improve rh_ci_py rh_ci_ra_fr2 rh_ci_rfsim_ra rh_ci_ue_parallel rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rohan_ulsim2RxFix rrc-enb-phy-testmode s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-demo-hs sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz sanitize-address sanitize-v1 sanitize-v1-tmp sarma_pvnp_oai sim-channels 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...@@ -1276,7 +1276,7 @@ typedef struct { ...@@ -1276,7 +1276,7 @@ typedef struct {
/** /**
* definition of a scheduling algorithm implementation used in the * definition of a scheduling algorithm implementation used in the
* default scheduler * default DL scheduler
*/ */
typedef struct { typedef struct {
char *name; char *name;
...@@ -1287,6 +1287,19 @@ typedef struct { ...@@ -1287,6 +1287,19 @@ typedef struct {
void *data; void *data;
} default_sched_dl_algo_t; } default_sched_dl_algo_t;
/**
* definition of a scheduling algorithm implementation used in the
* default UL scheduler
*/
typedef struct {
char *name;
void *(*setup)(void);
void (*unset)(void **);
int (*run)(
module_id_t, int, int, int, int, int, UE_list_t *, int, int, contig_rbs_t *, void *);
void *data;
} default_sched_ul_algo_t;
/*! \brief eNB common channels */ /*! \brief eNB common channels */
typedef struct { typedef struct {
int physCellId; int physCellId;
...@@ -1447,6 +1460,7 @@ typedef struct eNB_MAC_INST_s { ...@@ -1447,6 +1460,7 @@ typedef struct eNB_MAC_INST_s {
SCHEDULER_MODES scheduler_mode; SCHEDULER_MODES scheduler_mode;
/// scheduling algorithm used in default scheduler /// scheduling algorithm used in default scheduler
default_sched_dl_algo_t dl_algo; default_sched_dl_algo_t dl_algo;
default_sched_ul_algo_t ul_algo;
int32_t puSch10xSnr; int32_t puSch10xSnr;
int32_t puCch10xSnr; int32_t puCch10xSnr;
......
...@@ -133,6 +133,11 @@ void mac_top_init_eNB(void) ...@@ -133,6 +133,11 @@ void mac_top_init_eNB(void)
AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s); AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s);
mac[i]->dl_algo = *(default_sched_dl_algo_t *) d; mac[i]->dl_algo = *(default_sched_dl_algo_t *) d;
mac[i]->dl_algo.data = mac[i]->dl_algo.setup(); mac[i]->dl_algo.data = mac[i]->dl_algo.setup();
s = "round_robin_ul";
d = dlsym(NULL, s);
AssertFatal(d, "%s(): no scheduler algo '%s' found\n", __func__, s);
mac[i]->ul_algo = *(default_sched_ul_algo_t *) d;
mac[i]->ul_algo.data = mac[i]->ul_algo.setup();
init_UE_info(&mac[i]->UE_info); init_UE_info(&mac[i]->UE_info);
init_slice_info(&mac[i]->slice_info); init_slice_info(&mac[i]->slice_info);
} }
......
...@@ -830,17 +830,28 @@ int pp_find_rb_table_index(int approximate) { ...@@ -830,17 +830,28 @@ int pp_find_rb_table_index(int approximate) {
return p + 1; return p + 1;
} }
int g_start_ue_ul = -1; void *rr_ul_setup(void) {
int round_robin_ul(module_id_t Mod_id, void *data = malloc(sizeof(int));
int CC_id, *(int *) data = 0;
int frame, AssertFatal(data, "could not allocate data in %s()\n", __func__);
int subframe, return data;
int sched_frame, }
int sched_subframe, void rr_ul_unset(void **data) {
UE_list_t *UE_list, if (*data)
int max_num_ue, free(*data);
int num_contig_rb, *data = NULL;
contig_rbs_t *rbs) { }
int rr_ul_run(module_id_t Mod_id,
int CC_id,
int frame,
int subframe,
int sched_frame,
int sched_subframe,
UE_list_t *UE_list,
int max_num_ue,
int num_contig_rb,
contig_rbs_t *rbs,
void *data) {
AssertFatal(num_contig_rb <= 2, "cannot handle more than two contiguous RB regions\n"); AssertFatal(num_contig_rb <= 2, "cannot handle more than two contiguous RB regions\n");
UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info;
const int max_rb = num_contig_rb > 1 ? MAX(rbs[0].length, rbs[1].length) : rbs[0].length; const int max_rb = num_contig_rb > 1 ? MAX(rbs[0].length, rbs[1].length) : rbs[0].length;
...@@ -980,9 +991,10 @@ int round_robin_ul(module_id_t Mod_id, ...@@ -980,9 +991,10 @@ int round_robin_ul(module_id_t Mod_id,
end = la > lb ? 2 : -1; end = la > lb ? 2 : -1;
} }
if (g_start_ue_ul == -1) int *start_ue = data;
g_start_ue_ul = UE_list->head; if (*start_ue == -1)
int sUE_id = g_start_ue_ul; *start_ue = UE_list->head;
int sUE_id = *start_ue;
int rb_idx_given[MAX_MOBILES_PER_ENB]; int rb_idx_given[MAX_MOBILES_PER_ENB];
memset(rb_idx_given, 0, sizeof(rb_idx_given)); memset(rb_idx_given, 0, sizeof(rb_idx_given));
...@@ -1061,10 +1073,17 @@ int round_robin_ul(module_id_t Mod_id, ...@@ -1061,10 +1073,17 @@ int round_robin_ul(module_id_t Mod_id,
} }
/* just start with the next UE next time */ /* just start with the next UE next time */
g_start_ue_ul = next_ue_list_looped(UE_list, g_start_ue_ul); *start_ue = next_ue_list_looped(UE_list, *start_ue);
return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0); return rbs[0].length + (num_contig_rb > 1 ? rbs[1].length : 0);
} }
default_sched_ul_algo_t round_robin_ul = {
.name = "round_robin_ul",
.setup = rr_ul_setup,
.unset = rr_ul_unset,
.run = rr_ul_run,
.data = NULL
};
void ulsch_scheduler_pre_processor(module_id_t Mod_id, void ulsch_scheduler_pre_processor(module_id_t Mod_id,
int CC_id, int CC_id,
...@@ -1072,9 +1091,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1072,9 +1091,10 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
sub_frame_t subframeP, sub_frame_t subframeP,
int sched_frameP, int sched_frameP,
unsigned char sched_subframeP) { unsigned char sched_subframeP) {
UE_info_t *UE_info = &RC.mac[Mod_id]->UE_info; eNB_MAC_INST *mac = RC.mac[Mod_id];
const int N_RB_UL = to_prb(RC.mac[Mod_id]->common_channels[CC_id].ul_Bandwidth); UE_info_t *UE_info = &mac->UE_info;
COMMON_channels_t *cc = &RC.mac[Mod_id]->common_channels[CC_id]; const int N_RB_UL = to_prb(mac->common_channels[CC_id].ul_Bandwidth);
COMMON_channels_t *cc = &mac->common_channels[CC_id];
UE_list_t UE_to_sched; UE_list_t UE_to_sched;
UE_to_sched.head = -1; UE_to_sched.head = -1;
...@@ -1131,16 +1151,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1131,16 +1151,17 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
} }
} }
round_robin_ul(Mod_id, mac->ul_algo.run(Mod_id,
CC_id, CC_id,
frameP, frameP,
subframeP, subframeP,
sched_frameP, sched_frameP,
sched_subframeP, sched_subframeP,
&UE_to_sched, &UE_to_sched,
4, // max_num_ue 4, // max_num_ue
n_contig, n_contig,
rbs); rbs,
mac->ul_algo.data);
// the following block is meant for validation of the pre-processor to check // the following block is meant for validation of the pre-processor to check
// whether all UE allocations are non-overlapping and is not necessary for // whether all UE allocations are non-overlapping and is not necessary for
...@@ -1159,7 +1180,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id, ...@@ -1159,7 +1180,7 @@ void ulsch_scheduler_pre_processor(module_id_t Mod_id,
continue; continue;
print = 1; print = 1;
uint8_t harq_pid = subframe2harqpid(&RC.mac[Mod_id]->common_channels[CC_id], uint8_t harq_pid = subframe2harqpid(&mac->common_channels[CC_id],
sched_frameP, sched_subframeP); sched_frameP, sched_subframeP);
LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n", LOG_D(MAC, "%4d.%d UE%d %d RBs (index %d) at start %d, pre MCS %d %s\n",
frameP, frameP,
......
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