Commit 3faeff23 authored by Thomas Schlichter's avatar Thomas Schlichter

fixing compile errors and some warnings

parent 0e96ad6a
develop 1 128-ues 256_QAM_demod NR-PHY-MAC-IF-multi-UE NR_10MHz NR_CSI_reporting NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FR2_RA NR_FR2_RRC_SSB NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_NGAP NR_PUCCH_MultiUE NR_RA_updates NR_RRCConfiguration_FR2 NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SRB_Config NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_UL_DCI_improvements NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_scheduler NR_UL_scheduler_rebased NR_mac_uci_functions_rework NR_scheduling_CSIRS NR_scheduling_request PUSCH_TA_update RA_CI_test UE_DL_DCI_hotfix bch-fixes-bitmap benetel_5g_prach_fix benetel_phase_rotation bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion cce_indexing_fix cce_indexing_fix2 ci-deploy-docker-compose ci-ul-iperf-from-trf-container cleanup_softmodem_main constant_power develop-oriecpriupdates develop-sib1 dfts_alternatives dlsch_parallel dongzhanyi-zte-develop2 feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes finalize-oaicn-integration fix-ci-tun fix-itti-segv fix_do_ra_data fix_pdsch_low_prb fix_rrc_x2_ticking fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun flexran-apps flexran-repair-mme-mgmt fujitsu_lte_contribution fujitsu_lte_contribution-128 harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 inter-RRU-final ldpc-decoder-codegen2 ldpc_short_codeword_fixes load_gnb lte_uplink_improvement mac-fixes-wk45_2 mosaic5g-oai-ran mosaic5g-oai-sim nfapi_nr_develop ngap-dlul ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nrUE nrUE-hs nrUE-upper-layer nr_bsr nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_fdd_if_fix nr_prach_fr2 nr_ue_msg3 nr_ue_tti_cleanup nsa-ue nsa_remove_band_hardcodings oai-sim oc-docker-october-improvements openxg/develop ptrs_rrc_config pusch-mthread-scaling-fix ra-dl-ul remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert_memcpy rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_oc rh_ci_py rh_ci_rfsim_ra rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rrc-enb-phy-testmode s1_subnormal s1ap-bugfix-rab_setup small-bugfixes-w40 testing_with_external_txdata ul_dl_dci_same_slot ulsch_decode_mthread ulsim_changes x2-endc-processing yihongzheng_srb
...@@ -236,13 +236,12 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f) ...@@ -236,13 +236,12 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f)
} }
*/ */
int j2=0;
fp=f; fp=f;
switch (Qm) { switch (Qm) {
case 2: case 2:
e0=e; e0=e;
e1=e0+EQm; e1=e0+EQm;
for (int j = 0; j< EQm; j++,j2+=2){ for (int j = 0, j2 = 0; j< EQm; j++,j2+=2){
fp=&f[j2]; fp=&f[j2];
fp[0] = e0[j]; fp[0] = e0[j];
fp[1] = e1[j]; fp[1] = e1[j];
...@@ -253,7 +252,7 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f) ...@@ -253,7 +252,7 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f)
e1=e0+EQm; e1=e0+EQm;
e2=e1+EQm; e2=e1+EQm;
e3=e2+EQm; e3=e2+EQm;
for (int j = 0; j< EQm; j++,j2+=4){ for (int j = 0, j2 = 0; j< EQm; j++,j2+=4){
fp=&f[j2]; fp=&f[j2];
fp[0] = e0[j]; fp[0] = e0[j];
fp[1] = e1[j]; fp[1] = e1[j];
...@@ -287,7 +286,7 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f) ...@@ -287,7 +286,7 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f)
e5=e4+EQm; e5=e4+EQm;
e6=e5+EQm; e6=e5+EQm;
e7=e6+EQm; e7=e6+EQm;
for (int j = 0; j< EQm; j++,j2+=8){ for (int j = 0, j2 = 0; j< EQm; j++,j2+=8){
fp=&f[j2]; fp=&f[j2];
fp[0] = e0[j]; fp[0] = e0[j];
fp[1] = e1[j]; fp[1] = e1[j];
...@@ -310,7 +309,6 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f) ...@@ -310,7 +309,6 @@ void nr_interleaving_ldpc(uint32_t E, uint8_t Qm, uint8_t *e,uint8_t *f)
void nr_deinterleaving_ldpc(uint32_t E, uint8_t Qm, int16_t *e,int16_t *f) void nr_deinterleaving_ldpc(uint32_t E, uint8_t Qm, int16_t *e,int16_t *f)
{ {
int j2;
int16_t *e1,*e2,*e3,*e4,*e5,*e6,*e7; int16_t *e1,*e2,*e3,*e4,*e5,*e6,*e7;
switch(Qm) { switch(Qm) {
case 2: case 2:
......
...@@ -111,7 +111,6 @@ void nr_ulsch_unscrambling_optim(int16_t* llr, ...@@ -111,7 +111,6 @@ void nr_ulsch_unscrambling_optim(int16_t* llr,
uint32_t n_RNTI) { uint32_t n_RNTI) {
#if defined(__x86_64__) || defined(__i386__) #if defined(__x86_64__) || defined(__i386__)
uint8_t reset;
uint32_t x1, x2, s=0; uint32_t x1, x2, s=0;
x2 = (n_RNTI<<15) + Nid; x2 = (n_RNTI<<15) + Nid;
......
...@@ -88,4 +88,6 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB, ...@@ -88,4 +88,6 @@ void nr_ulsch_procedures(PHY_VARS_gNB *gNB,
uint8_t harq_pid); uint8_t harq_pid);
int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type); int16_t find_nr_ulsch(uint16_t rnti, PHY_VARS_gNB *gNB,find_type_t type);
void dump_pusch_stats(PHY_VARS_gNB *gNB);
void clear_pusch_stats(PHY_VARS_gNB *gNB);
...@@ -432,7 +432,6 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE, ...@@ -432,7 +432,6 @@ uint8_t nr_ue_pusch_common_procedures(PHY_VARS_NR_UE *UE,
int tx_offset, ap; int tx_offset, ap;
int32_t **txdata; int32_t **txdata;
int32_t **txdataF; int32_t **txdataF;
uint8_t Nl = UE->ulsch[thread_id][gNB_id][0]->harq_processes[harq_pid]->pusch_pdu.nrOfLayers; // cw 0
/////////////////////////IFFT/////////////////////// /////////////////////////IFFT///////////////////////
/////////// ///////////
......
...@@ -2933,7 +2933,7 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_ ...@@ -2933,7 +2933,7 @@ int nr_ue_pdsch_procedures(PHY_VARS_NR_UE *ue, UE_nr_rxtx_proc_t *proc, int eNB_
return -1; return -1;
} }
else { // This is to adjust the llr offset in the case of skipping over a dmrs symbol (i.e. in case of no PDSCH REs in DMRS) else { // This is to adjust the llr offset in the case of skipping over a dmrs symbol (i.e. in case of no PDSCH REs in DMRS)
if (pdsch == RA_PDSCH) ue->pdsch_vars_ra[eNB_id]->llr_offset[m]=ue->pdsch_vars_ra[eNB_id]->llr_offset[m-1]; if (pdsch == RA_PDSCH) ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr_offset[m]=ue->pdsch_vars[ue->current_thread_id[nr_tti_rx]][eNB_id]->llr_offset[m-1];
else if (pdsch == PDSCH) { else if (pdsch == PDSCH) {
if (nr_rx_pdsch(ue, if (nr_rx_pdsch(ue,
pdsch, pdsch,
...@@ -3892,7 +3892,6 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, ...@@ -3892,7 +3892,6 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
int coreset_nb_rb=0; int coreset_nb_rb=0;
int coreset_start_rb=0; int coreset_start_rb=0;
int symbol_offset_in_subframe=0;
if (pdcch_vars->nb_search_space > 0) if (pdcch_vars->nb_search_space > 0)
get_coreset_rballoc(pdcch_vars->pdcch_config[0].coreset.frequency_domain_resource,&coreset_nb_rb,&coreset_start_rb); get_coreset_rballoc(pdcch_vars->pdcch_config[0].coreset.frequency_domain_resource,&coreset_nb_rb,&coreset_start_rb);
...@@ -3903,7 +3902,6 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue, ...@@ -3903,7 +3902,6 @@ int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,
if ((ue->decode_MIB == 1) && slot_pbch) if ((ue->decode_MIB == 1) && slot_pbch)
{ {
LOG_I(PHY," ------ PBCH ChannelComp/LLR: frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx); LOG_I(PHY," ------ PBCH ChannelComp/LLR: frame.slot %d.%d ------ \n", frame_rx%1024, nr_tti_rx);
symbol_offset_in_subframe = (nr_tti_rx % fp->slots_per_subframe)*fp->symbols_per_slot;
for (int i=1; i<4; i++) { for (int i=1; i<4; i++) {
nr_slot_fep(ue, nr_slot_fep(ue,
......
...@@ -464,15 +464,15 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -464,15 +464,15 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
} }
if (get_softmodem_params()->phy_test == 0) if (get_softmodem_params()->phy_test == 0)
nr_schedule_RA(module_idP, frame_txP, slot_txP); nr_schedule_RA(module_idP, frame, slot);
else else
UE_list->fiveG_connected[UE_id] = true; UE_list->fiveG_connected[UE_id] = true;
if (get_softmodem_params()->phy_test == 1) { if (get_softmodem_params()->phy_test == 1) {
if (slot_txP == 7){ if (slot == 7){
NR_RA_t *ra = &RC.nrmac[module_idP]->common_channels[0].ra[0]; NR_RA_t *ra = &RC.nrmac[module_idP]->common_channels[0].ra[0];
ra->Msg2_frame = frame_txP; ra->Msg2_frame = frame;
ra->Msg2_slot = slot_txP; ra->Msg2_slot = slot;
ra->state = Msg2; ra->state = Msg2;
ra->bwp_id = 1; ra->bwp_id = 1;
NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id]; NR_CellGroupConfig_t *secondaryCellGroup = UE_list->secondaryCellGroup[UE_id];
...@@ -486,8 +486,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP, ...@@ -486,8 +486,8 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
AssertFatal(ra->ra_ss!=NULL,"no search space for RA'n"); AssertFatal(ra->ra_ss!=NULL,"no search space for RA'n");
nr_generate_Msg2(module_idP, 0/*CC_id*/, nr_generate_Msg2(module_idP, 0/*CC_id*/,
frame_txP, frame,
slot_txP); slot);
} }
} }
......
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