Commit 65f8298a authored by Raymond Knopp's avatar Raymond Knopp

modifications in UE system information handling to allow for decoding of all...

modifications in UE system information handling to allow for decoding of all SIBs. For USRP targets, timing advance and TX power control.

git-svn-id: http://svn.eurecom.fr/openair4G/trunk@7563 818b1a75-f10b-46b9-bf7c-635c3b92a50f
parent 9ae11fb8
develop 1 128-ues 207-feature-ued-platform-support 256_QAM_demod 2cw_fairRRscd 340-fix-beamforming-for-multiple-antenna 342-isip-pcie-lib 375-syrtem-sdr-platform 383-ulsch-scheduler-optimization 387-fraunhofer-iis-transmission-mode-4 401-bug-related-to-nr-pucch-format-2-generator 408-reworked 408-ue-main-threads 445-LDPC-implementation-on-GPU 459-pusch-based-ta-updates 464-ru_beamforming_in_gpu 464-ru_beamforming_in_gpu-CPUsubfunction 472-add-pusch-dmrs-modes 481-ldpc-decoder-on-gpu 5g_fapi_scf LTE-sidelink LTE_TRX_on_single_port NCTU_CS_ISIP NCTU_CS_ISIP_CPU NCTU_CS_ISIP_GPU NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NR_10MHz NR_CSI_reporting NR_DCI_01 NR_DL_sched_fixes NR_DL_scheduler NR_FAPI_beamindex_SSB_RO NR_FR2_RA NR_FR2_RRC_SSB NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_updates NR_RRCConfiguragion_FR2 NR_RRCConfiguration NR_RRCConfiguration_FR2 NR_RRCConfiguration_S1U NR_RRCConfiguration_merge_develop NR_RRCConfiguration_sync_source NR_RRCConfiguration_trx_thread NR_RRC_CP_bugfix NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_PRACH_procedures_todevelop NR_RRC_PUSCH NR_RRC_TA NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SCHED NR_SRB_Config NR_TRX_on_single_port NR_TRX_on_single_port2 NR_UE_MAC_scheduler NR_UE_RA_fixes NR_UE_UL_DCI_improvements NR_UE_enable_parallelization NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_beamforming_test NR_gNB_SCF_Indication NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_scheduling_CSIRS NR_scheduling_request NR_test_S1U_RRC_PRACH_procedures NR_ue_dlsch_dmrs_cdm New-Merge-sidelink-develop OpInConnect_ISIP PUSCH_TA_update PerfumeOldTdd RA_CI_test RRC-measurements-merge2develop UE_DL_DCI_hotfix UpdateRANRemoteUEReport add_iris_hw addoptions_nr_USRPdevice bch-fixes-bitmap benetel_5g_prach_fix benetel_phase_rotation benetel_phase_rotation_old block_mmse_receiver_with_whitenning bugfix-find-uci bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-pdcch_order cce_indexing_fix cce_indexing_fix2 ci-deploy-docker-compose ci-rd-july-improvements ci-ul-iperf-from-trf-container ci-yacine clean-5G-scope-round2 cleanup_softmodem_main constant_power debug_branch_init_sync develop-FeMBMS develop-aarch64build develop-ci develop-ci-fju develop-large-scale-emulations develop-m2ap develop-multi-RRUs develop-nb-iot develop-nb-iot-RRC develop-nb-iot-merge develop-nb-iot-merge-w-conflicts develop-nb-iot-ntust develop-nr develop-nr-adding-2018-09-asn1 develop-nr-fr2 develop-nr-fr2-rework develop-nr_cppcheck develop-oriecpriupdates develop-sib1 develop-sidekiq develop-vco3 develop_ci develop_inria_ci_deployment develop_inria_ci_deployment_gp develop_inria_ci_deployment_gp_b4merge develop_integration_2019_w44 develop_integration_2020_w15 develop_integration_2020_w19 develop_integration_w08 develop_jenkins_replay dfts_alternatives dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel dlsim-autotests documentation docupdate_tools dongzhanyi-zte-0001 dongzhanyi-zte-develop dongzhanyi-zte-develop2 dreibh/apt-auth-fix dreibh/device-load-fix dreibh/device-load-fix-develop-branch dreibh/doxygen-fix dual-connectivity dummy edrx enhancement-149-iqtxshift extend_sharedlibusage extend_sharedlibusage2 fapi_for_dmrs_and_ptrs feat-mac-sock feature-15-carrier_aggregation feature-21-TM7 feature-230-tm3_scheduler feature-247-tm89 feature-247-tm89-fixes feature-247-tm89-rebased feature-278-physical-layer-GPU-version feature-309-phy_procedures_eNB_TX_split_to_multi_threading feature-31-ff-scheduler-api feature-330-turbo_decoder_gpu feature-368-channel-simulator feature-39-X2-handover feature-4g-sched feature-68-enb-agent feature-flexran-cm-s1ap feature-nr-4g-nfapi-modifications feature-pdcp-task feature-send-rrc-message-for-wireshark-logging feature-support-clang-format feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes feature_tm3 fembms-enb-ue finalize-oaicn-integration firas fix-ci-tun fix-clock-source fix-dirty-ue-same-machine fix-itti fix-itti-segv fix-l2-sim fix-limeSDR-compile fix-segfault-flexran-isolated fix-softmodem-restart fix-warnings fix_do_ra_data fix_pdsch_low_prb fix_rfsim_mimo fix_rrc_x2_ticking fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun flexran-apps flexran-improvements flexran-repair-mme-mgmt flexran-report-split fr2-hw-test fujitsu_lte_contribution fujitsu_lte_contribution-128 gNB-nrUE-USRP gNB_mwc18_integration generate_push_ptrs harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable hotfix-ue-musim-compilation hotfix_usrp_lib improve_build_nr_lte_merge improve_nr_modulation improve_ue_stability initial-nfapi-PNF-fixes integration-develop-nr-2019w45 integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 inter-RRU inter-RRU-final inter-RRU-nr inter-RRU-oairu inter-rru-UE interoperability-test isip-turbo-decoder-dynamic isip-turbo-decoder-parallel isip_nr issue271_simulator issue392-simplify-s1-nos1step2_01 issue416_nfapicleanup issue_345_l2_fapi_simulator l2-fixes large_scale_simulations ldpc-dec-layering ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-decoder-improvements ldpc-offload ldpc_short_codeword_fixes load_gnb lte-m-ue_type lte_uplink_improvement mac-fixes-wk45_2 mac-monitoring main_python master mbms-fix-develop-nr merging-2019-w51-to-develop-nr mex_mmse_receiver mobipass-hack modify_fairRRscd_parallel mosaic5g-oai-ran mosaic5g-oai-sim mu_allocate multi-L1 multi-RRUs new_nos1 new_pdcp new_rlc new_rlc_2020 new_rlc_in_mbms nfapi-L2-emulator nfapi-bugfix nfapi_improvement nfapi_nr_develop ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-coreset-bug-fix nr-dlsch-multi-thread nr-dlsch-thread nr-dual-connectivity nr-interdigital-test nr-ip-uplink-noS1 nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-multiple-ssb nr-pdcp nr-pdsch-extraction-bugfix nr-physim-update nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nr-ssb-measurements nr-timing-measurement nr-timing-measurement-merge nr-ue-buffer-status nr-ue-slot-based nr-uldci nrUE nrUE-hs nrUE-upper-layer nr_beamforming nr_bsr nr_ci_dlsim nr_csi_newbranch nr_dci_procedures nr_demo_wsa2019 nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_dlsch_parallel_measurements nr_dlsim_plot nr_fapi_for_push_tmp nr_fdd_if_fix nr_fix_easycppcheck nr_flexible_NRBDL nr_improve_build_procedures nr_increase_tp nr_mib_vsa_test nr_pdcch_testing nr_pdcch_updates nr_pdsch_integration nr_polar_decoder_improvement nr_prach nr_prach_fr2 nr_pucch nr_pucch2 nr_segmentation_fixes nr_sim_fix nr_tdd_configuration nr_ue_msg3 nr_ue_tti_cleanup nr_vcd nrue-multi-thread nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oai-ubuntu-docker oai-ubuntu-docker-for-lmssdr oai_ue_mwc18_integration oairu oc-docker-october-improvements ocp_simulator openxg/develop pdcp-benchmark pdsch-ch-est polar8 preprocessor_refactor-2 ptrs_rrc_config pucch2ab pucchsim-multiue pusch-mthread-scaling-fix ra-dl-ul rau_rru_reciprocity_measurements recode_itti_from_scratch reduce_memory_footprint release_v1_2_0_candidate remove-ci-workaround remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert-f5c94279 revert-itti revert_memcpy rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_oc rh_ci_py rh_ci_rfsim_ra rh_doc_update_3 rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rhel77-build rlc-v2-bugfix-status-reporting rlc-v2-tick rlc_v2_coverity_fixes rrc-enb-phy-testmode rru-txwrite-modification ru-parallel-beamforming ru_rau_enhancement ru_rau_enhancement-external-timing runel runel-reverse-test s1_subnormal s1ap-bugfix-rab_setup schedule-si-fix signal-delay small-bugfixes-w40 smallcleanup softmodem_cleanup split73 tcri test-x310-perf testing_2symb_pdcch testing_with_external_txdata thread-pool tm7-iris tools_5Gadapt tp-ota-test trx_thread_param trx_write_thread ue-csi ue-fixes-ota ue-updates-runel-test ue_adjust_gain ue_dlsch-multi-threading ue_dlsch_decoding_ldpc_offload ue_nfapi_mch ues_test_tmp uhd_priority_set_cleanup ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes update-to-2019-march-june-release usrp_fix_adc_shift_and_pps_sync usrp_gpio_test workaround-rebased workaround-restart-not-working x2-endc-processing x2-ho x2-ka-test x2_neighbor_6cells x2_tdd yihongzheng_srb zzs
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......@@ -2,13 +2,13 @@ cmake_minimum_required(VERSION 2.8)
set(XFORMS True)
set(RRC_ASN1_VERSION "Rel10")
set(ENABLE_VCD_FIFO False )
set(RF_BOARD "EXMIMO")
set(RF_BOARD "OAI_USRP")
set(ENABLE_ITTI True)
set(ENABLE_USE_MME False)
set(PDCP_USE_NETLINK True)
set(LINK_ENB_PDCP_TO_IP_DRIVER True)
set(LINK_ENB_PDCP_TO_GTPV1U False)
set(PDCP_USE_NETLINK True )
set(PDCP_USE_NETLINK_QUEUES False)
set(LINUX True)
set(SECU False)
set(NAS_UE False)
......
......@@ -39,9 +39,7 @@
#include "SCHED/extern.h"
#include "MAC_INTERFACE/defs.h"
#include "MAC_INTERFACE/extern.h"
#ifdef USER_MODE
#include <math.h>
#endif
#ifdef OPENAIR2
#include "LAYER2/MAC/defs.h"
......@@ -296,12 +294,10 @@ int lte_sync_time_init(LTE_DL_FRAME_PARMS *frame_parms ) // LTE_UE_COMMON *com
#ifdef USER_MODE
#ifdef DEBUG_PHY
write_output("primary_sync0.m","psync0",primary_synch0_time,frame_parms->ofdm_symbol_size,1,1);
write_output("primary_sync1.m","psync1",primary_synch1_time,frame_parms->ofdm_symbol_size,1,1);
write_output("primary_sync2.m","psync2",primary_synch2_time,frame_parms->ofdm_symbol_size,1,1);
#endif
#endif
return (1);
}
......@@ -310,7 +306,6 @@ int lte_sync_time_init(LTE_DL_FRAME_PARMS *frame_parms ) // LTE_UE_COMMON *com
void lte_sync_time_free(void)
{
#ifdef USER_MODE
if (sync_corr_ue0) {
msg("Freeing sync_corr_ue (%p)...\n",sync_corr_ue0);
......@@ -342,7 +337,6 @@ void lte_sync_time_free(void)
free(primary_synch2_time);
}
#endif
sync_corr_ue0 = NULL;
sync_corr_ue1 = NULL;
sync_corr_ue2 = NULL;
......@@ -502,7 +496,7 @@ int lte_sync_time(int **rxdata, ///rx data in time domain
sync_source,peak_pos,peak_val);
#ifdef USER_MODE
if (debug_cnt == 0) {
write_output("sync_corr0_ue.m","synccorr0",sync_corr_ue0,2*length,1,2);
......@@ -514,7 +508,7 @@ int lte_sync_time(int **rxdata, ///rx data in time domain
debug_cnt++;
}
#endif
#endif
......@@ -574,11 +568,8 @@ int lte_sync_time_eNB(int32_t **rxdata, ///rx data in time domain
//calculate dot product of primary_synch0_time and rxdata[ar][n] (ar=0..nb_ant_rx) and store the sum in temp[n];
for (ar=0; ar<frame_parms->nb_antennas_rx; ar++) {
//#ifndef USER_MODE
result = dot_product((short*)primary_synch_time, (short*) &(rxdata[ar][n]), frame_parms->ofdm_symbol_size, 15);
//#else
// result = dot_product((short*)primary_synch_time, (short*) &(rxdata[ar][n]), frame_parms->ofdm_symbol_size+frame_parms->nb_prefix_samples, 12);
//#endif
//((short*)sync_corr)[2*n] += ((short*) &result)[0];
//((short*)sync_corr)[2*n+1] += ((short*) &result)[1];
sync_corr_eNB[n] += abs32(result);
......
......@@ -3714,10 +3714,10 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
}*/
if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)) { //
if (dlsch0_harq->round == 4) {
// if ((dlsch0_harq->round == 4) || ( {
dlsch0_harq->round = 0;
dlsch0_harq->first_tx = 1;
}
// }
// if (dlsch0_harq->round == 0)
// ndi = 1-dlsch0_harq->DCINdi;
......@@ -3731,8 +3731,15 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
dlsch0_harq->mimo_mode = frame_parms->mode1_flag == 1 ?SISO : ALAMOUTI;
dlsch0_harq->dl_power_off = 1; //no power offset
//LOG_I(PHY,"UE (%x/%d): Subframe %d Format1A DCI: ndi %d, old_ndi %d (first tx %d) harq_status %d\n",dlsch[0]->rnti,harq_pid,subframe,ndi,dlsch0_harq->DCINdi,
//dlsch0_harq->first_tx,dlsch0_harq->status);
LOG_D(PHY,"UE (%x/%d): Subframe %d Format1A DCI: ndi %d, old_ndi %d (first tx %d) harq_status %d, round %d\n",
dlsch[0]->rnti,
harq_pid,
subframe,
ndi,
dlsch0_harq->DCINdi,
dlsch0_harq->first_tx,
dlsch0_harq->status,
dlsch0_harq->round);
if ((ndi!=dlsch0_harq->DCINdi)|| // DCI has been toggled or this is the first transmission
(dlsch0_harq->first_tx==1)) {
dlsch0_harq->round = 0;
......@@ -3746,7 +3753,14 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
dlsch0_harq->DCINdi = ndi;
dlsch0_harq->mcs = mcs;
dlsch0_harq->TBS = TBStable[get_I_TBS(mcs)][NPRB-1];
if ((rnti==si_rnti) || (rnti==p_rnti) || (rnti==ra_rnti)) {
dlsch0_harq->TBS = TBStable[mcs][NPRB-1];
dlsch0_harq->Qm = 2;
}
else {
dlsch0_harq->TBS = TBStable[get_I_TBS(mcs)][NPRB-1];
dlsch0_harq->Qm = get_Qm(mcs);
}
dlsch[0]->rnti = rnti;
dlsch0 = dlsch[0];
//printf("Format 1A: harq_pid %d, nb_rb %d, round %d\n",harq_pid,dlsch0_harq->nb_rb,dlsch0_harq->round);
......@@ -3898,6 +3912,12 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
dlsch0_harq->mcs = mcs;
dlsch0_harq->TBS = TBStable[get_I_TBS(mcs)][NPRB-1];
if (mcs <= 28)
dlsch0_harq->Qm = get_Qm(mcs);
else if (mcs<=31)
dlsch0_harq->Qm = (mcs-28)<<1;
else
LOG_E(PHY,"invalid mcs %d\n",mcs);
// msg("test: MCS %d, NPRB %d, TBS %d\n",mcs,NPRB,dlsch0_harq->TBS);
dlsch[0]->current_harq_pid = harq_pid;
......@@ -4238,9 +4258,17 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
if (dlsch0_harq->nb_rb>1) {
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
if (mcs1 <= 28)
dlsch0_harq->Qm = get_Qm(mcs1);
else if (mcs1<=31)
dlsch0_harq->Qm = (mcs1-28)<<1;
else
LOG_E(PHY,"invalid mcs1 %d\n",mcs1);
} else
dlsch0_harq->TBS =0;
/*
if (dlsch0_harq->mcs > 18)
printf("mcs %d, TBS %d\n",dlsch0_harq->mcs,dlsch0_harq->TBS);
......@@ -4256,9 +4284,16 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
if (dlsch1_harq->nb_rb>1) {
dlsch1_harq->TBS = TBStable[dlsch1_harq->mcs][dlsch1_harq->nb_rb-1];
if (mcs2 <= 28)
dlsch1_harq->Qm = get_Qm(mcs2);
else if (mcs1<=31)
dlsch1_harq->Qm = (mcs2-28)<<1;
else
LOG_E(PHY,"invalid mcs2 %d\n",mcs2);
} else
dlsch1_harq->TBS = 0;
dlsch0->rnti = rnti;
dlsch1->rnti = rnti;
......@@ -4626,6 +4661,8 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch0_harq->nb_rb-1];
if ((dlsch0->active==1) && (dlsch1->active==1)) {
dlsch0_harq->mimo_mode = LARGE_CDD;
dlsch1_harq->mimo_mode = LARGE_CDD;
......@@ -4644,7 +4681,8 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
dlsch0_harq->dl_power_off = 0; //apply power offset
dlsch1_harq->dl_power_off = 0; //apply power offset
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch0_harq->TBS = TBStable[get_I_TBS(dlsch0_harq->mcs)][dlsch0_harq->nb_rb-1];
dlsch1_harq->TBS = TBStable[get_I_TBS(dlsch1_harq->mcs)][dlsch1_harq->nb_rb-1];
break;
case 1: // one-layers on TB 0, two on TB 1
......@@ -4721,6 +4759,20 @@ int generate_ue_dlsch_params_from_dci(uint8_t subframe,
LOG_E(PHY,"Illegal number of antennas for eNB %d\n",frame_parms->nb_antennas_tx_eNB);
}
if (mcs1 <= 28)
dlsch0_harq->Qm = get_Qm(mcs1);
else if (mcs1<=31)
dlsch0_harq->Qm = (mcs1-28)<<1;
else
LOG_E(PHY,"invalid mcs1 %d\n",mcs1);
if (mcs2 <= 28)
dlsch1_harq->Qm = get_Qm(mcs2);
else if (mcs2<=31)
dlsch1_harq->Qm = (mcs2-28)<<1;
else
LOG_E(PHY,"invalid mcs2 %d\n",mcs2);
// printf("Format 2A: NPRB=%d (rballoc %x,mcs1 %d, mcs2 %d, frame_type %d N_RB_DL %d,active %d/%d)\n",NPRB,rballoc,mcs1,mcs2,frame_parms->frame_type,frame_parms->N_RB_DL,dlsch0->active,dlsch1->active);
//printf("UE (%x/%d): Subframe %d Format2A DCI: ndi1 %d, old_ndi1 %d, ndi2 %d, old_ndi2 %d (first tx1 %d, first tx2 %d) harq_status1 %d, harq_status2 %d\n",dlsch0->rnti,harq_pid,subframe,ndi,dlsch0_harq->DCINdi,
// dlsch0_harq->first_tx,dlsch1_harq->first_tx,dlsch0_harq->status,dlsch1_harq->status);
......
......@@ -515,6 +515,8 @@ typedef struct {
uint8_t round;
/// MCS format for this DLSCH
uint8_t mcs;
/// Qm (modulation order) for this DLSCH
uint8_t Qm;
/// Redundancy-version of the current sub-frame
uint8_t rvidx;
/// MIMO mode for this DLSCH
......
......@@ -244,8 +244,6 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
*/
A = harq_process->TBS; //2072 for QPSK 1/3
// mod_order = get_Qm(harq_process->mcs);
ret = dlsch->max_turbo_iterations;
......@@ -278,8 +276,33 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
err_flag = 0;
r_offset = 0;
unsigned char bw_scaling =1;
switch (frame_parms->N_RB_DL) {
case 6:
bw_scaling =16;
break;
case 25:
bw_scaling =4;
break;
case 50:
bw_scaling =2;
break;
default:
bw_scaling =1;
break;
}
if (harq_process->C >= MAX_NUM_DLSCH_SEGMENTS/bw_scaling) {
LOG_E(PHY,"Illegal harq_process->C %d > %d\n",harq_process->C,MAX_NUM_DLSCH_SEGMENTS/bw_scaling);
return((1+dlsch->max_turbo_iterations));
}
for (r=0; r<harq_process->C; r++) {
// Get Turbo interleaver parameters
if (r<harq_process->Cminus)
Kr = harq_process->Kminus;
......@@ -316,7 +339,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
harq_pid,r, G,
Kr*3,
harq_process->TBS,
get_Qm(harq_process->mcs),
harq_process->Qm,
harq_process->nb_rb,
harq_process->Nl,
harq_process->rvidx,
......@@ -335,7 +358,7 @@ uint32_t dlsch_decoding(PHY_VARS_UE *phy_vars_ue,
dlsch->Kmimo,
harq_process->rvidx,
(harq_process->round==0)?1:0,
get_Qm(harq_process->mcs),
harq_process->Qm,
harq_process->Nl,
r,
&E)==-1) {
......
......@@ -325,7 +325,7 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
frame_parms,
symbol,
first_symbol_flag,
get_Qm(dlsch0_harq->mcs),
dlsch0_harq->Qm,
nb_rb,
lte_ue_pdsch_vars[eNB_id]->log2_maxh,
phy_measurements); // log2_maxh+I0_shift
......@@ -380,7 +380,7 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
avg, symbol, nb_rb);
// LOG_D(PHY,"llr_offset = %d\n",offset_mumimo_llr_drange[dlsch0_harq->mcs][(dlsch1_harq->mcs>>1)-1]);
avg[0] = log2_approx(avg[0]) - 13 + offset_mumimo_llr_drange[dlsch0_harq->mcs][(get_Qm(dlsch1_harq->mcs)>>1)-1];
avg[0] = log2_approx(avg[0]) - 13 + offset_mumimo_llr_drange[dlsch0_harq->mcs][(dlsch1_harq->Qm>>1)-1];
lte_ue_pdsch_vars[eNB_id]->log2_maxh = cmax(avg[0],0);
// printf("log2_maxh =%d\n",lte_ue_pdsch_vars[eNB_id]->log2_maxh);
......@@ -391,8 +391,8 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
phy_measurements,
eNB_id,
symbol,
get_Qm(dlsch0_harq->mcs),
get_Qm(dlsch1_harq->mcs),
dlsch0_harq->Qm,
dlsch1_harq->Qm,
dlsch0_harq->round,
nb_rb,
lte_ue_pdsch_vars[eNB_id]->log2_maxh);
......@@ -451,7 +451,7 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
phy_measurements,
eNB_id,
symbol,
get_Qm(dlsch0_harq->mcs),
dlsch0_harq->Qm,
nb_rb,
lte_ue_pdsch_vars[eNB_id]->log2_maxh,
dlsch0_harq->dl_power_off);
......@@ -526,7 +526,7 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
phy_measurements,
eNB_id,
symbol,
get_Qm(dlsch0_harq->mcs),
dlsch0_harq->Qm,
nb_rb,
lte_ue_pdsch_vars[eNB_id]->log2_maxh,
1);
......@@ -599,7 +599,7 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
// printf("LLR");
switch (get_Qm(dlsch0_harq->mcs)) {
switch (dlsch0_harq->Qm) {
case 2 :
if (dlsch0_harq->mimo_mode != LARGE_CDD) {
if (dual_stream_flag == 0)
......@@ -643,7 +643,7 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
} else { // TM3
DevAssert(dlsch1_harq);
if (get_Qm(dlsch1_harq->mcs) == 2) {
if (dlsch1_harq->Qm == 2) {
/* dlsch_qpsk_llr(frame_parms,
lte_ue_pdsch_vars[eNB_id]->rxdataF_comp0,
lte_ue_pdsch_vars[eNB_id]->llr[0],
......@@ -667,7 +667,7 @@ int rx_pdsch(PHY_VARS_UE *phy_vars_ue,
symbol,first_symbol_flag,nb_rb,
adjust_G2(frame_parms,dlsch1_harq->rb_alloc,2,subframe,symbol),
lte_ue_pdsch_vars[eNB_id]->llr128_2ndstream);
} else if (get_Qm(dlsch1_harq->mcs) == 4) {
} else if (dlsch1_harq->Qm == 4) {
dlsch_qpsk_16qam_llr(frame_parms,
lte_ue_pdsch_vars[eNB_id]->rxdataF_comp0,
lte_ue_pdsch_vars[eNB_id]->rxdataF_comp1[dlsch0_harq->round],
......
......@@ -52,7 +52,7 @@
#include "common_lib.h"
extern openair0_config_t openair0_cfg[];
#endif
//#define DEBUG_INITIAL_SYNCH
#define DEBUG_INITIAL_SYNCH
int pbch_detection(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
{
......@@ -292,6 +292,8 @@ int initial_sync(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
frame_parms->frame_type=FDD;
init_frame_parms(frame_parms,1);
// write_output("rxdata0.m","rxd0",phy_vars_ue->lte_ue_common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
#ifdef OAI_USRP
for (aarx = 0; aarx<frame_parms->nb_antennas_rx;aarx++) {
rxdata128 = (__m128i*)phy_vars_ue->lte_ue_common_vars.rxdata[aarx];
......@@ -304,6 +306,7 @@ int initial_sync(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
frame_parms,
(int *)&phy_vars_ue->lte_ue_common_vars.eNb_id);
// write_output("rxdata1.m","rxd1",phy_vars_ue->lte_ue_common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
if (sync_pos >= frame_parms->nb_prefix_samples)
sync_pos2 = sync_pos - frame_parms->nb_prefix_samples;
else
......@@ -361,6 +364,7 @@ int initial_sync(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
init_frame_parms(&phy_vars_ue->lte_frame_parms,1);
lte_gold(frame_parms,phy_vars_ue->lte_gold_table[0],frame_parms->Nid_cell);
ret = pbch_detection(phy_vars_ue,mode);
// write_output("rxdata2.m","rxd2",phy_vars_ue->lte_ue_common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
#ifdef DEBUG_INITIAL_SYNCH
LOG_I(PHY,"FDD Normal prefix: CellId %d metric %d, phase %d, flip %d, pbch %d\n",
......@@ -407,7 +411,7 @@ int initial_sync(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
init_frame_parms(&phy_vars_ue->lte_frame_parms,1);
lte_gold(frame_parms,phy_vars_ue->lte_gold_table[0],frame_parms->Nid_cell);
ret = pbch_detection(phy_vars_ue,mode);
// write_output("rxdata3.m","rxd3",phy_vars_ue->lte_ue_common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
#ifdef DEBUG_INITIAL_SYNCH
LOG_I(PHY,"FDD Extended prefix: CellId %d metric %d, phase %d, flip %d, pbch %d\n",
frame_parms->Nid_cell,metric_fdd_ecp,phase_fdd_ecp,flip_fdd_ecp,ret);
......@@ -454,7 +458,7 @@ int initial_sync(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
lte_gold(frame_parms,phy_vars_ue->lte_gold_table[0],frame_parms->Nid_cell);
ret = pbch_detection(phy_vars_ue,mode);
// write_output("rxdata4.m","rxd4",phy_vars_ue->lte_ue_common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
#ifdef DEBUG_INITIAL_SYNCH
LOG_I(PHY,"TDD Normal prefix: CellId %d metric %d, phase %d, flip %d, pbch %d\n",
......@@ -501,6 +505,7 @@ int initial_sync(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
lte_gold(frame_parms,phy_vars_ue->lte_gold_table[0],frame_parms->Nid_cell);
ret = pbch_detection(phy_vars_ue,mode);
// write_output("rxdata5.m","rxd5",phy_vars_ue->lte_ue_common_vars.rxdata[0],10*frame_parms->samples_per_tti,1,1);
#ifdef DEBUG_INITIAL_SYNCH
LOG_I(PHY,"TDD Extended prefix: CellId %d metric %d, phase %d, flip %d, pbch %d\n",
frame_parms->Nid_cell,metric_tdd_ecp,phase_tdd_ecp,flip_tdd_ecp,ret);
......@@ -590,6 +595,7 @@ int initial_sync(PHY_VARS_UE *phy_vars_ue, runmode_t mode)
}
// exit_fun("debug exit");
return ret;
}
......@@ -33,23 +33,6 @@
#define SOFFSET 0
void rescale(int16_t *input,int length)
{
#if defined(__x86_64__) || defined(__i386__)
__m128i *input128 = (__m128i *)input;
#elif defined(__arm__)
int16x8_t *input128 = (int16x8_t *)input;
#endif
int i;
for (i=0; i<length>>2; i++) {
#if defined(__x86_64__) || defined(__i386__)
input128[i] = _mm_srai_epi16(input128[i],4);
#elif defined(__arm__)
input128[i] = vshrq_n_s16(input128[i],4);
#endif
}
}
int slot_fep(PHY_VARS_UE *phy_vars_ue,
unsigned char l,
......@@ -148,18 +131,11 @@ int slot_fep(PHY_VARS_UE *phy_vars_ue,
memcpy((void *)tmp_dft_in,
(void *)&ue_common_vars->rxdata[aa][(rx_offset-nb_prefix_samples0) % frame_length_samples],
frame_parms->ofdm_symbol_size*sizeof(int));
#ifdef OAI_USRP
rescale((int16_t *)tmp_dft_in,
frame_parms->ofdm_symbol_size);
#endif
dft((int16_t *)tmp_dft_in,
(int16_t *)&ue_common_vars->rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
} else { // use dft input from RX buffer directly
start_meas(&phy_vars_ue->rx_dft_stats);
#ifdef OAI_USRP
rescale((int16_t *)&ue_common_vars->rxdata[aa][(rx_offset-nb_prefix_samples0) % frame_length_samples],
frame_parms->ofdm_symbol_size+nb_prefix_samples0);
#endif
dft((int16_t *)&ue_common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
(int16_t *)&ue_common_vars->rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
stop_meas(&phy_vars_ue->rx_dft_stats);
......@@ -186,17 +162,10 @@ int slot_fep(PHY_VARS_UE *phy_vars_ue,
memcpy((void *)tmp_dft_in,
(void *)&ue_common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
frame_parms->ofdm_symbol_size*sizeof(int));
#ifdef OAI_USRP
rescale((int16_t *)tmp_dft_in,
frame_parms->ofdm_symbol_size);
#endif
dft((int16_t *)tmp_dft_in,
(int16_t *)&ue_common_vars->rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
} else { // use dft input from RX buffer directly
#ifdef OAI_USRP
rescale((int16_t *)&ue_common_vars->rxdata[aa][(rx_offset-nb_prefix_samples) % frame_length_samples],
frame_parms->ofdm_symbol_size+nb_prefix_samples);
#endif
dft((int16_t *)&ue_common_vars->rxdata[aa][(rx_offset) % frame_length_samples],
(int16_t *)&ue_common_vars->rxdataF[aa][frame_parms->ofdm_symbol_size*symbol],1);
}
......
......@@ -114,7 +114,7 @@ typedef struct {
int32_t freq_offset;
uint32_t tx_rx_switch_point;
uint32_t manual_timing_advance; /// 1 to override automatic timing advance
uint32_t timing_advance;
int32_t timing_advance;
uint32_t dual_tx; /// 1 for dual-antenna TX, 0 for single-antenna TX
uint32_t tdd; /// 1 for TDD mode, 0 for FDD mode
uint32_t rx_rf_mode;
......
This diff is collapsed.
......@@ -163,7 +163,7 @@ void pusch_power_cntl(PHY_VARS_UE *phy_vars_ue,uint8_t subframe,uint8_t eNB_id,u
phy_vars_ue->ulsch_ue[eNB_id]->Po_PUSCH += (mac_xface->get_Po_NOMINAL_PUSCH(phy_vars_ue->Mod_id,0) + PL);
LOG_I(PHY,"[UE %d][RAPROC] frame %d, subframe %d: Msg3 Po_PUSCH %d dBm (%d,%d,100*PL=%d,%d,%d)\n",
LOG_D(PHY,"[UE %d][RAPROC] frame %d, subframe %d: Msg3 Po_PUSCH %d dBm (%d,%d,100*PL=%d,%d,%d)\n",
phy_vars_ue->Mod_id,phy_vars_ue->frame_tx,subframe,phy_vars_ue->ulsch_ue[eNB_id]->Po_PUSCH,
100*mac_xface->get_Po_NOMINAL_PUSCH(phy_vars_ue->Mod_id,0),
hundred_times_log10_NPRB[nb_rb-1],
......@@ -182,7 +182,7 @@ void pusch_power_cntl(PHY_VARS_UE *phy_vars_ue,uint8_t subframe,uint8_t eNB_id,u
else if (phy_vars_ue->ulsch_ue[eNB_id]->PHR > 40)
phy_vars_ue->ulsch_ue[eNB_id]->PHR = 40;
LOG_I(PHY,"[UE %d][PUSCH %d] frame %d, subframe %d: Po_PUSCH %d dBm : tx power %d, Po_NOMINAL_PUSCH %d,log10(NPRB) %f,PHR %d, PL %d, alpha*PL %f,delta_IF %f,f_pusch %d\n",
LOG_D(PHY,"[UE %d][PUSCH %d] frame %d, subframe %d: Po_PUSCH %d dBm : tx power %d, Po_NOMINAL_PUSCH %d,log10(NPRB) %f,PHR %d, PL %d, alpha*PL %f,delta_IF %f,f_pusch %d\n",
phy_vars_ue->Mod_id,harq_pid,phy_vars_ue->frame_tx,subframe,
phy_vars_ue->ulsch_ue[eNB_id]->Po_PUSCH,
phy_vars_ue->tx_power_max_dBm,
......
......@@ -244,7 +244,7 @@ void Msg3_tx(module_id_t module_idP,uint8_t CC_id,frame_t frameP, uint8_t eNB_id
}
// start contention resolution timer
LOG_I(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Setting contention resolution timer\n",module_idP,frameP);
LOG_D(MAC,"[UE %d][RAPROC] Frame %d : Msg3_tx: Setting contention resolution timer\n",module_idP,frameP);
UE_mac_inst[module_idP].RA_contention_resolution_cnt = 0;
UE_mac_inst[module_idP].RA_contention_resolution_timer_active = 1;
#if defined(USER_MODE) && defined(OAI_EMU)
......@@ -448,9 +448,45 @@ PRACH_RESOURCES_t *ue_get_rach(module_id_t module_idP,int CC_id,frame_t frameP,
UE_mac_inst[module_idP].RA_PREAMBLE_TRANSMISSION_COUNTER++;
UE_mac_inst[module_idP].RA_prach_resources.ra_PREAMBLE_RECEIVED_TARGET_POWER +=
(rach_ConfigCommon->powerRampingParameters.powerRampingStep<<1); // 2dB increments in ASN.1 definition
if (UE_mac_inst[module_idP].RA_PREAMBLE_TRANSMISSION_COUNTER == rach_ConfigCommon->ra_SupervisionInfo.preambleTransMax) {
LOG_D(MAC,"[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n",module_idP,frameP,rach_ConfigCommon->ra_SupervisionInfo.preambleTransMax);
int preambleTransMax;
switch (rach_ConfigCommon->ra_SupervisionInfo.preambleTransMax) {
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n3:
preambleTransMax = 3;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n4:
preambleTransMax = 4;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n5:
preambleTransMax = 5;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n6:
preambleTransMax = 6;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n7:
preambleTransMax = 7;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n8:
preambleTransMax = 8;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n10:
preambleTransMax = 10;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n20:
preambleTransMax = 20;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n50:
preambleTransMax = 50;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n100:
preambleTransMax = 100;
break;
case RACH_ConfigCommon__ra_SupervisionInfo__preambleTransMax_n200:
preambleTransMax = 200;
break;
}
if (UE_mac_inst[module_idP].RA_PREAMBLE_TRANSMISSION_COUNTER == preambleTransMax) {
LOG_D(MAC,"[UE %d] Frame %d: Maximum number of RACH attempts (%d)\n",module_idP,frameP,preambleTransMax);
// send message to RRC
UE_mac_inst[module_idP].RA_PREAMBLE_TRANSMISSION_COUNTER=1;
UE_mac_inst[module_idP].RA_prach_resources.ra_PREAMBLE_RECEIVED_TARGET_POWER = get_Po_NOMINAL_PUSCH(module_idP,CC_id);
......
......@@ -1435,7 +1435,7 @@ void ue_get_sdu(module_id_t module_idP,int CC_id,frame_t frameP,sub_frame_t subf
bsr_l,
post_padding); // long_bsr
LOG_I(MAC,
LOG_D(MAC,
"[UE %d] Generate header :bufflen %d sdu_length_total %d, num_sdus %d, sdu_lengths[0] %d, sdu_lcids[0] %d => payload offset %d, dcch_header_len %d, dtch_header_len %d, padding %d,post_padding %d, bsr len %d, phr len %d, reminder %d \n",
module_idP,buflen, sdu_length_total,num_sdus,sdu_lengths[0],sdu_lcids[0],payload_offset, dcch_header_len, dtch_header_len,
short_padding,post_padding, bsr_len, phr_len,buflen-sdu_length_total-payload_offset);
......
......@@ -362,7 +362,7 @@ mac_rrc_lite_data_ind(
if(eNB_flagP == ENB_FLAG_NO) {
if(srb_idP == BCCH) {
LOG_T(RRC,"[UE %d] Received SDU for BCCH on SRB %d from eNB %d\n",module_idP,srb_idP,eNB_indexP);
LOG_D(RRC,"[UE %d] Received SDU for BCCH on SRB %d from eNB %d\n",module_idP,srb_idP,eNB_indexP);
#if defined(ENABLE_ITTI)
{
......
......@@ -189,9 +189,9 @@ typedef enum HO_STATE_e {
typedef struct UE_RRC_INFO_s {
UE_STATE_t State;
uint8_t SIB1Status;
uint8_t SIB1systemInfoValueTag;
uint8_t SIStatus;
uint32_t SIStatus;
uint32_t SIcnt;
#ifdef Rel10
uint8_t MCCHStatus[8]; // MAX_MBSFN_AREA
#endif
......
This diff is collapsed.
......@@ -283,7 +283,7 @@ double rx_gain[MAX_NUM_CCs][4] = {{110,0,0,0}};
#endif
double sample_rate=30.72e6;
double bw = 14e6;
double bw = 10.0e6;
static int tx_max_power[MAX_NUM_CCs]; /* = {0,0}*/;
......@@ -2537,7 +2537,7 @@ int main( int argc, char **argv )
}
#endif
#ifdef NAS_NETLINK
#ifdef PDCP_USE_NETLINK
netlink_init();
#endif
......@@ -2774,6 +2774,7 @@ int main( int argc, char **argv )
if(frame_parms[0]->N_RB_DL == 100) {
sample_rate = 30.72e6;
bw = 10.0e6;
#ifndef EXMIMO
openair0_cfg[0].samples_per_packet = 2048;
samples_per_frame = 307200;
......@@ -2783,6 +2784,7 @@ int main( int argc, char **argv )
#endif
} else if(frame_parms[0]->N_RB_DL == 50) {
sample_rate = 15.36e6;
bw = 5.0e6;
#ifndef EXMIMO
openair0_cfg[0].samples_per_packet = 2048;
samples_per_frame = 153600;
......@@ -2791,6 +2793,7 @@ int main( int argc, char **argv )
#endif
} else if (frame_parms[0]->N_RB_DL == 25) {
sample_rate = 7.68e6;
bw = 2.5e6;
#ifndef EXMIMO
openair0_cfg[0].samples_per_packet = 1024;
samples_per_frame = 76800;
......@@ -2799,6 +2802,7 @@ int main( int argc, char **argv )
#endif
} else if (frame_parms[0]->N_RB_DL == 6) {
sample_rate = 1.92e6;
bw = 0.96e6;
#ifndef EXMIMO
openair0_cfg[0].samples_per_packet = 256;
samples_per_frame = 19200;
......@@ -2961,8 +2965,11 @@ int main( int argc, char **argv )
// connect the TX/RX buffers
if (UE_flag==1) {
openair_daq_vars.timing_advance = 0;
#ifdef OAI_USRP
openair_daq_vars.timing_advance = 160;
#else
openair_daq_vars.timing_advance = 170;
#endif
if (setup_ue_buffers(UE,&openair0_cfg[0],rf_map)!=0) {
printf("Error setting up eNB buffer\n");
exit(-1);
......
......@@ -390,6 +390,7 @@ static void *UE_thread_synch(void *arg)
case pbch:
if (initial_sync( UE, UE->mode ) == 0) {
hw_slot_offset = (UE->rx_offset<<1) / UE->lte_frame_parms.samples_per_tti;
......@@ -410,15 +411,23 @@ static void *UE_thread_synch(void *arg)
switch(UE->lte_frame_parms.N_RB_DL) {
case 6:
openair0_cfg[0].sample_rate =1.92e6;
openair0_cfg[0].rx_bw =.96e6;
openair0_cfg[0].tx_bw =.96e6;
break;
case 25:
openair0_cfg[0].sample_rate=7.68e6;
openair0_cfg[0].sample_rate =7.68e6;
openair0_cfg[0].rx_bw =2.5e6;
openair0_cfg[0].tx_bw =2.5e6;
break;
case 50:
openair0_cfg[0].sample_rate=15.36e6;
openair0_cfg[0].sample_rate =15.36e6;
openair0_cfg[0].rx_bw =5.0e6;
openair0_cfg[0].tx_bw =5.0e6;
break;
case 100:
openair0_cfg[0].sample_rate=30.72e6;
openair0_cfg[0].rx_bw=10.0e6;
openair0_cfg[0].tx_bw=10.0e6;
break;
}
......@@ -687,6 +696,27 @@ static void *UE_thread_tx(void *arg)
* \param arg is a pointer to a \ref PHY_VARS_UE structure.
* \returns a pointer to an int. The storage is not on the heap and must not be freed.
*/
#ifdef OAI_USRP
void rescale(int16_t *input,int length)
{
#if defined(__x86_64__) || defined(__i386__)
__m128i *input128 = (__m128i *)input;
#elif defined(__arm__)
int16x8_t *input128 = (int16x8_t *)input;
#endif
int i;
for (i=0; i<length>>2; i++) {
#if defined(__x86_64__) || defined(__i386__)
input128[i] = _mm_srai_epi16(input128[i],4);
#elif defined(__arm__)
input128[i] = vshrq_n_s16(input128[i],4);
#endif
}
}
#endif
static void *UE_thread_rx(void *arg)
{
static int UE_thread_rx_retval;
......@@ -767,11 +797,78 @@ static void *UE_thread_rx(void *arg)
for (i=0; i<2; i++) {
if ((subframe_select( &UE->lte_frame_parms, UE->slot_rx>>1 ) == SF_DL) ||
(UE->lte_frame_parms.frame_type == FDD)) {
#ifdef OAI_USRP
// this does the adjustments of RX signal amplitude to bring into least 12 significant bits
int slot_length = UE->lte_frame_parms.samples_per_tti>>1;
int rx_offset = (UE->slot_rx)*slot_length + UE->rx_offset;
int frame_length = UE->lte_frame_parms.samples_per_tti*10;
int aa;
if (rx_offset > frame_length)
rx_offset-=frame_length;
if (rx_offset >= 0) {
if (rx_offset + slot_length < frame_length)
for (aa=0;aa<UE->lte_frame_parms.nb_antennas_rx;aa++)
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][rx_offset&(~0x3)],
slot_length);
else {
int diff = rx_offset + slot_length - frame_length;
for (aa=0;aa<UE->lte_frame_parms.nb_antennas_rx;aa++){
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][rx_offset&(~0x3)],
slot_length-diff);
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][0],
diff);
}
}
}
else {
for (aa=0;aa<UE->lte_frame_parms.nb_antennas_rx;aa++){
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][(frame_length+rx_offset)&(~0x3)],
-rx_offset);
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][0],
slot_length+rx_offset);
}
}
#endif
phy_procedures_UE_RX( UE, 0, 0, UE->mode, no_relay, NULL );
}
if ((subframe_select( &UE->lte_frame_parms, UE->slot_rx>>1 ) == SF_S) &&
((UE->slot_rx&1) == 0)) {
#ifdef OAI_USRP
// this does the adjustments of RX signal amplitude to bring into least 12 significant bits
int slot_length = UE->lte_frame_parms.samples_per_tti>>1;
int rx_offset = (UE->slot_rx)*slot_length + UE->rx_offset;
int frame_length = UE->lte_frame_parms.samples_per_tti*10;
if (rx_offset > frame_length)
rx_offset-=frame_length;
int aa;
if (rx_offset >= 0) {
if (rx_offset + slot_length < frame_length)
for (aa=0;aa<UE->lte_frame_parms.nb_antennas_rx;aa++)
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][rx_offset&(~0x3)],
slot_length);
else {
int diff = rx_offset + slot_length - frame_length;
for (aa=0;aa<UE->lte_frame_parms.nb_antennas_rx;aa++){
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][rx_offset&(~0x3)],
slot_length-diff);
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][0],
diff);
}
}
}
else {
for (aa=0;aa<UE->lte_frame_parms.nb_antennas_rx;aa++){
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][(frame_length+rx_offset)&(~0x3)],
-rx_offset);
rescale((int16_t*)&UE->lte_ue_common_vars.rxdata[aa][0],
slot_length+rx_offset);
}
}
#endif
phy_procedures_UE_RX( UE, 0, 0, UE->mode, no_relay, NULL );
}
......@@ -938,9 +1035,9 @@ void *UE_thread(void *arg)
for (int i=0; i<UE->lte_frame_parms.nb_antennas_rx; i++)
rxp[i] = (dummy_dump==0) ? (void*)&rxdata[i][rxpos] : (void*)dummy[i];
// if (dummy_dump == 0)
// printf("writing %d samples to %d\n",spp - ((first_rx==1) ? rx_off_diff : 0),rxpos);
/* if (dummy_dump == 0)
printf("writing %d samples to %d (first_rx %d)\n",spp - ((first_rx==1) ? rx_off_diff : 0),rxpos,first_rx);
*/
rxs = openair0.trx_read_func(&openair0,
&timestamp,
rxp,
......@@ -952,7 +1049,9 @@ void *UE_thread(void *arg)
return &UE_thread_retval;
}
rx_off_diff = 0;
if (rx_off_diff !=0)
LOG_I(PHY,"frame %d, rx_offset %d, rx_off_diff %d\n",UE->frame_rx,UE->rx_offset,rx_off_diff);
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME( VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_READ, 0 );
// Transmit TX buffer based on timestamp from RX
......@@ -968,7 +1067,7 @@ void *UE_thread(void *arg)
openair0.trx_write_func(&openair0,
(timestamp+spp*tx_delay-tx_forward_nsamps),
txp,
spp,
spp - ((first_rx==1) ? rx_off_diff : 0),
UE->lte_frame_parms.nb_antennas_tx,
1);
......@@ -980,6 +1079,9 @@ void *UE_thread(void *arg)
rt_sleep_ns(1000000);
#endif
rx_off_diff = 0;
first_rx = 0;
rxpos += spp;
txpos += spp;
......@@ -1128,6 +1230,7 @@ void *UE_thread(void *arg)
rx_off_diff = 0;
LTE_DL_FRAME_PARMS *frame_parms = &UE->lte_frame_parms; // for macro FRAME_LENGTH_COMPLEX_SAMPLES
// LOG_I(PHY,"UE->rx_offset %d\n",UE->rx_offset);
if ((UE->rx_offset > RX_OFF_MAX) && (start_rx_stream == 0)) {
start_rx_stream=1;
frame=0;
......@@ -1148,11 +1251,20 @@ void *UE_thread(void *arg)
#endif
UE->rx_offset=0;
tx_enabled = 1;
} else if ((UE->rx_offset < RX_OFF_MIN) && (start_rx_stream==1) && (rx_correction_timer == 0)) {
} else if ((UE->rx_offset<(FRAME_LENGTH_COMPLEX_SAMPLES/2)) &&
(UE->rx_offset > RX_OFF_MIN) &&
(start_rx_stream==1) &&
(rx_correction_timer == 0)) {
rx_off_diff = -UE->rx_offset + RX_OFF_MIN;
LOG_D(PHY,"UE->rx_offset %d > %d, diff %d\n",UE->rx_offset,RX_OFF_MIN,rx_off_diff);
rx_correction_timer = 5;
} else if ((UE->rx_offset > (FRAME_LENGTH_COMPLEX_SAMPLES-RX_OFF_MAX)) && (start_rx_stream==1) && (rx_correction_timer == 0)) {
rx_off_diff = FRAME_LENGTH_COMPLEX_SAMPLES-UE->rx_offset;
} else if ((UE->rx_offset>(FRAME_LENGTH_COMPLEX_SAMPLES/2)) &&
(UE->rx_offset < (FRAME_LENGTH_COMPLEX_SAMPLES-RX_OFF_MIN)) &&
(start_rx_stream==1) &&
(rx_correction_timer == 0)) { // moving to the left so drop rx_off_diff samples
rx_off_diff = FRAME_LENGTH_COMPLEX_SAMPLES - RX_OFF_MIN - UE->rx_offset;
LOG_D(PHY,"UE->rx_offset %d < %d, diff %d\n",UE->rx_offset,FRAME_LENGTH_COMPLEX_SAMPLES-RX_OFF_MIN,rx_off_diff);(UE->rx_offset>(FRAME_LENGTH_COMPLEX_SAMPLES/2));
rx_correction_timer = 5;
}
......
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