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wangjie
OpenXG-RAN
Commits
4d47e3da
Commit
4d47e3da
authored
4 years ago
by
Raymond Knopp
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IF4p5 testing. seems to work again with fixes after merge with develop
parent
1bf9ea6d
x2_handle_sctp_shutdown
512-dataplane-bug-in-l2nfapi_nos1
FR2_NSA
NRUE_usedlschparallel
NR_2port_CSIRS
NR_CSIRS_tomerge
NR_F1C_F1U_extensions
NR_RRCReconfiguration_BWP
NR_UE_PUCCH_bugfixes
NR_UE_SA
NR_UE_SSB_meas
NR_UE_reworking_UCI_procedures
NR_gNB_initial_MIB_fix
NR_new_ul_antennaports
NR_phytest_bugfixes
NR_reworking_UL_antennaports
RFquality
Test_SA_5GREC
add-ru-docker-image
avxllr
bandwidth-testing
benetel_dpdk20
bugfix-nr-t-reordering
ci-add-sabox-support
ci-fix-module-ul-iperf
ci_benetel_longrun_limits
ci_fix_iperf_for_module
ci_hotfix_module_ue_ip_address
ci_improve_module_ctl
ci_nsa_2x2_implem
ci_nsa_benetel
ci_nsa_fixes
ci_nsa_pipes_improve
ci_nsa_test_integration_2021_wk19
ci_nsa_traces
ci_nsa_uplink
ci_sa_rfsim_test
ci_test_5GREC
ci_test_nsa_2x2
ci_test_nsa_on_develop
ci_testinfra_as_code
ci_update_build_nasmesh
code-cleanup-20210716
debug-UL-5GRECORDS
debug_UL_signal
develop
develop-NR_SA_F1AP_5GRECORDS
develop-NR_SA_F1AP_5GRECORDS-abs
develop-NR_SA_F1AP_5GRECORDS-hs1
develop-NR_SA_F1AP_5GRECORDS-lts
develop-NR_SA_F1AP_5GRECORDS-lts-wf
develop-NR_SA_F1AP_5GRECORDS_100M
develop-NR_SA_F1AP_5GRECORDS_lfq_0607
develop-NSA_SA_fixes
develop-aw2sori
develop_fpga_ldpc
dongzhanyi-zte-develop1
episys-merge
fedora-gen-kernel-fix
fix-check
fix-compile
fix-lte-ue-modem-in-docker-container
fix-physim-run-script-on-cluster
fix-retransmission-rbg
fix_nr_ulsim
flexran-rtc-repo-is-public
hack-bch-no-sched-sf-0
integration_2021_wk19
integration_2021_wk20_a
integration_2021_wk22
integration_2021_wk23
integration_2021_wk27
integration_2021_wk28
integration_2021_wk30
integration_2021_wk30_b
ldpc_offload_t1
migrate-vm-pipeline-to-bionic
nfapi_nr_arch_mod
nr-dl-mimo-2layer
nr-pdcp-small-bugfixes
nr_improve_chanest
nr_ue_remove_high_speed_flag
oairu
phy-asan-fixes
prb_based_dl_channel_estimation
rh_ci_test_rfsim_sa
scs_60_iisc
test-5GREC
test-nsa-benetel
2021.w30
2021.w29
2021.w28
2021.w27
2021.w26
2021.w25
2021.w24
2021.w23
2021.w22
2021.w20
2021.w19
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1 changed file
with
9 additions
and
10 deletions
+9
-10
targets/RT/USER/lte-enb.c
targets/RT/USER/lte-enb.c
+9
-10
No files found.
targets/RT/USER/lte-enb.c
View file @
4d47e3da
...
...
@@ -1155,7 +1155,7 @@ void init_transport(PHY_VARS_eNB *eNB) {
void
init_eNB_afterRU
(
void
)
{
int
inst
,
CC_id
,
ru_id
,
i
,
aa
;
int
inst
,
CC_id
,
i
,
aa
;
PHY_VARS_eNB
*
eNB
;
LOG_I
(
PHY
,
"%s() RC.nb_inst:%d
\n
"
,
__FUNCTION__
,
RC
.
nb_inst
);
...
...
@@ -1165,13 +1165,14 @@ void init_eNB_afterRU(void) {
for
(
CC_id
=
0
;
CC_id
<
RC
.
nb_CC
[
inst
];
CC_id
++
)
{
LOG_I
(
PHY
,
"RC.nb_CC[inst:%d][CC_id:%d]:%p
\n
"
,
inst
,
CC_id
,
RC
.
eNB
[
inst
][
CC_id
]);
eNB
=
RC
.
eNB
[
inst
][
CC_id
];
phy_init_lte_eNB
(
eNB
,
0
,
0
);
// map antennas and PRACH signals to eNB RX
if
(
0
)
AssertFatal
(
eNB
->
num_RU
>
0
,
"Number of RU attached to eNB %d is zero
\n
"
,
eNB
->
Mod_id
);
// map antennas and PRACH signals to eNB RX
LOG_I
(
PHY
,
"Mapping RX ports from %d RUs to eNB %d
\n
"
,
eNB
->
num_RU
,
eNB
->
Mod_id
);
eNB
->
frame_parms
.
nb_antennas_rx
=
0
;
LOG_I
(
PHY
,
"eNB->num_RU:%d
\n
"
,
eNB
->
num_RU
);
AssertFatal
(
eNB
->
num_RU
>
0
,
"Number of RU attached to eNB %d is zero
\n
"
,
eNB
->
Mod_id
);
for
(
int
ru_id
=
0
,
aa
=
0
;
ru_id
<
eNB
->
num_RU
;
ru_id
++
)
eNB
->
frame_parms
.
nb_antennas_rx
+=
eNB
->
RU_list
[
ru_id
]
->
nb_rx
;
phy_init_lte_eNB
(
eNB
,
0
,
0
);
LOG_I
(
PHY
,
"Overwriting eNB->prach_vars.rxsigF[0]:%p
\n
"
,
eNB
->
prach_vars
.
rxsigF
[
0
]);
eNB
->
prach_vars
.
rxsigF
[
0
]
=
(
int16_t
**
)
malloc16
(
64
*
sizeof
(
int16_t
*
));
...
...
@@ -1180,10 +1181,8 @@ void init_eNB_afterRU(void) {
eNB
->
prach_vars_br
.
rxsigF
[
ce_level
]
=
(
int16_t
**
)
malloc16
(
64
*
sizeof
(
int16_t
*
));
}
LOG_I
(
PHY
,
"eNB->num_RU:%d
\n
"
,
eNB
->
num_RU
);
for
(
ru_id
=
0
,
aa
=
0
;
ru_id
<
eNB
->
num_RU
;
ru_id
++
)
{
eNB
->
frame_parms
.
nb_antennas_rx
+=
eNB
->
RU_list
[
ru_id
]
->
nb_rx
;
for
(
int
ru_id
=
0
,
aa
=
0
;
ru_id
<
eNB
->
num_RU
;
ru_id
++
)
{
AssertFatal
(
eNB
->
RU_list
[
ru_id
]
->
common
.
rxdataF
!=
NULL
,
"RU %d : common.rxdataF is NULL
\n
"
,
...
...
@@ -1231,7 +1230,7 @@ void init_eNB_afterRU(void) {
init_eNB_proc
(
inst
);
}
for
(
ru_id
=
0
;
ru_id
<
RC
.
nb_RU
;
ru_id
++
)
{
for
(
int
ru_id
=
0
;
ru_id
<
RC
.
nb_RU
;
ru_id
++
)
{
AssertFatal
(
RC
.
ru
[
ru_id
]
!=
NULL
,
"ru_id %d is null
\n
"
,
ru_id
);
RC
.
ru
[
ru_id
]
->
wakeup_rxtx
=
wakeup_rxtx
;
RC
.
ru
[
ru_id
]
->
wakeup_prach_eNB
=
wakeup_prach_eNB
;
...
...
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