Commit 7a7c1bcc authored by Robert Schmidt's avatar Robert Schmidt

Calculate TBS in pre-processor and use the results in post-proc

parent d8cecde9
dev 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA Fix_SA_SIB1 NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_initsync_fixes NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_PUCCH_MultiUE NR_RA_cleanup NR_RRCReconfiguration_BWP NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_UE_CONFIG_REQ_FIXES NR_UE_PUCCH_bugfixes NR_UE_SA NR_UE_SSB_meas NR_UE_dlsch_bugfix NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_Wireshark NR_beam_simulation NR_cleanup_PUCCH_resources NR_gNB_initial_MIB_fix NR_multiplexing_HARQ_CSI_PUCCH NR_new_ul_antennaports NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 PBCHNRTCFIX RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC add-dmrs-test add-ru-docker-image avxllr bandwidth-testing benetel_config_file_fix benetel_dpdk20 benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes bsr-fix bugfix-free-ra-process bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge ci-add-sabox-support ci-fix-module-ul-iperf ci-new-docker-pipeline ci-reduce-nb-vms ci-test ci_benetel_longrun_limits ci_benetel_test ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_2x2_implem ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_phytest ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_2x2 ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_update_build_nasmesh ci_vm_resource_fix cleanup_softmodem_main code-cleanup-20210716 debug-UL-5GRECORDS debug_UL_signal detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-NSA_SA_fixes develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-aw2sori develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop-wf-du develop_fpga_ldpc develop_stable disable_CSI_measrep docker-improvements-2021-april docker-no-cache-option dongzhanyi-zte-develop1 enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development fedora-gen-kernel-fix fft_bench_hotfix fix-check fix-compile fix-lte-ue-modem-in-docker-container fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-physim-run-script-on-cluster fix-quectel fix-realtime fix-retransmission-rbg fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_do_ra_data fix_nr_ulsim fix_rb_corruption fix_reestablishment fixes-CE-RLC-PDU-size fixgtpu flexran-rtc-repo-is-public git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-only-test gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-bch-no-sched-sf-0 hack-exit-gnb-when-no-enb-nsa integ-w13-test-rt-issue integration_2020_wk15 integration_2020_wk50 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integration_w5GC_CBRA_test inter-RRU-final itti-enhancement ldpc_offload_t1 lte-ulsch-bugfix lte_uplink_improvement migrate-cpp-check-container migrate-vm-pipeline-to-bionic minor-fix-doc-basic-sim msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new nr-bsr-fix nr-dl-mimo-2layer nr-dmrs-fixes nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-small-bugfixes nr-pdcp-srb-integrity nr-ra-fix nr-stats-print nrPBCHTCFix nrPbchTcFix nr_improve_chanest nr_power_measurement_fixes nr_ue_pdcp_fix nr_ue_remove_high_speed_flag nr_ul_pf nr_ul_scfdma oairu oairu-dockerfile-support openxg/develop phy-asan-fixes physim-build-deploy physim-deploy-handle-error-cases prb_based_dl_channel_estimation ptrs_rrc_config pusch-retrans-fix-ue recursive-cmake rh-ci-add-ue-parallelization rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins 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......@@ -452,9 +452,29 @@ void nr_ul_preprocessor_phytest(module_id_t module_id,
num_dmrs_cdm_grps_no_data,
ps);
sched_ctrl->sched_pusch.mcs = 9;
sched_ctrl->sched_pusch.rbStart = rbStart;
sched_ctrl->sched_pusch.rbSize = rbSize;
const int mcs = 9;
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
sched_pusch->mcs = mcs;
sched_pusch->rbStart = rbStart;
sched_pusch->rbSize = rbSize;
/* Calculate TBS from MCS */
sched_pusch->R = nr_get_code_rate_ul(mcs, ps->mcs_table);
sched_pusch->Qm = nr_get_Qm_ul(mcs, ps->mcs_table);
if (ps->pusch_Config->tp_pi2BPSK
&& ((ps->mcs_table == 3 && mcs < 2) || (ps->mcs_table == 4 && mcs < 6))) {
sched_pusch->R >>= 1;
sched_pusch->Qm <<= 1;
}
sched_pusch->tb_size = nr_compute_tbs(sched_pusch->Qm,
sched_pusch->R,
sched_pusch->rbSize,
ps->nrOfSymbols,
ps->N_PRB_DMRS * ps->num_dmrs_symb,
0, // nb_rb_oh
0,
1 /* NrOfLayers */)
>> 3;
/* mark the corresponding RBs as used */
for (int rb = rbStart; rb < rbStart + rbSize; rb++)
......
......@@ -551,9 +551,29 @@ void nr_simple_ulsch_preprocessor(module_id_t module_id,
num_dmrs_cdm_grps_no_data,
ps);
sched_ctrl->sched_pusch.mcs = 9;
sched_ctrl->sched_pusch.rbStart = rbStart;
sched_ctrl->sched_pusch.rbSize = rbSize;
const int mcs = 9;
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
sched_pusch->mcs = mcs;
sched_pusch->rbStart = rbStart;
sched_pusch->rbSize = rbSize;
/* Calculate TBS from MCS */
sched_pusch->R = nr_get_code_rate_ul(mcs, ps->mcs_table);
sched_pusch->Qm = nr_get_Qm_ul(mcs, ps->mcs_table);
if (ps->pusch_Config->tp_pi2BPSK
&& ((ps->mcs_table == 3 && mcs < 2) || (ps->mcs_table == 4 && mcs < 6))) {
sched_pusch->R >>= 1;
sched_pusch->Qm <<= 1;
}
sched_pusch->tb_size = nr_compute_tbs(sched_pusch->Qm,
sched_pusch->R,
sched_pusch->rbSize,
ps->nrOfSymbols,
ps->N_PRB_DMRS * ps->num_dmrs_symb,
0, // nb_rb_oh
0,
1 /* NrOfLayers */)
>> 3;
/* mark the corresponding RBs as used */
for (int rb = 0; rb < sched_ctrl->sched_pusch.rbSize; rb++)
......@@ -574,6 +594,8 @@ void nr_schedule_ulsch(module_id_t module_id,
const NR_UE_list_t *UE_list = &UE_info->list;
for (int UE_id = UE_list->head; UE_id >= 0; UE_id = UE_list->next[UE_id]) {
NR_UE_sched_ctrl_t *sched_ctrl = &UE_info->UE_sched_ctrl[UE_id];
/* dynamic PUSCH values (RB alloc, MCS, hence R, Qm, TBS) that change in
* every TTI are pre-populated by the preprocessor and used below */
NR_sched_pusch_t *sched_pusch = &sched_ctrl->sched_pusch;
if (sched_pusch->rbSize <= 0)
continue;
......@@ -593,28 +615,10 @@ void nr_schedule_ulsch(module_id_t module_id,
* through nr_save_pusch_fields() */
NR_sched_pusch_save_t *ps = &sched_ctrl->pusch_save;
/* Calculate TBS from MCS */
const uint8_t mcs = sched_pusch->mcs;
uint16_t R = nr_get_code_rate_ul(mcs, ps->mcs_table);
uint8_t Qm = nr_get_Qm_ul(mcs, ps->mcs_table);
if (ps->pusch_Config->tp_pi2BPSK
&& ((ps->mcs_table == 3 && mcs < 2) || (ps->mcs_table == 4 && mcs < 6))) {
R >>= 1;
Qm <<= 1;
}
const uint32_t tb_size = nr_compute_tbs(Qm,
R,
sched_pusch->rbSize,
ps->nrOfSymbols,
ps->N_PRB_DMRS * ps->num_dmrs_symb,
0, // nb_rb_oh
0,
1 /* NrOfLayers */) >> 3;
/* Statistics */
UE_info->mac_stats[UE_id].ulsch_rounds[cur_harq->round]++;
if (cur_harq->round == 0)
UE_info->mac_stats[UE_id].ulsch_total_bytes_scheduled += tb_size;
UE_info->mac_stats[UE_id].ulsch_total_bytes_scheduled += sched_pusch->tb_size;
/* PUSCH in a later slot, but corresponding DCI now! */
......@@ -646,9 +650,9 @@ void nr_schedule_ulsch(module_id_t module_id,
pusch_pdu->cyclic_prefix = 0;
/* FAPI: PUSCH information always included */
pusch_pdu->target_code_rate = R;
pusch_pdu->qam_mod_order = Qm;
pusch_pdu->mcs_index = mcs;
pusch_pdu->target_code_rate = sched_pusch->R;
pusch_pdu->qam_mod_order = sched_pusch->Qm;
pusch_pdu->mcs_index = sched_pusch->mcs;
pusch_pdu->mcs_table = ps->mcs_table;
pusch_pdu->transform_precoding = ps->transform_precoding;
if (ps->pusch_Config->dataScramblingIdentityPUSCH)
......@@ -702,7 +706,7 @@ void nr_schedule_ulsch(module_id_t module_id,
pusch_pdu->pusch_data.rv_index = nr_rv_round_map[cur_harq->round];
pusch_pdu->pusch_data.harq_process_id = harq_id;
pusch_pdu->pusch_data.new_data_indicator = cur_harq->ndi;
pusch_pdu->pusch_data.tb_size = tb_size;
pusch_pdu->pusch_data.tb_size = sched_pusch->tb_size;
pusch_pdu->pusch_data.num_cb = 0; //CBG not supported
/* PUSCH PTRS */
......
......@@ -321,6 +321,11 @@ typedef struct NR_sched_pusch {
/// MCS
uint8_t mcs;
/// TBS-related info
uint16_t R;
uint8_t Qm;
uint32_t tb_size;
} NR_sched_pusch_t;
typedef struct NR_UE_harq {
......
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