Commit b1937713 authored by Raymond Knopp's avatar Raymond Knopp

12-bit frequency-domain equalizer LUT. fix for log2_maxh in ULSCH receiver

parent d77f9ad0
x2_handle_sctp_shutdown 512-dataplane-bug-in-l2nfapi_nos1 FR2_NSA NRUE_usedlschparallel NR_2port_CSIRS NR_CSIRS_tomerge NR_F1C_F1U_extensions NR_RRCReconfiguration_BWP NR_UE_PUCCH_bugfixes NR_UE_SA NR_UE_SSB_meas NR_UE_reworking_UCI_procedures NR_gNB_initial_MIB_fix NR_new_ul_antennaports NR_phytest_bugfixes NR_reworking_UL_antennaports RFquality Test_SA_5GREC add-ru-docker-image avxllr bandwidth-testing benetel_dpdk20 bugfix-nr-t-reordering ci-add-sabox-support ci-fix-module-ul-iperf ci_benetel_longrun_limits ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_2x2_implem ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_sa_rfsim_test ci_test_5GREC ci_test_nsa_2x2 ci_test_nsa_on_develop ci_testinfra_as_code ci_update_build_nasmesh code-cleanup-20210716 debug-UL-5GRECORDS debug_UL_signal develop develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-NSA_SA_fixes develop-aw2sori develop_fpga_ldpc dongzhanyi-zte-develop1 episys-merge fedora-gen-kernel-fix fix-check fix-compile fix-lte-ue-modem-in-docker-container fix-physim-run-script-on-cluster fix-retransmission-rbg fix_nr_ulsim flexran-rtc-repo-is-public hack-bch-no-sched-sf-0 integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_2021_wk28 integration_2021_wk30 integration_2021_wk30_b ldpc_offload_t1 migrate-vm-pipeline-to-bionic nfapi_nr_arch_mod nr-dl-mimo-2layer nr-pdcp-small-bugfixes nr_improve_chanest nr_ue_remove_high_speed_flag oairu phy-asan-fixes prb_based_dl_channel_estimation rh_ci_test_rfsim_sa scs_60_iisc test-5GREC test-nsa-benetel 2021.w30 2021.w29 2021.w28 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19
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......@@ -425,6 +425,7 @@ int phy_init_lte_eNB(PHY_VARS_eNB *eNB,
generate_phich_reg_mapping (fp);
init_sss();
init_fde();
for (UE_id = 0; UE_id < NUMBER_OF_UE_MAX; UE_id++) {
eNB->first_run_timing_advance[UE_id] =
1; ///This flag used to be static. With multiple eNBs this does no longer work, hence we put it in the structure. However it has to be initialized with 1, which is performed here.
......
......@@ -22,8 +22,8 @@
#include "PHY/defs_eNB.h"
#include "PHY/sse_intrin.h"
// This is 512/(1:256) in __m128i format
int16_t inv_ch[256*8] = {512,512,512,512,512,512,512,512,
// This is 4096/(1:4096) in __m128i format
__m128i inv_ch[4096];/* = {512,512,512,512,512,512,512,512,
256,256,256,256,256,256,256,256,
170,170,170,170,170,170,170,170,
128,128,128,128,128,128,128,128,
......@@ -279,7 +279,11 @@ int16_t inv_ch[256*8] = {512,512,512,512,512,512,512,512,
2,2,2,2,2,2,2,2,
2,2,2,2,2,2,2,2,
2,2,2,2,2,2,2,2,
};
};*/
void init_fde() {
for (int i=1;i<4096;i++) inv_ch[i] = _mm_set1_epi16(4096/i);
}
void freq_equalization(LTE_DL_FRAME_PARMS *frame_parms,
int32_t **rxdataF_comp,
......@@ -312,12 +316,12 @@ void freq_equalization(LTE_DL_FRAME_PARMS *frame_parms,
amp=(*((int16_t*)&ul_ch_mag128[re]));
if (amp>255)
amp=255;
if (amp>4095)
amp=4095;
// printf("freq_eq: symbol %d re %d => %d,%d,%d, (%d) (%d,%d) => ",symbol,re,*((int16_t*)(&ul_ch_mag128[re])),amp,inv_ch[8*amp],*((int16_t*)(&ul_ch_mag128[re]))*inv_ch[8*amp],*(int16_t*)&(rxdataF_comp128[re]),*(1+(int16_t*)&(rxdataF_comp128[re])));
//printf("freq_eq: symbol %d re %d => mag %d,amp %d,inv %d, prod %d (%d,%d)\n",symbol,re,*((int16_t*)(&ul_ch_mag128[re])),amp,_mm_extract_epi16(inv_ch[amp],0),(*((int16_t*)(&ul_ch_mag128[re]))*_mm_extract_epi16(inv_ch[amp],0))>>3,*(int16_t*)&(rxdataF_comp128[re]),*(1+(int16_t*)&(rxdataF_comp128[re])));
#if defined(__x86_64__) || defined(__i386__)
rxdataF_comp128[re] = _mm_mullo_epi16(rxdataF_comp128[re],*((__m128i *)&inv_ch[8*amp]));
rxdataF_comp128[re] = _mm_srai_epi16(_mm_mullo_epi16(rxdataF_comp128[re],inv_ch[amp]),3);
if (Qm==4)
ul_ch_mag128[re] = _mm_set1_epi16(324); // this is 512*2/sqrt(10)
......@@ -326,7 +330,7 @@ void freq_equalization(LTE_DL_FRAME_PARMS *frame_parms,
ul_ch_magb128[re] = _mm_set1_epi16(158); // this is 512*2/sqrt(42)
}
#elif defined(__arm__)
rxdataF_comp128[re] = vmulq_s16(rxdataF_comp128[re],*((int16x8_t *)&inv_ch[8*amp]));
rxdataF_comp128[re] = vmulq_s16(rxdataF_comp128[re],inv_ch[amp]);
if (Qm==4)
ul_ch_mag128[re] = vdupq_n_s16(324); // this is 512*2/sqrt(10)
......
......@@ -288,6 +288,7 @@ void freq_equalization(LTE_DL_FRAME_PARMS *frame_parms,
unsigned short Msc_RS,
unsigned char Qm);
void init_fde(void);
void dump_I0_stats(FILE *fd,PHY_VARS_eNB *eNB);
/** @} */
......
......@@ -514,7 +514,6 @@ void ulsch_16qam_llr(LTE_DL_FRAME_PARMS *frame_parms,
for (i=0; i<(nb_rb*3); i++) {
#if defined(__x86_64__) || defined(__i386__)
mmtmpU0 = _mm_abs_epi16(rxF[i]);
// print_shorts("tmp0",&tmp0);
mmtmpU0 = _mm_subs_epi16(ch_mag[i],mmtmpU0);
(*llrp128)[0] = _mm_unpacklo_epi32(rxF[i],mmtmpU0);
(*llrp128)[1] = _mm_unpackhi_epi32(rxF[i],mmtmpU0);
......@@ -1160,8 +1159,7 @@ void rx_ulsch(PHY_VARS_eNB *eNB,
for (aarx=0; aarx<frame_parms->nb_antennas_rx; aarx++)
avgs = cmax(avgs,avgU[aarx]);
// log2_maxh = 4+(log2_approx(avgs)/2);
log2_maxh = (log2_approx(avgs)/2); //+ log2_approx(frame_parms->nb_antennas_rx-1)+4;
log2_maxh = 4+(log2_approx(avgs)/2);
LOG_D(PHY,"[ULSCH] log2_maxh = %d (%d,%d)\n",log2_maxh,avgU[0],avgs);
for (l=0; l<(frame_parms->symbols_per_tti-ulsch[UE_id]->harq_processes[harq_pid]->srs_active); l++) {
......
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