Commit fe6aa838 authored by Florian Kaltenberger's avatar Florian Kaltenberger

Merge branch 'nr_ue_fapi_improvements' into 'develop-nr'

Nr ue fapi improvements

See merge request oai/openairinterface5g!618
parents 633551db 40adad6f
dev 1 128-ues 256_QAM_demod 445-LDPC-implementation-on-GPU 459-pusch-based-ta-updates 464-ru_beamforming_in_gpu 464-ru_beamforming_in_gpu-CPUsubfunction 472-add-pusch-dmrs-modes 481-ldpc-decoder-on-gpu 512-dataplane-bug-in-l2nfapi_nos1 5g_fapi_scf FR2_NSA Fix_SA_SIB1 LTE_TRX_on_single_port NCTU_CS_ISIP NCTU_CS_ISIP_CPU NCTU_CS_ISIP_GPU NCTU_OpinConnect_Beamforming_ISIP NCTU_OpinConnect_LDPC NR-PHY-MAC-IF-multi-UE NRPRACH_highSpeed_saankhya NRUE_usedlschparallel NR_10MHz NR_2port_CSIRS NR_CSIRS_tomerge NR_CSI_reporting NR_DCI_01 NR_DLUL_PF NR_DLUL_PF_4UL NR_DLUL_PF_rebased NR_DL_MIMO NR_DL_sched_fixes NR_DL_scheduler NR_F1C_F1U_extensions NR_FAPI_beamindex_SSB_RO NR_FAPI_beamindex_SSB_RO_SEMPROJ NR_FDD_FIX NR_FR2_RA NR_FR2_RRC_SSB NR_FR2_initsync_fixes NR_MAC_CE_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge NR_MAC_Multi_Rach_GlobalEdge-old NR_MAC_SSB NR_MAC_SSB_RO_GlobalEdge NR_MAC_SSB_RO_UE_IDCC NR_MAC_SSB_RO_merge NR_MAC_TCI_UCI_GlobalEdge NR_MCS_BLER NR_NGAP NR_PDCP_noS1 NR_PUCCH_MultiUE NR_RA_cleanup NR_RA_updates NR_RRCConfiguragion_FR2 NR_RRCConfiguration NR_RRCConfiguration_FR2 NR_RRCConfiguration_S1U NR_RRCConfiguration_merge_develop NR_RRCConfiguration_sync_source NR_RRCConfiguration_trx_thread NR_RRCReconfiguration_BWP NR_RRC_CP_bugfix NR_RRC_PDCP NR_RRC_PRACH_procedures NR_RRC_PRACH_procedures_todevelop NR_RRC_PUSCH NR_RRC_TA NR_RRC_X2AP_AMBR_Change_Global_edge NR_RRC_X2AP_RemoveHardcodings_GlobalEdge NR_RRC_config_simplified NR_RRC_harq NR_RRC_harq_b NR_RRC_harq_hacks NR_RRC_harq_newdcipdu NR_SA_F1AP_5GRECORDS NR_SA_F1AP_5GRECORDS-USIM NR_SA_F1AP_5GRECORDS-wf-0623 NR_SA_F1AP_5GRECORDS_lts NR_SA_F1AP_RFSIMULATOR NR_SA_F1AP_RFSIMULATOR2 NR_SA_F1AP_RFSIMULATOR2_SRB NR_SA_F1AP_RFSIMULATOR3 NR_SA_F1AP_RFSIMULATOR3_tmp NR_SA_F1AP_RFSIMULATOR3_wf NR_SA_F1AP_RFSIMULATOR_w5GCN NR_SA_F1AP_dev NR_SA_NGAP_RRC NR_SA_NGAP_RRC_wk42 NR_SA_itti_sim_wk48 NR_SA_itti_sim_wk48_hs NR_SA_itti_sim_wk48_hs1 NR_SA_w5GCN_new_gtpu NR_SCHED NR_SCHED_HARQ NR_SCHED_PDCCH_PUCCH_HARQ NR_SCHED_PDCCH_PUCCH_HARQ_rebased NR_SCHED_fixes NR_SRB_Config NR_TRX_on_single_port NR_TRX_on_single_port2 NR_UE_CONFIG_REQ_FIXES NR_UE_MAC_scheduler NR_UE_PUCCH_bugfixes NR_UE_RA_fixes NR_UE_SA NR_UE_SSB_meas NR_UE_UL_DCI_improvements NR_UE_dlsch_bugfix NR_UE_enable_parallelization NR_UE_rework_test NR_UE_reworking_UCI_procedures NR_UE_stability_fixes NR_UL_FAPI_programming NR_UL_SCFDMA_100MHz NR_UL_scheduler NR_UL_scheduler_rebased NR_UL_scheduling NR_Wireshark NR_beam_simulation NR_beamforming_test NR_cleanup_PUCCH_resources NR_gNB_SCF_Indication NR_gNB_initial_MIB_fix NR_ipaccess_testing NR_mac_uci_functions_rework NR_msg2_phytest NR_multiplexing_HARQ_CSI_PUCCH NR_new_ul_antennaports NR_phytest_bugfixes NR_reworking_UL_antennaports NR_scheduling_CSIRS NR_scheduling_request NR_scheduling_request2 NR_scheduling_request3 NR_test_S1U_RRC_PRACH_procedures NR_ue_dlsch_dmrs_cdm OpInConnect_ISIP PBCHNRTCFIX PUSCH_TA_update RA_CI_test RFquality Saankhya_NRPRACH_HighSpeed Test_SA_5GREC UE_DL_DCI_hotfix add-dmrs-test add-ru-docker-image addoptions_nr_USRPdevice avxllr bandwidth-testing bch-fixes-bitmap benetel_5g_prach_fix benetel_config_file_fix benetel_dpdk20 benetel_driver_uldl_pf_merge benetel_driver_update benetel_fixes benetel_phase_rotation benetel_phase_rotation_old bsr-fix bugfix-free-ra-process bugfix-minor-remove-wrong-log bugfix-nr-bands bugfix-nr-ldpc-post-processing bugfix-nr-ldpc-size-typo bugfix-nr-pdcp-sn-size bugfix-nr-rate-matching-assertion bugfix-nr-t-reordering bugfix-x2-SgNBAdditionRequest bugfix_gnb_rt_stats_html bupt-sa-merge cce_indexing_fix cce_indexing_fix2 ci-add-sabox-support ci-deploy-asterix ci-deploy-docker-compose ci-fix-module-ul-iperf ci-new-docker-pipeline ci-rd-july-improvements ci-reduce-nb-vms ci-test ci-ul-iperf-from-trf-container ci_benetel_longrun_limits ci_benetel_test ci_fix_iperf_for_module ci_hotfix_module_ue_ip_address ci_improve_module_ctl ci_nsa_2x2_implem ci_nsa_benetel ci_nsa_fixes ci_nsa_pipes_improve ci_nsa_test_integration_2021_wk19 ci_nsa_traces ci_nsa_uplink ci_phytest ci_quectel_support ci_sa_rfsim_test ci_solve_ul_for_module ci_test_5GREC ci_test_nsa_2x2 ci_test_nsa_fix_quectel_nic ci_test_nsa_on_develop ci_test_ra_fr2 ci_testinfra_as_code ci_update_build_nasmesh ci_vm_resource_fix clean-5G-scope-round2 cleanup_softmodem_main code-cleanup-20210716 constant_power debug-UL-5GRECORDS debug_UL_signal debug_branch_init_sync detached-w16-test develop develop-CBRA-v3 develop-CCE develop-NR_SA_F1AP_5GRECORDS develop-NR_SA_F1AP_5GRECORDS-abs develop-NR_SA_F1AP_5GRECORDS-hs develop-NR_SA_F1AP_5GRECORDS-hs1 develop-NR_SA_F1AP_5GRECORDS-lts develop-NR_SA_F1AP_5GRECORDS-lts-wf develop-NR_SA_F1AP_5GRECORDS-v3 develop-NR_SA_F1AP_5GRECORDS_100M develop-NR_SA_F1AP_5GRECORDS_LDPC_FPGA develop-NR_SA_F1AP_5GRECORDS_lfq_0607 develop-NSA_SA_fixes develop-SA-CBRA develop-SA-CBRA-CUDU develop-SA-CBRA-Msg5 develop-SA-CBRA-lts develop-SA-CBRA-ulsch-lts develop-SA-RA develop-SnT develop-aw2sori develop-ci develop-nr develop-nr-fr2 develop-nr-fr2-rework develop-nr_cppcheck develop-oriecpriupdates develop-sib1 develop-sib1-local develop-sib1-lts develop-sib1-update develop-sib1-update-test1 develop-sib1-update-ue develop-wf-du develop_fpga_ldpc develop_inria_ci_deployment develop_inria_ci_deployment_gp develop_integration_2020_w15 develop_integration_2020_w19 develop_integration_w08 develop_stable dfts_alternatives disable_CSI_measrep dlsch-all-dlslots dlsch_encode_mthread dlsch_parallel docker-improvements-2021-april docker-no-cache-option docupdate_tools dongzhanyi-zte-develop dongzhanyi-zte-develop1 dongzhanyi-zte-develop2 dreibh/apt-auth-fix dreibh/device-load-fix dreibh/device-load-fix-develop-branch dual-connectivity edrx enhance-rfsim episys-merge episys/nsa_baseline episys/nsa_development extend_sharedlibusage extend_sharedlibusage2 fapi_for_dmrs_and_ptrs feature-4g-sched feature-nr-4g-nfapi-modifications feature-support-clang-format feature/make-s1-mme-port-configurable feature/make-s1-mme-port-configurable-with-astyle-fixes fedora-gen-kernel-fix fembms-enb-ue fft_bench_hotfix finalize-oaicn-integration firas fix-check fix-ci-tun fix-clock-source fix-compile fix-itti-segv fix-l2-sim fix-limeSDR-compile fix-lte-ue-modem-in-docker-container fix-nr-pdcp-timer fix-nr-rlc-range-nack fix-physim-deploy fix-physim-run-script-on-cluster fix-quectel fix-realtime fix-retransmission-rbg fix-softmodem-restart fix-warnings fix-x2-without-gnb fix_NR_DLUL_PF fix_NR_DLUL_PF_benchmark fix_coreset_dmrs_idx fix_do_ra_data fix_nr_ulsim fix_pdsch_low_prb fix_rb_corruption fix_reestablishment fix_rfsim_mimo fix_rrc_x2_ticking fixes-CE-RLC-PDU-size fixes-mac-sched-nfapi fixes-mac-sched-tun fixes-tun fixgtpu flexran-apps flexran-improvements flexran-repair-mme-mgmt flexran-rtc-repo-is-public fr2-hw-test fujitsu_lte_contribution fujitsu_lte_contribution-128 generate_push_ptrs git-dashboard gnb-freerun-txru gnb-n300-fixes gnb-only-test gnb-realtime-hotfix gnb-realtime-quickfix gnb-threadpool hack-bch-no-sched-sf-0 hack-exit-gnb-when-no-enb-nsa harq-hotfix hotfix-minor-remove-nr-rlc-cppcheck-error hotfix-nr-rlc-tick hotfix-ocp-executable hotfix-ue-musim-compilation hotfix_usrp_lib improve_build_nr_lte_merge improve_nr_modulation improve_ue_stability integ-w13-test-rt-issue integration-develop-nr-2019w45 integration_2020_wk15 integration_2020_wk40 integration_2020_wk41 integration_2020_wk42_2 integration_2020_wk45 integration_2020_wk45_2 integration_2020_wk46 integration_2020_wk46_2 integration_2020_wk47 integration_2020_wk48 integration_2020_wk48_2 integration_2020_wk49 integration_2020_wk50 integration_2020_wk50_1 integration_2020_wk51 integration_2020_wk51_2 integration_2021_wk02 integration_2021_wk02_wMR988 integration_2021_wk04 integration_2021_wk05 integration_2021_wk06 integration_2021_wk06_MR978 integration_2021_wk06_b integration_2021_wk06_c integration_2021_wk08 integration_2021_wk08_2 integration_2021_wk08_MR963 integration_2021_wk09 integration_2021_wk09_b integration_2021_wk10 integration_2021_wk10_b integration_2021_wk11 integration_2021_wk12 integration_2021_wk12_b integration_2021_wk13_a integration_2021_wk13_b integration_2021_wk13_b_fix_tdas integration_2021_wk13_b_fixed integration_2021_wk13_c integration_2021_wk14_a integration_2021_wk15_a integration_2021_wk16 integration_2021_wk17_a integration_2021_wk17_b integration_2021_wk18_a integration_2021_wk18_b integration_2021_wk19 integration_2021_wk20_a integration_2021_wk22 integration_2021_wk23 integration_2021_wk27 integration_2021_wk28 integration_2021_wk30 integration_2021_wk30_b integration_w5GC_CBRA_test inter-RRU-final inter-RRU-nr inter-RRU-oairu inter-rru-UE interoperability-test isip_nr itti-enhancement l2-fixes ldpc-dec-layering ldpc-decoder-codegen ldpc-decoder-codegen2 ldpc-decoder-improvements ldpc-offload ldpc_offload_t1 ldpc_short_codeword_fixes load_gnb lte-ulsch-bugfix lte_uplink_improvement mac-fixes-wk45_2 mbms-fix-develop-nr merging-2019-w51-to-develop-nr migrate-cpp-check-container migrate-vm-pipeline-to-bionic minor-fix-doc-basic-sim mosaic5g-oai-ran mosaic5g-oai-sim msg4_phy_0303_lfq multiple_ssb_sib1_bugfix nasmesh_kernel_5.8 new-gtpu new_rlc_2020 nfapi-bugfix nfapi_nr_arch_mod nfapi_nr_develop nfapi_nr_develop_new ngap-dlul ngap-support ngap-w48-merge2 ngap-wf ngap-wf-1120 ngap-wf-1120-srb ngap-wf-1120-srb-gtp ngap-wf-1120-srb-gtp-hs ngap-wf-1120-srb-gtp-hs1 ngap-wf-1120-srb-gtp-hs2 ngap-wf-1120-srb-gtp-yhz ngap-wf-1203-yunsdr ngap-wf-liuyu ngap_lfq_1120 ngap_merge noCore nr-bsr-fix nr-coreset-bug-fix nr-dl-mimo-2layer nr-dlsch-multi-thread nr-dlsch-thread nr-dmrs-fixes nr-dual-connectivity nr-interdigital-test nr-ip-uplink-noS1 nr-mac-pdu-wireshark nr-mac-remove-ue-list nr-pdcp nr-pdcp-benchmarking nr-pdcp-improvements nr-pdcp-nea2-security nr-pdcp-nia2-integrity nr-pdcp-small-bugfixes nr-pdcp-srb-integrity nr-pdsch-extraction-bugfix nr-physim-update nr-ra-fix nr-rlc-am-bugfix-w44 nr-rlc-bugfix-w44 nr-ssb-measurements nr-stats-print nr-timing-measurement nr-timing-measurement-merge nr-ue-buffer-status nr-uldci nrPBCHTCFix nrPbchTcFix nrUE nrUE-hs nrUE-upper-layer nr_beamforming nr_bsr nr_csi_newbranch nr_dl_dmrs_type2 nr_dl_pf nr_dl_pf2 nr_dl_ul_ptrs nr_dlsch_parallel_measurements nr_fapi_for_push_tmp nr_fdd_if_fix nr_fix_easycppcheck nr_improve_build_procedures nr_improve_chanest nr_increase_tp nr_pdcch_testing nr_polar_decoder_improvement nr_power_measurement_fixes nr_prach nr_prach_fr2 nr_pucch nr_pucch2 nr_segmentation_fixes nr_sim_fix nr_tdd_configuration nr_ue_msg3 nr_ue_pdcp_fix nr_ue_remove_high_speed_flag nr_ue_tti_cleanup nr_ul_pf nr_ul_scfdma nr_vcd nrue-multi-thread nrue_msg2_reception nsa-ue nsa_remove_band_hardcodings oai-sim oai-ubuntu-docker oai-ubuntu-docker-for-lmssdr oairu oairu-dockerfile-support oc-docker-october-improvements openxg/develop pdcp-benchmark pdsch-ch-est phy-asan-fixes physim-build-deploy physim-deploy-handle-error-cases polar8 prb_based_dl_channel_estimation ptrs_rrc_config pusch-mthread-scaling-fix pusch-retrans-fix-ue ra-dl-ul recursive-cmake reduce_memory_footprint remove_nos1_hack_pdcp remove_x2_gnb_hardcoding repair-TA revert-f5c94279 revert_memcpy rh-ci-add-ue-parallelization rh_ci_add_runtime_stats rh_ci_add_uldlharq_stats rh_ci_fix_autoterminate rh_ci_fr1_update rh_ci_gsheet_rt_monitoring rh_ci_nsa2jenkins rh_ci_nsa_test_n310 rh_ci_oc rh_ci_phy_test_improve rh_ci_py rh_ci_ra_fr2 rh_ci_rfsim_ra rh_ci_test_benetel rh_ci_test_nsa rh_ci_test_nsa_wk16 rh_ci_test_nsa_wk17_b rh_ci_test_nsa_wk17b rh_ci_test_rfsim_sa rh_ci_ue_parallel rh_doc_update_3 rh_fr1_newjenkins rh_fr1_update rh_gnb_compile_fix rh_wk50_debug rlc-v2-bugfix-status-reporting rlc-v2-tick rlc_v2_coverity_fixes rohan_ulsim2RxFix rrc-enb-phy-testmode ru-parallel-beamforming runel runel-reverse-test s1-subnormal_rewrite s1_subnormal s1_subnormal-robert s1ap-bugfix-rab_setup sa-demo sa-demo-hs sa-merge-rrc-srb sa-msg4 sa-msg4-rrc sa-msg4-rrc-yihz sa-msg4-rrc-yihz-hs sa_rrc_yihz sanitize-address sanitize-v1 sanitize-v1-tmp sarma_pvnp_oai scs_60_iisc sim-channels small-bugfixes-w40 small-config-change small_nr_bugfixes smallcleanup softmodem_cleanup split73 t-gnb-tracer test-5GREC test-nsa-benetel test-panos test_nsa_gtpu_fix test_rt-fix_phy-test testing_2symb_pdcch testing_with_external_txdata tools_5Gadapt tp-ota-test trx_thread_param trx_write_thread ue-csi ue-dci-false-detection ue-fixes ue-fixes-ota ue-pdsch-pusch-parallel ue-race-fix ue-updates-runel-test ue_adjust_gain ue_beam_selection ue_dlsch_decoding_ldpc_offload ue_nfapi_mch uhd_priority_set_cleanup ul-freq-iq-samps-to-file ul_dl_dci_same_slot ul_harq ulsch_decode_mthread ulsim_changes update-to-2019-march-june-release usrp_fix_adc_shift_and_pps_sync usrp_gpio_test usrp_stop_cleanly usrp_x400 wf-sa-rrc wf_testc wireshark-T-hack-ueid wireshark-log-scheduling-requests wk11-with-phytest x2-endc-processing x2_handle_sctp_shutdown xiangwab xiangwan xw2 yihongzheng_srb zzs 2021.wk14_a 2021.wk13_d 2021.wk13_c 2021.w30 2021.w29 2021.w28 2021.w27 2021.w26 2021.w25 2021.w24 2021.w23 2021.w22 2021.w20 2021.w19 2021.w18_b 2021.w18_a 2021.w17_b 2021.w16 2021.w15 2021.w14 2021.w13_a 2021.w12 2021.w11 2021.w10 2021.w09 2021.w08 2021.w06 2021.w05 2021.w04 2021.w02 2020.w51_2 2020.w51 2020.w50 2020.w49 2020.w48_2 2020.w48 2020.w47 2020.w46_2 2020.w46 2020.w45_2 2020.w45 2020.w44 2020.w42_2 2020.w42 2020.w41 2020.w39 2020.w38 2020.w37 2020.w36 2020.w34 2020.w33 2020.w31 2020.w30 2020.w29 2020.w28 2020.w26 2020.w25 2020.w24 2020.w23 2020.w22 2020.w19 2020.w17 2020.w16 2020.w15 2020.w11 2020.w09 2020.w06 2020.w05 2020.w04 2020.w03 nr-ip-over-lte-v.1.5 nr-ip-over-lte-v.1.4 nr-ip-over-lte-v.1.3 nr-ip-over-lte-v.1.2 nr-ip-over-lte-v.1.1 nr-ip-over-lte-v.1.0 develop-nr-2020w03 develop-nr-2020w02 develop-nr-2019w51 develop-nr-2019w50 develop-nr-2019w48 develop-nr-2019w47 develop-nr-2019w45 develop-nr-2019w43 develop-nr-2019w42 develop-nr-2019w40 develop-nr-2019w28 benetel_phase_rotation benetel_gnb_rel_2.0 benetel_gnb_rel_1.0 benetel_enb_rel_2.0 benetel_enb_rel_1.0
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......@@ -350,39 +350,42 @@ static void UE_synch(void *arg) {
}
void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
nr_dcireq_t dcireq;
nr_scheduled_response_t scheduled_response;
// Process Rx data for one sub-frame
if (slot_select_nr(&UE->frame_parms, proc->frame_tx, proc->nr_tti_tx) & NR_DOWNLINK_SLOT) {
//clean previous FAPI MESSAGE
UE->rx_ind.number_pdus = 0;
UE->dci_ind.number_of_dcis = 0;
//clean previous FAPI MESSAGE
// call L2 for DL_CONFIG (DCI)
UE->dcireq.module_id = UE->Mod_id;
UE->dcireq.gNB_index = 0;
UE->dcireq.cc_id = 0;
UE->dcireq.frame = proc->frame_rx;
UE->dcireq.slot = proc->nr_tti_rx;
nr_ue_dcireq(&UE->dcireq); //to be replaced with function pointer later
NR_UE_MAC_INST_t *UE_mac = get_mac_inst(0);
UE_mac->scheduled_response.dl_config = &UE->dcireq.dl_config_req;
UE_mac->scheduled_response.ul_config = NULL;
UE_mac->scheduled_response.tx_request = NULL;
UE_mac->scheduled_response.module_id = UE->Mod_id;
UE_mac->scheduled_response.CC_id = 0;
UE_mac->scheduled_response.frame = proc->frame_rx;
UE_mac->scheduled_response.slot = proc->nr_tti_rx;
nr_ue_scheduled_response(&UE_mac->scheduled_response);
//write_output("uerxdata_frame.m", "uerxdata_frame", UE->common_vars.rxdata[0], UE->frame_parms.samples_per_frame, 1, 1);
//TODO: all of this has to be moved to the MAC!!!
dcireq.module_id = UE->Mod_id;
dcireq.gNB_index = 0;
dcireq.cc_id = 0;
dcireq.frame = proc->frame_rx;
dcireq.slot = proc->nr_tti_rx;
nr_ue_dcireq(&dcireq); //to be replaced with function pointer later
scheduled_response.dl_config = &dcireq.dl_config_req;
scheduled_response.ul_config = NULL;
scheduled_response.tx_request = NULL;
scheduled_response.module_id = UE->Mod_id;
scheduled_response.CC_id = 0;
scheduled_response.frame = proc->frame_rx;
scheduled_response.slot = proc->nr_tti_rx;
nr_ue_scheduled_response(&scheduled_response);
#ifdef UE_SLOT_PARALLELISATION
phy_procedures_slot_parallelization_nrUE_RX( UE, proc, 0, 0, 1, UE->mode, no_relay, NULL );
#else
uint64_t a=rdtsc();
phy_procedures_nrUE_RX( UE, proc, 0, 1, UE->mode, UE_mac->phy_config.config_req.pbch_config);
phy_procedures_nrUE_RX( UE, proc, 0, 1, UE->mode);
LOG_D(PHY,"phy_procedures_nrUE_RX: slot:%d, time %lu\n", proc->nr_tti_rx, (rdtsc()-a)/3500);
//printf(">>> nr_ue_pdcch_procedures ended\n");
#endif
}
// no UL for now
/*
if (UE->mac_enabled==1) {
// trigger L2 to run ue_scheduler thru IF module
// [TODO] mapping right after NR initial sync
......@@ -395,6 +398,7 @@ void processSlotRX( PHY_VARS_NR_UE *UE, UE_nr_rxtx_proc_t *proc) {
UE->if_inst->ul_indication(&UE->ul_indication);
}
}
*/
}
/*!
......
#!/bin/sh
echo "building ctags for openair1 and openair2 ..."
ctags -e -R --exclude=openair1/DOCS/ --exclude=openair2/DOCS/ --exclude=openair1/SIMULATION/ --exclude=targets/DOCS/ --exclude=targets/PROJECTS/ openair1 openair2 openair3 targets cmake_targets common nfapi
ctags -e -R --exclude=openair1/DOCS/ --exclude=openair2/DOCS/ --exclude=openair1/SIMULATION/ --exclude=targets/DOCS/ --exclude=targets/PROJECTS/ openair1 openair2 openair3 targets cmake_targets common nfapi executables
......@@ -237,9 +237,9 @@ uint32_t nr_dlsch_decoding(PHY_VARS_NR_UE *phy_vars_ue,
uint32_t Tbslbrm = 950984;
uint16_t nb_rb = 30;
double Coderate = 0.0;
nfapi_nr_config_request_t *cfg = &phy_vars_ue->nrUE_config;
uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value;
uint8_t nb_re_dmrs = (dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4;
//nfapi_nr_config_request_t *cfg = &phy_vars_ue->nrUE_config;
//uint8_t dmrs_type = cfg->pdsch_config.dmrs_type.value;
uint8_t nb_re_dmrs = 6; //(dmrs_type==NFAPI_NR_DMRS_TYPE1)?6:4;
uint16_t length_dmrs = 1; //cfg->pdsch_config.dmrs_max_length.value;
uint32_t i,j;
......
......@@ -566,8 +566,8 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
}
uint32_t payload = 0;
uint8_t xtra_byte = 0;
xtra_byte = (out>>24)&0xff;
//uint8_t xtra_byte = 0;
nr_ue_pbch_vars->xtra_byte = (out>>24)&0xff;
for (int i=0; i<NR_POLAR_PBCH_PAYLOAD_BITS; i++)
payload |= ((out>>i)&1)<<(NR_POLAR_PBCH_PAYLOAD_BITS-i-1);
......@@ -575,18 +575,18 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
for (int i=0; i<3; i++)
decoded_output[i] = (uint8_t)((payload>>((3-i)<<3))&0xff);
n_hf = ((xtra_byte>>4)&0x01); // computing the half frame index from the extra byte
n_hf = ((nr_ue_pbch_vars->xtra_byte>>4)&0x01); // computing the half frame index from the extra byte
ssb_index = i_ssb; // ssb index corresponds to i_ssb for Lmax = 4,8
if (Lmax == 64) { // for Lmax = 64 ssb index 4th,5th and 6th bits are in extra byte
for (int i=0; i<3; i++)
ssb_index += (((xtra_byte>>(7-i))&0x01)<<(3+i));
ssb_index += (((nr_ue_pbch_vars->xtra_byte>>(7-i))&0x01)<<(3+i));
}
ue->symbol_offset = nr_get_ssb_start_symbol(frame_parms, ssb_index, n_hf);
#ifdef DEBUG_PBCH
printf("xtra_byte %x payload %x\n", xtra_byte, payload);
printf("xtra_byte %x payload %x\n", nr_ue_pbch_vars->xtra_byte, payload);
for (int i=0; i<(NR_POLAR_PBCH_PAYLOAD_BITS>>3); i++) {
// printf("unscrambling pbch_a[%d] = %x \n", i,pbch_a[i]);
......@@ -594,19 +594,25 @@ int nr_rx_pbch( PHY_VARS_NR_UE *ue,
}
#endif
ue->dl_indication.rx_ind = &ue->rx_ind; // hang on rx_ind instance
ue->dl_indication.proc=proc;
//ue->rx_ind.sfn_slot = 0; //should be set by higher-1-layer, i.e. clean_and_set_if_instance()
ue->rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_MIB;
ue->rx_ind.rx_indication_body[0].mib_pdu.pdu = &decoded_output[0];
ue->rx_ind.rx_indication_body[0].mib_pdu.additional_bits = xtra_byte;
ue->rx_ind.rx_indication_body[0].mib_pdu.ssb_index = i_ssb; // confirm with TCL
ue->rx_ind.rx_indication_body[0].mib_pdu.ssb_length = Lmax; // confirm with TCL
ue->rx_ind.rx_indication_body[0].mib_pdu.cell_id = frame_parms->Nid_cell; // confirm with TCL
ue->rx_ind.number_pdus = 1;
nr_downlink_indication_t dl_indication;
fapi_nr_rx_indication_t rx_ind;
dl_indication.rx_ind = &rx_ind; // hang on rx_ind instance
dl_indication.dci_ind = NULL;
dl_indication.proc=proc; // needed to signal back the frame number -> FIXME
dl_indication.module_id=0;
dl_indication.cc_id=proc->CC_id;
rx_ind.rx_indication_body[0].pdu_type = FAPI_NR_RX_PDU_TYPE_MIB;
rx_ind.rx_indication_body[0].mib_pdu.pdu = &decoded_output[0]; //not good as it is pointing to a memory that can change
rx_ind.rx_indication_body[0].mib_pdu.additional_bits = nr_ue_pbch_vars->xtra_byte;
rx_ind.rx_indication_body[0].mib_pdu.ssb_index = i_ssb; // confirm with TCL
rx_ind.rx_indication_body[0].mib_pdu.ssb_length = Lmax; // confirm with TCL
rx_ind.rx_indication_body[0].mib_pdu.cell_id = frame_parms->Nid_cell; // confirm with TCL
rx_ind.number_pdus = 1;
if (ue->if_inst && ue->if_inst->dl_indication)
ue->if_inst->dl_indication(&ue->dl_indication);
ue->if_inst->dl_indication(&dl_indication);
return 0;
}
......@@ -50,15 +50,12 @@ int generate_ue_ulsch_params(PHY_VARS_NR_UE *UE,
unsigned char harq_pid){
int N_PRB_oh, N_RE_prime, cwd_idx, length_dmrs, Nid_cell;
int nb_rb, Nsymb_pusch, first_rb, nb_codewords;
int nb_rb, Nsymb_pusch, first_rb, nb_codewords,mcs,rvidx;
uint16_t n_rnti;
fapi_nr_dci_pdu_rel15_t *ul_dci_pdu;
NR_UE_ULSCH_t *ulsch_ue;
NR_UL_UE_HARQ_t *harq_process_ul_ue;
ul_dci_pdu = &UE->dci_ind.dci_list[0].dci;
//--------------------------Temporary configuration-----------------------------//
length_dmrs = 1;
n_rnti = 0x1234;
......@@ -66,7 +63,9 @@ int generate_ue_ulsch_params(PHY_VARS_NR_UE *UE,
nb_rb = 50;
first_rb = 30;
Nsymb_pusch = 12;
nb_codewords = (ul_dci_pdu->precod_nbr_layers>4)?2:1;
nb_codewords = 1;
mcs = 9;
rvidx = 0;
//------------------------------------------------------------------------------//
for (cwd_idx = 0; cwd_idx < nb_codewords; cwd_idx++) {
......@@ -87,19 +86,19 @@ int generate_ue_ulsch_params(PHY_VARS_NR_UE *UE,
if (harq_process_ul_ue) {
harq_process_ul_ue->mcs = ul_dci_pdu->mcs;
harq_process_ul_ue->Nl = ul_dci_pdu->precod_nbr_layers;
harq_process_ul_ue->mcs = mcs;
harq_process_ul_ue->Nl = nb_codewords;
harq_process_ul_ue->nb_rb = nb_rb;
harq_process_ul_ue->first_rb = first_rb;
harq_process_ul_ue->number_of_symbols = Nsymb_pusch;
harq_process_ul_ue->num_of_mod_symbols = N_RE_prime*nb_rb*nb_codewords;
harq_process_ul_ue->rvidx = ul_dci_pdu->rv;
harq_process_ul_ue->TBS = nr_compute_tbs(ul_dci_pdu->mcs,
harq_process_ul_ue->rvidx = rvidx;
harq_process_ul_ue->TBS = nr_compute_tbs(harq_process_ul_ue->mcs,
nb_rb,
Nsymb_pusch,
ulsch_ue->nb_re_dmrs,
length_dmrs,
ul_dci_pdu->precod_nbr_layers);
harq_process_ul_ue->Nl);
}
......
......@@ -822,6 +822,8 @@ typedef struct {
/// \brief Pointer to PBCH decoded output.
/// - first index: ? [0..63] (hard coded)
uint8_t *decoded_output;
/// \brief PBCH additional bits
uint8_t xtra_byte;
/// \brief Total number of PDU errors.
uint32_t pdu_errors;
/// \brief Total number of PDU errors 128 frames ago.
......@@ -923,18 +925,22 @@ typedef struct {
NR_UE_COMMON common_vars;
nr_ue_if_module_t *if_inst;
nfapi_nr_config_request_t nrUE_config;
nr_downlink_indication_t dl_indication;
nr_uplink_indication_t ul_indication;
//nfapi_nr_config_request_t nrUE_config; <-- don't use config type for gNB!!!
fapi_nr_config_request_t nrUE_config;
// the following structures are not part of PHY_vars_UE anymore as it is not thread safe. They are now on the stack of the functions that actually need them
//nr_downlink_indication_t dl_indication;
//nr_uplink_indication_t ul_indication;
/// UE FAPI DCI request
nr_dcireq_t dcireq;
//nr_dcireq_t dcireq;
// pointers to the next 2 strcutres are also included in dl_indictation
/// UE FAPI indication for DLSCH reception
fapi_nr_rx_indication_t rx_ind;
//fapi_nr_rx_indication_t rx_ind;
/// UE FAPI indication for DCI reception
fapi_nr_dci_indication_t dci_ind;
//fapi_nr_dci_indication_t dci_ind;
// point to the current rxTx thread index
uint8_t current_thread_id[40];
......
......@@ -123,7 +123,7 @@ void phy_procedures_nrUE_TX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t e
@param r_type indicates the relaying operation: 0: no_relaying, 1: unicast relaying type 1, 2: unicast relaying type 2, 3: multicast relaying
@param phy_vars_rn pointer to RN variables
*/
int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t do_pdcch_flag,runmode_t mode,fapi_nr_pbch_config_t pbch_config);
int phy_procedures_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t do_pdcch_flag,runmode_t mode);
int phy_procedures_slot_parallelization_nrUE_RX(PHY_VARS_NR_UE *ue,UE_nr_rxtx_proc_t *proc,uint8_t eNB_id,uint8_t abstraction_flag,uint8_t do_pdcch_flag,runmode_t mode,relaying_type_t r_type);
......
......@@ -49,10 +49,10 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
uint8_t cc_id = scheduled_response->CC_id;
uint32_t i;
int slot = scheduled_response->slot;
uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot];
if(scheduled_response != NULL){
// Note: we have to handle the thread IDs for this. To be revisited completely.
uint8_t thread_id = PHY_vars_UE_g[module_id][cc_id]->current_thread_id[slot];
NR_UE_PDCCH *pdcch_vars2 = PHY_vars_UE_g[module_id][cc_id]->pdcch_vars[thread_id][0];
NR_UE_DLSCH_t *dlsch0 = PHY_vars_UE_g[module_id][cc_id]->dlsch[thread_id][0][0];
NR_UE_ULSCH_t *ulsch0 = PHY_vars_UE_g[module_id][cc_id]->ulsch[thread_id][0][0];
......@@ -147,6 +147,7 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
ulsch0->harq_processes[current_harq_pid]->mcs = pusch_config_pdu->mcs;
ulsch0->harq_processes[current_harq_pid]->DCINdi = pusch_config_pdu->ndi;
ulsch0->harq_processes[current_harq_pid]->rvidx = pusch_config_pdu->rv;
ulsch0->harq_processes[current_harq_pid]->Nl = pusch_config_pdu->n_layers;
ulsch0->f_pusch = pusch_config_pdu->absolute_delta_PUSCH;
}
if(ul_config->ul_config_list[i].pdu_type == FAPI_NR_UL_CONFIG_TYPE_PUCCH){
......@@ -213,6 +214,8 @@ int8_t nr_ue_scheduled_response(nr_scheduled_response_t *scheduled_response){
int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){
fapi_nr_config_request_t nrUE_config = PHY_vars_UE_g[phy_config->Mod_id][phy_config->CC_id]->nrUE_config;
if(phy_config != NULL){
if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_PBCH){
LOG_I(MAC,"[L1][IF module][PHY CONFIG]\n");
......@@ -227,6 +230,8 @@ int8_t nr_ue_phy_config_request(nr_phy_config_t *phy_config){
LOG_I(MAC,"half frame bit: %d\n", phy_config->config_req.pbch_config.half_frame_bit);
LOG_I(MAC,"-------------------------------\n");
memcpy(&nrUE_config.pbch_config,&phy_config->config_req.pbch_config,sizeof(fapi_nr_pbch_config_t));
}
if(phy_config->config_req.config_mask & FAPI_NR_CONFIG_REQUEST_MASK_DL_BWP_COMMON){
......
This diff is collapsed.
......@@ -685,6 +685,8 @@ int main(int argc, char **argv)
UE_mac->phy_config.config_req.pbch_config.ssb_index = 0;
UE_mac->phy_config.config_req.pbch_config.half_frame_bit = 0;
nr_ue_phy_config_request(&UE_mac->phy_config);
for (SNR=snr0; SNR<snr1; SNR+=.2) {
n_errors = 0;
......@@ -735,8 +737,7 @@ int main(int argc, char **argv)
&UE_proc,
0,
do_pdcch_flag,
normal_txrx,
UE_mac->phy_config.config_req.pbch_config);
normal_txrx);
if (n_trials==1) {
LOG_M("rxsigF0.m","rxsF0", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[0],slot_length_complex_samples_no_prefix,1,1);
......@@ -744,7 +745,7 @@ int main(int argc, char **argv)
LOG_M("rxsigF1.m","rxsF1", UE->common_vars.common_vars_rx_data_per_thread[0].rxdataF[1],slot_length_complex_samples_no_prefix,1,1);
}
if (UE->dci_ind.number_of_dcis==0) n_errors++;
if (UE_mac->dl_config_request.number_pdus==0) n_errors++;
}
} //noise trials
......
......@@ -637,10 +637,10 @@ int main(int argc, char **argv)
uint8_t gNB_xtra_byte=0;
for (int i=0; i<8; i++)
gNB_xtra_byte |= ((gNB->pbch.pbch_a>>(31-i))&1)<<(7-i);
payload_ret = (UE->rx_ind.rx_indication_body->mib_pdu.additional_bits == gNB_xtra_byte);
payload_ret = (UE->pbch_vars[0]->xtra_byte == gNB_xtra_byte);
for (i=0;i<3;i++){
payload_ret += (UE->rx_ind.rx_indication_body->mib_pdu.pdu[i] == gNB->pbch_pdu[2-i]);
payload_ret += (UE->pbch_vars[0]->decoded_output[i] == gNB->pbch_pdu[2-i]);
//printf("pdu byte %d gNB: 0x%02x UE: 0x%02x\n",i,gNB->pbch_pdu[i], UE->rx_ind.rx_indication_body->mib_pdu.pdu[i]);
}
//printf("xtra byte gNB: 0x%02x UE: 0x%02x\n",gNB_xtra_byte, UE->rx_ind.rx_indication_body->mib_pdu.additional_bits);
......@@ -656,7 +656,6 @@ int main(int argc, char **argv)
if (((float)n_errors/(float)n_trials <= target_error_rate) && (n_errors_payload==0)) {
printf("PBCH test OK\n");
printf("Synchronization obtained for i_ssb = %d\n",UE->rx_ind.rx_indication_body[0].mib_pdu.ssb_index);
break;
}
......
......@@ -55,6 +55,7 @@
#include "PHY/TOOLS/tools_defs.h"
#include "PHY/NR_TRANSPORT/nr_sch_dmrs.h"
#include "PHY/phy_vars.h"
#include "SCHED_NR_UE/fapi_nr_ue_l1.h"
//#include "PHY/MODULATION/modulation_common.h"
//#include "common/config/config_load_configmodule.h"
......@@ -170,6 +171,7 @@ int main(int argc, char **argv) {
int start_symbol = NR_SYMBOLS_PER_SLOT - nb_symb_sch;
uint16_t nb_rb = 50;
uint8_t Imcs = 9;
uint8_t precod_nbr_layers = 1;
int gNB_id = 0;
int ap;
int tx_offset;
......@@ -182,7 +184,6 @@ int main(int argc, char **argv) {
cpuf = get_cpu_freq_GHz();
fapi_nr_dci_pdu_rel15_t *ul_dci_pdu;
UE_nr_rxtx_proc_t UE_proc;
......@@ -444,11 +445,6 @@ int main(int argc, char **argv) {
}
}
ul_dci_pdu = &UE->dci_ind.dci_list[0].dci;
ul_dci_pdu->mcs = Imcs;
ul_dci_pdu->rv = 0;
ul_dci_pdu->precod_nbr_layers = 1;
unsigned char harq_pid = 0;
unsigned int TBS = 8424;
......@@ -459,14 +455,14 @@ int main(int argc, char **argv) {
mod_order = nr_get_Qm(Imcs, 1);
available_bits = nr_get_G(nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, mod_order, 1);
TBS = nr_compute_tbs(Imcs, nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, ul_dci_pdu->precod_nbr_layers);
TBS = nr_compute_tbs(Imcs, nb_rb, nb_symb_sch, nb_re_dmrs, length_dmrs, precod_nbr_layers);
NR_gNB_ULSCH_t *ulsch_gNB = gNB->ulsch[UE_id+1][0];
nfapi_nr_ul_config_ulsch_pdu *rel15_ul = &ulsch_gNB->harq_processes[harq_pid]->ulsch_pdu;
NR_UE_ULSCH_t **ulsch_ue = UE->ulsch[0][0];
// --------- setting rel15_ul parameters ----------
// --------- setting rel15_ul parameters for gNB --------
rel15_ul->rnti = n_rnti;
rel15_ul->ulsch_pdu_rel15.start_rb = start_rb;
rel15_ul->ulsch_pdu_rel15.number_rbs = nb_rb;
......@@ -477,9 +473,41 @@ int main(int argc, char **argv) {
rel15_ul->ulsch_pdu_rel15.Qm = mod_order;
rel15_ul->ulsch_pdu_rel15.mcs = Imcs;
rel15_ul->ulsch_pdu_rel15.rv = 0;
rel15_ul->ulsch_pdu_rel15.n_layers = ul_dci_pdu->precod_nbr_layers;
rel15_ul->ulsch_pdu_rel15.ndi = 0;
rel15_ul->ulsch_pdu_rel15.n_layers = precod_nbr_layers;
///////////////////////////////////////////////////
nr_scheduled_response_t scheduled_response;
fapi_nr_ul_config_request_t ul_config;
//fapi_nr_tx_request_t tx_request;
scheduled_response.module_id = 0;
scheduled_response.CC_id = 0;
scheduled_response.frame = frame;
scheduled_response.slot = slot;
scheduled_response.dl_config = NULL;
scheduled_response.ul_config = &ul_config;
scheduled_response.dl_config = NULL;
ul_config.sfn_slot = slot;
ul_config.number_pdus = 1;
ul_config.ul_config_list[0].pdu_type = FAPI_NR_UL_CONFIG_TYPE_PUSCH;
ul_config.ul_config_list[0].ulsch_config_pdu.rnti = n_rnti;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_rbs = nb_rb;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_rb = start_rb;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.number_symbols = nb_symb_sch;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.start_symbol = start_symbol;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.mcs = Imcs;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.ndi = 0;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.rv = 0;
ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.n_layers = precod_nbr_layers;
//there are plenty of other parameters that we don't seem to be using for now. e.g.
//ul_config.ul_config_list[0].ulsch_config_pdu.ulsch_pdu_rel15.absolute_delta_PUSCH = 0;
// set FAPI parameters for UE, put them in the scheduled response and call
//nr_ue_scheduled_response(&scheduled_response);
unsigned char *estimated_output_bit;
unsigned char *test_input_bit;
unsigned int errors_bit = 0;
......
......@@ -72,14 +72,15 @@ int handle_dci(module_id_t module_id, int cc_id, unsigned int gNB_index, fapi_nr
// L2 Abstraction Layer
int8_t handle_dlsch (module_id_t module_id, int cc_id, uint8_t gNB_index, fapi_nr_dci_indication_t *dci_ind, uint8_t *pduP, uint32_t pdu_len){
// return 0;
return 0;
/*
return nr_ue_process_dlsch( module_id,
cc_id,
gNB_index,
dci_ind,
pduP,
pdu_len);
*/
}
int nr_ue_ul_indication(nr_uplink_indication_t *ul_info){
......@@ -156,6 +157,9 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
(dl_info->dci_ind->dci_list+i)->rnti,
(dl_info->dci_ind->dci_list+i)->dci_format)) << FAPI_NR_DCI_IND;
AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" );
nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response);
/*switch((dl_info->dci_ind->dci_list+i)->dci_type){
case FAPI_NR_DCI_TYPE_0_0:
......@@ -242,9 +246,6 @@ int nr_ue_dl_indication(nr_downlink_indication_t *dl_info){
dl_info->rx_ind = NULL;
dl_info->dci_ind = NULL;
AssertFatal( nr_ue_if_module_inst[module_id] != NULL, "IF module is void!\n" );
nr_ue_if_module_inst[module_id]->scheduled_response(&mac->scheduled_response);
return 0;
}
......
......@@ -65,6 +65,7 @@ typedef struct {
frame_t frame;
/// slot
int slot;
/// proc is needed to signal back decoded frame number to PHY. However, this is not really FAPI procedure and should be done differently
UE_nr_rxtx_proc_t * proc;
/// NR UE FAPI-like P7 message, direction: L1 to L2
......
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