Commit 71bdd3cc authored by Pankaj Darak's avatar Pankaj Darak

QDMA Linux reference driver 2019.1 Patch release

Co-Authored-By: default avatarsujathabanoth-xlnx <sujathabanoth-xlnx@users.noreply.github.com>
parent 8d603ef2
...@@ -181,10 +181,10 @@ vf: user mod_vf ...@@ -181,10 +181,10 @@ vf: user mod_vf
mod: mod_pf mod_vf mod: mod_pf mod_vf
.PHONY: install .PHONY: install
install: install-mods install-user install-etc install-dev install: install-user install-etc install-dev
.PHONY: uninstall .PHONY: uninstall
uninstall: uninstall-mod uninstall-user uninstall-dev uninstall: uninstall-user uninstall-dev
.PHONY: user .PHONY: user
user: user:
...@@ -276,8 +276,8 @@ install-etc: ...@@ -276,8 +276,8 @@ install-etc:
install -v -m 644 etc/30-qdma.rules $(udev_install_path); \ install -v -m 644 etc/30-qdma.rules $(udev_install_path); \
fi; fi;
.PHONY: uninstall-mod .PHONY: uninstall-mods
uninstall-mod: uninstall-mods:
@echo "Un-installing $(kernel_install_path) ..." @echo "Un-installing $(kernel_install_path) ..."
@/bin/rm -rf $(kernel_install_path)/* @/bin/rm -rf $(kernel_install_path)/*
@depmod -a @depmod -a
...@@ -298,9 +298,10 @@ uninstall-dev: ...@@ -298,9 +298,10 @@ uninstall-dev:
.PHONY: help .PHONY: help
help: help:
@echo "Build Targets:";\ @echo "Build Targets:";\
echo " install - Installs all compiled drivers.";\ echo " install - Installs user tools and development headers.";\
echo " uninstall - Uninstalls drivers.";\ echo " uninstall - Uninstalls user tools and development headers.";\
echo " clean - Removes all generated files.";\ echo " install-mods - Installs drivers.";\
echo " uninstall-mods - Uninstalls drivers.";\
echo;\ echo;\
echo "Build Options:";\ echo "Build Options:";\
echo " KOBJ=<path> - Kernel build (object) path.";\ echo " KOBJ=<path> - Kernel build (object) path.";\
...@@ -312,5 +313,4 @@ help: ...@@ -312,5 +313,4 @@ help:
echo " kernel_install_path=<path>";\ echo " kernel_install_path=<path>";\
echo " - kernel module install path.";\ echo " - kernel module install path.";\
echo " user_install_path=<path>";\ echo " user_install_path=<path>";\
echo " - user cli tool install path.";\ echo " - user cli tool install path.";
ech_;
Release: 2019.1 Release: 2019.1 Patch
=============== =====================
NOTE: NOTE:
This release is based on the 2019.1 QDMA design This release is based on the 2019.1 QDMA IP
Performance benchmark numbers are captured in performance report
for this version of driver and released along with the driver package
QDMA Linux driver is supported in auto mode by default
SUPPORTED FEATURES: SUPPORTED FEATURES:
=================== ===================
...@@ -64,9 +58,17 @@ SUPPORTED FEATURES: ...@@ -64,9 +58,17 @@ SUPPORTED FEATURES:
- Interoperability between Linux driver (as PF/VF) and DPDK driver (as PF/VF) - Interoperability between Linux driver (as PF/VF) and DPDK driver (as PF/VF)
- Driver restructuring to partition QDMA access code such that it can be used across different drivers - Driver restructuring to partition QDMA access code such that it can be used across different drivers
2019.1 Patch Updates
--------------------
- Addressed the issues observed in static analysis of the code base
- Added the User Logic pluggability
- Supported HW Error detection in poll mode
KNOWN ISSUES: KNOWN ISSUES:
============= =============
- Sometimes completions are not received when C2H PIDX updates are held for 64 descriptors - Sometimes completions are not received when C2H PIDX updates are held for 64 descriptors
- FLR Reset on a PF while any VFs are attached to PF is not working
DRIVER LIMITATIONS: DRIVER LIMITATIONS:
=================== ===================
......
...@@ -27,9 +27,9 @@ author = 'Xilinx, Inc' ...@@ -27,9 +27,9 @@ author = 'Xilinx, Inc'
# The short X.Y version # The short X.Y version
#version = u'' #version = u''
version = '2019.1' version = '2019.1 Patch'
# The full version, including alpha/beta/rc tags # The full version, including alpha/beta/rc tags
release = u'2019.1' release = u'2019.1 Patch'
# -- General configuration --------------------------------------------------- # -- General configuration ---------------------------------------------------
......
*************** *********************************
dma_from_device DMA from Device (dma_from_device)
*************** *********************************
dma_from_device is a user application tool provided along with QDMA Linux driver to perform the Card to Host data transfers. dma_from_device is a user application tool provided along with QDMA Linux driver to perform the Card to Host data transfers.
usage: dma_from_device [OPTIONS] usage:
::
[xilinx@]# dma_from_device [OPTIONS]
Read via SGDMA, optionally save output to a file
**OPTIONS**
:: ::
-d (--device) device (defaults to /dev/qdma01000-MM-0) -d (--device) device path from /dev. Device name is formed as qdmabbddf-<mode>-<queue_number>. Ex: /dev/qdma01000-MM-0
-a (--address) the start address on the AXI bus -a (--address) the start address on the AXI bus
-s (--size) size of a single transfer in bytes, default 32. -s (--size) size of a single transfer in bytes, default 32 bytes.
-o (--offset) page offset of transfer -o (--offset) page offset of transfer
-c (--count) number of transfers, default is 1. -c (--count) number of transfers, default is 1.
-f (--file) file to write the data of the transfers -f (--file) file to write the data of the transfers
...@@ -20,7 +25,15 @@ Read via SGDMA, optionally save output to a file ...@@ -20,7 +25,15 @@ Read via SGDMA, optionally save output to a file
-v (--verbose) verbose output -v (--verbose) verbose output
Example:
:: ::
[xilinx@]# dma_from_device -d /dev/qdma01000-ST-1 -s 64 [xilinx@]# dma_from_device -d /dev/qdma01000-ST-1 -s 64
** Average BW = 64, 0.880221 ** Average BW = 64, 0.880221
\ No newline at end of file
**NOTE**:
For ST C2H, the dma_from_device application only tries to perform the C2H transfers and it does not take care of generating the packets. The Packet generation is user logic specific functionality and users of the QDMA IP and driver shall make sure the user logic functionality is implemented and integrated in the bit stream used and appropriate configuration parameters are being set before executing dma_from_device command.
Ex: Xilinx example design user logic functionality requires the number of packets, packet length and queue id to be configured in user logic specific registers and packet generation needs to be triggered by configuring a specic register. This is subject to change as per the user logic design.
\ No newline at end of file
************* *****************************
dma_to_device DMA to Device (dma_to_device)
************* *****************************
dma_to_device is a user application tool provided along with QDMA Linux driver to perform the Host to Card data transfers. dma_to_device is a user application tool provided along with QDMA Linux driver to perform the Host to Card data transfers.
usage: dma_to_device [OPTIONS] usage:
Write via SGDMA, optionally read input from a file. ::
[xilinx@]# dma_to_device [OPTIONS]
**Parameters**
**OPTIONS**
:: ::
-d (--device) device (defaults to /dev/qdma01000-MM-0) -d (--device) device path from /dev. Device name is formed as qdmabbddf-<mode>-<queue_number>. Ex: /dev/qdma01000-MM-0
-a (--address) the start address on the AXI bus -a (--address) the start address on the AXI bus
-s (--size) size of a single transfer in bytes, default 32, -s (--size) size of a single transfer in bytes, default 32 bytes
-o (--offset) page offset of transfer -o (--offset) page offset of transfer
-c (--count) number of transfers, default 1 -c (--count) number of transfers, default 1
-f (--data infile) filename to read the data from. -f (--data input file) filename to read the data from.
-w (--data outfile) filename to write the data of the transfers -w (--data output file) filename to write the data of the transfers
-h (--help) print usage help and exit -h (--help) print usage help and exit
-v (--verbose) verbose output -v (--verbose) verbose output
Example:
:: ::
[xilinx@]# dma_to_device -d /dev/qdma01000-ST-1 -s 64 [xilinx@]# dma_to_device -d /dev/qdma01000-ST-1 -s 64
......
********************* ******************************
DMA Performance Tool DMA Performance Tool (dmaperf)
********************* ******************************
Xilinx-developed custom tool``dmaperf`` is used to collect the performance metrics for unidirectional and bidirectional traffic. Xilinx-developed custom tool``dmaperf`` is used to collect the performance metrics for unidirectional and bidirectional traffic.
The QDMA Linux kernel reference driver is a PCIe device driver, it manages the QDMA queues in the HW. The driver creates a character device for each queue pair configured.
Standard IO tools such as ``fio`` can be used for performing IO operations using the char device interface. Standard IO tools such as ``fio`` can be used for performing IO operations using the char device interface.
However, most of the tools are limited to sending / receiving 1 packet at a time and wait for the processing of the packet to complete, so they are not able to keep the driver/ HW busy enough for performance measurement. Although fio also supports asynchronous interfaces, it does not continuously submit IO requests while polling for the completion in parallel. However, most of the tools are limited to sending / receiving 1 packet at a time and wait for the processing of the packet to complete, so they are not able to keep the driver/ HW busy enough for performance measurement. Although fio also supports asynchronous interfaces, it does not continuously submit IO requests while polling for the completion in parallel.
...@@ -28,11 +26,10 @@ dmaperf tool takes a configuration file as input. The configuration file format ...@@ -28,11 +26,10 @@ dmaperf tool takes a configuration file as input. The configuration file format
dir=bi #dir dir=bi #dir
pf_range=0:0 #no spaces pf_range=0:0 #no spaces
q_range=0:0 #no spaces q_range=0:0 #no spaces
flags= #no spaces
wb_acc=5 wb_acc=5
tmr_idx=9 tmr_idx=9
cntr_idx=0 cntr_idx=0
trig_mode=cntr_tmr trig_mode=usr_cnt
rngidx=9 rngidx=9
ram_width=15 #31 bits - 2^31 = 2GB ram_width=15 #31 bits - 2^31 = 2GB
runtime=30 #secs runtime=30 #secs
...@@ -47,16 +44,16 @@ dmaperf tool takes a configuration file as input. The configuration file format ...@@ -47,16 +44,16 @@ dmaperf tool takes a configuration file as input. The configuration file format
- name : name of the configuration - name : name of the configuration
- mode : mode of the queue, streaming\(st\) or memory mapped\(mm\). Mode defaults to mm. - mode : mode of the queue, streaming\(st\) or memory mapped\(mm\). Mode defaults to mm.
- dir : Direction of the queue, host-to-card\(h2c\), card-to-host \(c2h\) or both \(bi\). - dir : Direction of the queue, host-to-card\(h2c\), card-to-host \(c2h\) or both \(bi\).
- pf_range : Range of the PFs from 0-3 on which the performance metrics to be collected. - pf_range : Range of the PFs from 0-3 on which the performance metrics are to be collected.
- q_range : Range of the Queues from 0-2047 on which the performance metrics to be collected. - q_range : Range of the Queues from 0-2047 on which the performance metrics are to be collected.
- flags : queue flags - flags : queue flags
- wb_acc : write back accumulation index from CSR register - wb_acc : write back accumulation index from CSR register \( 0 - 15 \)
- tmr_idx : timer index from CSR register - tmr_idx : timer index from CSR register \( 0 - 15 \)
- cntr_idx : Counter index from CSR register - cntr_idx : Counter index from CSR register \( 0 - 15 \)
- trig_mode : trigger mode - trig_mode : trigger mode \(every, usr_cnt, usr, usr_tmr, dis\)
- rngidx : Ring index from CSR register - rngidx : Ring index from CSR register \( 0 - 15 \)
- runtime : Duration of the performance runs, time in seconds. - runtime : Duration of the performance runs, time in seconds.
- num_threads : number of threads to be used in dmaperf application to pump the traffic to queues - num_threads : number of threads to be used in dmaperf application to pump the traffic to queues
- bidir_en : Enable the bi-direction or not - bidir_en : Enable or Disable the bi-direction mode \( 0: Disable, 1: Enable \)
- num_pkt : number of packets - num_pkt : number of packets
- pkt_sz : Packet size - pkt_sz : Packet size
\ No newline at end of file \ No newline at end of file
...@@ -6,8 +6,8 @@ QDMA Linux Driver supports the following list of features ...@@ -6,8 +6,8 @@ QDMA Linux Driver supports the following list of features
QDMA Hardware Features QDMA Hardware Features
********************** **********************
* SRIOV with 4 Physical Functions(PF) and 252 Virtual Functions(VF) * SRIOV with 4 Physical Functions (PF) and 252 Virtual Functions (VF)
* Memory Mapped(MM) and Stream(ST) interfaces per queue * Memory Mapped (MM) and Stream (ST) interfaces per queue
* 2048 queue sets * 2048 queue sets
* 2048 H2C (Host-to-Card) descriptor rings * 2048 H2C (Host-to-Card) descriptor rings
...@@ -16,18 +16,19 @@ QDMA Hardware Features ...@@ -16,18 +16,19 @@ QDMA Hardware Features
* Supports Legacy and MSI-X Interrupts * Supports Legacy and MSI-X Interrupts
* 2048 MSI-X vectors. * 2048 MSI-X vectors.
* Up to 8 MSI-X per function. * Up to 32 MSI-X per function.
* Interrupt Aggregation * Interrupt Aggregation
* User Interrupts * User Interrupts
* Error Interrupts * Error Interrupts
* Legacy Interrupts : Supported only for PF0 with single queue
* Legacy Interrupts : Supported only for PF0 with single queue
* Mailbox communication between PF and VF driver * Mailbox communication between PF and VF driver
* Interrupt support for Mailbox events * Interrupt support for Mailbox events
* Flexible interrupt allocation between PF/VF * Flexible interrupt allocation between PF/VF
* HW Error reporting * HW Error reporting
* Zero byte transfers * Zero byte transfers
* Immediate data transfers * Immediate data transfers
* Descriptor bypass(8, 16, 32, 64 descriptor sizes) support * Descriptor bypass (8, 16, 32, 64 bytes descriptor sizes) support
* Descriptor Prefetching * Descriptor Prefetching
* Streaming C2H completion entry coalescing * Streaming C2H completion entry coalescing
* Disabling overflow check in completion ring * Disabling overflow check in completion ring
...@@ -37,6 +38,8 @@ QDMA Hardware Features ...@@ -37,6 +38,8 @@ QDMA Hardware Features
* Flexible BAR mapping for QDMA configuration register space * Flexible BAR mapping for QDMA configuration register space
* ECC support * ECC support
* Completions in memory mapped mode * Completions in memory mapped mode
* Function Level Reset
* User Controlled Completions
For details on Hardware Features refer to QDMA_Product_Guide_. For details on Hardware Features refer to QDMA_Product_Guide_.
...@@ -51,10 +54,10 @@ QDMA Software Features ...@@ -51,10 +54,10 @@ QDMA Software Features
PF and VF drivers can be inserted in different modes. PF and VF drivers can be inserted in different modes.
- Polling Mode - Polling Mode
In Poll Mode, Software polls for the write back completions(Status Descriptor Write Back) In Poll Mode, Software polls for the write back completions (Status Descriptor Write Back)
- Direct Interrupt Mode - Direct Interrupt Mode
In Direct Interrupt mode, Each queue is assigned to one of the available interrupt vectors in a round robin fashion to service the requests. In Direct Interrupt mode, each queue is assigned to one of the available interrupt vectors in a round robin fashion to service the requests.
Interrupt is raised by the HW upon receiving the completions and software reads the completion status. Interrupt is raised by the HW upon receiving the completions and software reads the completion status.
- Indirect Interrupt Mode - Indirect Interrupt Mode
...@@ -67,9 +70,9 @@ QDMA Software Features ...@@ -67,9 +70,9 @@ QDMA Software Features
Auto mode is mix of Poll and Interrupt Aggregation mode. Driver polls for the write back status updates. Auto mode is mix of Poll and Interrupt Aggregation mode. Driver polls for the write back status updates.
Interrupt aggregation is used for processing the completion ring. Interrupt aggregation is used for processing the completion ring.
- Allows only Privileged Physical Functions to program the contexts and registers - Allows only Privileged Physical Function to program the contexts and registers
- Dynamic queue configuration - Dynamic queue configuration, refer to Interface file, libqdma_export.h (struct qdma_queue_conf) for configurable parameters
- Dynamic driver configuration - Dynamic driver configuration, refer to Interface file, libqdma_export.h (struct qdma_dev_conf) for configurable parameters
- Driver configuration through sysfs - Driver configuration through sysfs
- Asynchronous and Synchronous IO support - Asynchronous and Synchronous IO support
- Display the Version details for SW and HW - Display the Version details for SW and HW
\ No newline at end of file
...@@ -4,7 +4,7 @@ Xilinx QDMA Linux Driver ...@@ -4,7 +4,7 @@ Xilinx QDMA Linux Driver
Xilinx QDMA Subsystem for PCIe example design is implemented on a Xilinx FPGA, Xilinx QDMA Subsystem for PCIe example design is implemented on a Xilinx FPGA,
which is connected to an X86 host system through PCI Express. which is connected to an X86 host system through PCI Express.
Xilinx QDMA Linux Driver is implemented as a combination of user space and Xilinx QDMA Linux Driver package consists of user space applications and
kernel driver components to control and configure the QDMA subsystem. kernel driver components to control and configure the QDMA subsystem.
QDMA Linux Driver consists of the following four major components: QDMA Linux Driver consists of the following four major components:
...@@ -21,14 +21,14 @@ QDMA Linux Driver consists of the following four major components: ...@@ -21,14 +21,14 @@ QDMA Linux Driver consists of the following four major components:
- Transfer Management - Transfer Management
- DebugFS Support - DebugFS Support
- **Driver Interface**: This layer create a simple linux pci_driver interface and a character driver interface to demonstrate the QDMA IP functionalities using the Linux QDMA IP driver. It creates a NL interface to facilitate the user applications to interact with the ``Libqdma`` module. It also creates ``sysfs`` interface to enable users to configure and control various QDMA IP parameters. - **Driver Interface**: This layer create a simple linux pci_driver \( struct pci_driver \) interface and a character driver interface \( struct file_operations \) to demonstrate the QDMA IP functionalities using the Linux QDMA IP driver. It creates a netlink \( NL \) interface to facilitate the user applications to interact with the ``Libqdma`` module. It also creates ``sysfs`` interface to enable users to configure and control various QDMA IP parameters.
- **Applications**: QDMA IP Driver provides the following sample applications. - **Applications**: QDMA IP Driver provides the following sample applications.
- Dmactl : This application provides set of commands to configure and control the queues in the system - dmactl : This application provides set of commands to configure and control the queues in the system
- dma_to_device : This application enables the users to perform Host to Card(H2C) transfer - dma_to_device : This application enables the users to perform Host to Card (H2C) transfer
- dma_from_device : This application enables the users to perform Card to Host(C2H) transfer - dma_from_device : This application enables the users to perform Card to Host (C2H) transfer
- Dmaperf : This application provides interfaces to extract performance numbers for QDMA IP in MM and ST modes - dmaperf : This application provides commands to measure performance numbers for QDMA IP in MM and ST modes
.. image:: /images/qdma_linux_driver_architecture.PNG .. image:: /images/qdma_linux_driver_architecture.PNG
......
...@@ -20,7 +20,7 @@ For VM testing, host system must support virtualization and it must be enabled i ...@@ -20,7 +20,7 @@ For VM testing, host system must support virtualization and it must be enabled i
Host System Configuration Host System Configuration
------------------------- -------------------------
Linux QDMA Driver latest release is verified on following Host system configuration for PF and VF functionality Linux QDMA Driver release is verified on following Host system configuration for PF and VF functionality
+--------------------------+-------------------------------------------------------------+ +--------------------------+-------------------------------------------------------------+
| Host System | Configuration Details | | Host System | Configuration Details |
...@@ -41,7 +41,7 @@ Note: QEMU is a hosted virtual machine monitor which emulates the machine's proc ...@@ -41,7 +41,7 @@ Note: QEMU is a hosted virtual machine monitor which emulates the machine's proc
Guest System Configuration Guest System Configuration
-------------------------- --------------------------
Linux QDMA VF Driver latest release is verified on following Host system configuration for VF functionality Linux QDMA VF Driver release is verified on following Guest system configuration for VF functionality
========================= ================================== ========================= ==================================
Guest System(VM) Configuration Details Guest System(VM) Configuration Details
...@@ -53,43 +53,43 @@ Cores 4 ...@@ -53,43 +53,43 @@ Cores 4
========================= ================================== ========================= ==================================
Supported OS List Supported Linux Distributions
------------------ -----------------------------
Linux QDMA Driver also supported on following OS and kernel versions Linux QDMA Driver is supported on the following linux distributions
+-------------------------+-------------+----------------+ +-------------------------+---------------------+----------------+
| Operating System | OS Version | Kernel Version | | Linux Distribution | Version | Kernel Version |
+=========================+=============+================+ +=========================+=====================+================+
| CentOS |7.4-1708 |3.10.0-693 | | CentOS |7.4-1708 |3.10.0-693 |
| +-------------+----------------+ | +---------------------+----------------+
| |7.5-1804 |3.10.0-862 | | |7.5-1804 |3.10.0-862 |
| +-------------+----------------+ | +---------------------+----------------+
| |7.6-1810 |3.10.0-957 | | |7.6-1810 |3.10.0-957 |
+-------------------------+-------------+----------------+ +-------------------------+---------------------+----------------+
|Fedora |28 |4.16 | |Fedora |28 |4.16 |
| +-------------+----------------+ | +---------------------+----------------+
| |29 |4.18 | | |29 |4.18 |
| +-------------+----------------+ | +---------------------+----------------+
| |30 |5.0 | | |30 |5.0 |
+-------------------------+-------------+----------------+ +-------------------------+---------------------+----------------+
|Ubuntu |14.04.06 |4.4.0-93 | |Ubuntu |14.04.06 |4.4.0-93 |
| +-------------+----------------+ | +---------------------+----------------+
| |16.04 |4.10 | | |16.04 |4.10 |
| +-------------+----------------+ | +---------------------+----------------+
| |18.04 |4.15.0-23 | | |18.04 |4.15.0-23 |
| +-------------+----------------+ | +---------------------+----------------+
| |18.04.2 |3.10.0 | | |18.04.2 |3.10.0 |
| +-------------+----------------+ | +---------------------+----------------+
| |18.04.2 |3.10.0 | | |18.04.2 |3.10.0 |
+-------------------------+-------------+----------------+ +-------------------------+---------------------+----------------+
Supported Kernel.org Version List Supported Kernel Versions
--------------------------------- -------------------------
Linux QDMA Driver verified on following kernel.org versions Linux QDMA Driver is verified on following kernel.org Linux kernel versions
+-------------------------+-----------------+ +-------------------------+-----------------+
|Kernel.org | Kernel Version | |Kernel.org | Kernel Version |
...@@ -107,11 +107,10 @@ Linux QDMA Driver verified on following kernel.org versions ...@@ -107,11 +107,10 @@ Linux QDMA Driver verified on following kernel.org versions
| | 5.0.14 | | | 5.0.14 |
+-------------------------+-----------------+ +-------------------------+-----------------+
The following kernel functions shall be included in the OS kernel being used. Make sure that these functions are included in the kernel. The following kernel functions shall be included in the OS kernel version being used. Make sure that these functions are included in the kernel.
- Timer Functions - Timer Functions
- PCIe Functions - PCIe Functions
- Kernel Memory functions - Kernel Memory functions
- Kernel threads
- Memory and GFP Functions - Memory and GFP Functions
...@@ -6,9 +6,7 @@ This section describes the details on controlling and configuring the QDMA IP ...@@ -6,9 +6,7 @@ This section describes the details on controlling and configuring the QDMA IP
System Level Configurations System Level Configurations
--------------------------- ---------------------------
QDMA driver provides the sysfs interface to enable to user to perform system level configurations. QDMA ``PF`` and ``VF`` drivers expose several ``sysfs`` nodes under the ``pci`` device root node. QDMA driver provides the sysfs interface to enable to user to perform system level configurations. QDMA ``PF`` and ``VF`` drivers expose several ``sysfs`` nodes under the ``pci`` device root node. ``sysfs`` provides an interface to configure the module.
Once the qdma module is inserted and until any queue is added into the system and FMAP programming is not done, sysfs provides an interface to configure parameters for the module configuration.
:: ::
...@@ -21,12 +19,13 @@ Once the qdma module is inserted and until any queue is added into the system an ...@@ -21,12 +19,13 @@ Once the qdma module is inserted and until any queue is added into the system an
Based on the above lspci output, traverse to ``/sys/bus/pci/devices/<device node>/qdma`` to find the list of configurable parameters specific to PF or VF driver. Based on the above lspci output, traverse to ``/sys/bus/pci/devices/<device node>/qdma`` to find the list of configurable parameters specific to PF or VF driver.
1. **Instantiates the Virtual Functions** 1. **Instantiate the Virtual Functions**
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
QDMA IP supports 252 Virtual Functions(VFs). ``/sys/bus/pci/devices/<device node>`` provides two configurable entries QDMA IP supports 252 Virtual Functions (VFs). ``/sys/bus/pci/devices/<device node>`` provides two configurable entries
- ``sriov_totalvfs`` : Indicates the maximum number of VFs supported for PF. This is a read only entry having the value the that was configured during bit stream generation.
- ``sriov_totalvfs`` : Indicates the maximum number of VFs supported for PF. This is a read only entry which can be configured during bit stream generation.
- ``sriov_numvfs`` : Enables the user to specify the number of VFs required for a PF - ``sriov_numvfs`` : Enables the user to specify the number of VFs required for a PF
Display the currently supported max VFs: Display the currently supported max VFs:
...@@ -48,14 +47,12 @@ Once the VFS are instantiated, required number of queues can be allocated the VF ...@@ -48,14 +47,12 @@ Once the VFS are instantiated, required number of queues can be allocated the VF
2. **Allocate the Queues to a function** 2. **Allocate the Queues to a function**
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
QDMA IP supports maximum of 2048 queues. By default there are no queues assigned to the functions. QDMA IP supports maximum of 2048 queues. By default, all functions have 0 queues assigned.
``qmax`` configuration parameter enables the user to update the number of queues for a PF. This configuration parameter indicates "Maximum number of queues associated for the current pf". ``qmax`` configuration parameter enables the user to update the number of queues for a PF. This configuration parameter indicates "Maximum number of queues associated for the current pf".
If the queue allocation needs to be different for any PF, access the qmax sysfs entry and set the required number. If the queue allocation needs to be different for any PF, access the qmax sysfs entry and set the required number.
Once the number of queues for any PF is changed from the default value, the remaining set of queues among the 2048 queues are evenly distributed for the remaining PFs.
Display the current value: Display the current value:
:: ::
...@@ -63,7 +60,7 @@ Display the current value: ...@@ -63,7 +60,7 @@ Display the current value:
[xilinx@]# cat /sys/bus/pci/devices/0000:01:00.0/qdma/qmax [xilinx@]# cat /sys/bus/pci/devices/0000:01:00.0/qdma/qmax
0 0
Set a new value: To set 1024 as qmax for PF0:
:: ::
...@@ -76,6 +73,10 @@ Set a new value: ...@@ -76,6 +73,10 @@ Set a new value:
qdma01002 0000:01:00.2 max QP: 0, -~- qdma01002 0000:01:00.2 max QP: 0, -~-
qdma01003 0000:01:00.3 max QP: 0, -~- qdma01003 0000:01:00.3 max QP: 0, -~-
To set 1770 as qmax for PF0, 8 as q max for PF1, PF2, PF3:
::
[xilinx@]# echo 1770 > /sys/bus/pci/devices/0000\:01\:00.0/qdma/qmax [xilinx@]# echo 1770 > /sys/bus/pci/devices/0000\:01\:00.0/qdma/qmax
[xilinx@]# echo 8 > /sys/bus/pci/devices/0000\:01\:00.1/qdma/qmax [xilinx@]# echo 8 > /sys/bus/pci/devices/0000\:01\:00.1/qdma/qmax
[xilinx@]# echo 8 > /sys/bus/pci/devices/0000\:01\:00.2/qdma/qmax [xilinx@]# echo 8 > /sys/bus/pci/devices/0000\:01\:00.2/qdma/qmax
...@@ -89,11 +90,11 @@ Set a new value: ...@@ -89,11 +90,11 @@ Set a new value:
qdma01003 0000:01:00.3 max QP: 8, 1786~1793 qdma01003 0000:01:00.3 max QP: 8, 1786~1793
``qmax`` configuration parameter is available for virtual functions as well. Once the ``qmax_vfs`` is configured, qmax for each VF can be updated from pool of queues assigned for the VFs. ``qmax`` configuration parameter is available for virtual functions as well.
3. **Reserve the Queues to VFs** 3. **Reserve the Queues for VFs**
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
QDMA IP supports 2048 queues and from the set of 2048 queues, use the ``qmax`` sysfs entry to allocate queues to VFs similar to PFs. QDMA IP supports 2048 queues and from the set of 2048 queues, use the ``qmax`` sysfs entry to allocate queues to VFs similar to PFs.
...@@ -105,7 +106,7 @@ Display the current value: ...@@ -105,7 +106,7 @@ Display the current value:
[xilinx@] #cat /sys/bus/pci/devices/0000:81:00.4/qdma/qmax [xilinx@] #cat /sys/bus/pci/devices/0000:81:00.4/qdma/qmax
0 0
Set a new value: To set 1024 as qmax for VF0 of PF0:
:: ::
...@@ -117,9 +118,10 @@ Set a new value: ...@@ -117,9 +118,10 @@ Set a new value:
Interrupt ring size is associated with indirect interrupt mode. Interrupt ring size is associated with indirect interrupt mode.
When the module is inserted in indirect interrupt mode, by default the interrupt aggregation ring size is set 0 i.e 512 entries When the mode is set to indirect interrupt mode, by default the interrupt aggregation ring size is set 0 index value.
Each interrupt aggregation ring entry size is 64 Bytes. Index size 0 refers to 4KB size, i.e 4KB/64 = 512 entries.
User can configure he interrupt ring entries in multiples of 512 hence set the ``intr_rngsz`` with multiplication factor User can configure the interrupt ring entries in multiples of 512 hence set the ``intr_rngsz`` with multiplication factor
| 0 - INTR_RING_SZ_4KB, Accommodates 512 entries | 0 - INTR_RING_SZ_4KB, Accommodates 512 entries
| 1 - INTR_RING_SZ_8KB, Accommodates 1024 entries | 1 - INTR_RING_SZ_8KB, Accommodates 1024 entries
...@@ -127,8 +129,8 @@ User can configure he interrupt ring entries in multiples of 512 hence set the ` ...@@ -127,8 +129,8 @@ User can configure he interrupt ring entries in multiples of 512 hence set the `
| 3 - INTR_RING_SZ_16KB, Accommodates 2048 entries | 3 - INTR_RING_SZ_16KB, Accommodates 2048 entries
| 4 - INTR_RING_SZ_20KB, Accommodates 2560 entries | 4 - INTR_RING_SZ_20KB, Accommodates 2560 entries
| 5 - INTR_RING_SZ_24KB, Accommodates 3072 entries | 5 - INTR_RING_SZ_24KB, Accommodates 3072 entries
| 6 - INTR_RING_SZ_24KB, Accommodates 3584 entries | 6 - INTR_RING_SZ_28KB, Accommodates 3584 entries
| 7 - INTR_RING_SZ_24KB, Accommodates 4096 entries | 7 - INTR_RING_SZ_32KB, Accommodates 4096 entries
Display the current value: Display the current value:
...@@ -137,17 +139,17 @@ Display the current value: ...@@ -137,17 +139,17 @@ Display the current value:
[xilinx@]# cat /sys/bus/pci/devices/0000:81:00.0/qdma/intr_rngsz [xilinx@]# cat /sys/bus/pci/devices/0000:81:00.0/qdma/intr_rngsz
0 0
Set a new value: To set value 2 to intr_rngsz:
:: ::
[xilinx@]# echo 2 > /sys/bus/pci/devices/0000:81:00.0/qdma/intr_rngsz [xilinx@]# echo 2 > /sys/bus/pci/devices/0000:81:00.0/qdma/intr_rngsz
5. **Set Completion Interval** 5. **Set Write Back Interval**
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
``cmpt_intrvl`` indicated the interval at which completions are generated for an MM or H2C Stream queue running in non-bypass mode. ``cmpt_intrvl`` indicated the interval at which write backs are generated for an MM or H2C Stream queue running in non-bypass mode.
User can set any of the following list of values for this configuration parameter. User can set any of the following list of values for this configuration parameter.
| 3'h0: 4 | 3'h0: 4
...@@ -159,9 +161,9 @@ User can set any of the following list of values for this configuration paramete ...@@ -159,9 +161,9 @@ User can set any of the following list of values for this configuration paramete
| 3'h6: 256 | 3'h6: 256
| 3'h7: 512 | 3'h7: 512
Completion accumulation value is calculated as 2^(register bit [2:0]). Maximum accumulation is 512.
Accumulation can be disabled via queue context. Accumulation can be disabled via queue context.
Display the current value: Display the current value:
:: ::
...@@ -169,7 +171,7 @@ Display the current value: ...@@ -169,7 +171,7 @@ Display the current value:
[xilinx@]# cat /sys/bus/pci/devices/0000:81:00.0/qdma/cmpt_intrvl [xilinx@]# cat /sys/bus/pci/devices/0000:81:00.0/qdma/cmpt_intrvl
0 0
Set a new value: To set value 2 to cmpt_intrvl:
:: ::
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
...@@ -72,7 +72,7 @@ enum qdma_cdev_ioctl_cmd { ...@@ -72,7 +72,7 @@ enum qdma_cdev_ioctl_cmd {
QDMA_CDEV_IOCTL_CMDS QDMA_CDEV_IOCTL_CMDS
}; };
struct class *qdma_class; static struct class *qdma_class;
static struct kmem_cache *cdev_cache; static struct kmem_cache *cdev_cache;
static ssize_t cdev_gen_read_write(struct file *file, char __user *buf, static ssize_t cdev_gen_read_write(struct file *file, char __user *buf,
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
......
This diff is collapsed.
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
...@@ -40,7 +40,8 @@ ...@@ -40,7 +40,8 @@
* @return 0: success * @return 0: success
* @return <0: failure * @return <0: failure
*****************************************************************************/ *****************************************************************************/
int xnl_respond_buffer(struct genl_info *info, char *buf, int buflen); int xnl_respond_buffer(struct genl_info *info, char *buf, int buflen,
int error);
int xlnx_nl_init(void); int xlnx_nl_init(void);
void xlnx_nl_exit(void); void xlnx_nl_exit(void);
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
...@@ -76,15 +76,6 @@ module_param(num_threads, uint, 0644); ...@@ -76,15 +76,6 @@ module_param(num_threads, uint, 0644);
MODULE_PARM_DESC(num_threads, MODULE_PARM_DESC(num_threads,
"Number of threads to be created each for request and writeback processing"); "Number of threads to be created each for request and writeback processing");
static unsigned int tm_mode_en;
module_param(tm_mode_en, uint, 0644);
MODULE_PARM_DESC(tm_mode_en,
"Enable Traffic Manager mode for bypass ST H2C xmit. Default disabled");
static unsigned int tm_one_cdh_en;
module_param(tm_one_cdh_en, uint, 0644);
MODULE_PARM_DESC(tm_one_cdh_en,
"Enable 1 CDH for Traffic Manager mode. Default is Zero CDH");
#include "pci_ids.h" #include "pci_ids.h"
...@@ -248,14 +239,10 @@ static ssize_t set_qmax(struct device *dev, ...@@ -248,14 +239,10 @@ static ssize_t set_qmax(struct device *dev,
static ssize_t show_cmpl_status_acc(struct device *dev, static ssize_t show_cmpl_status_acc(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
struct pci_dev *pdev = to_pci_dev(dev);
struct xlnx_pci_dev *xpdev; struct xlnx_pci_dev *xpdev;
int len; int len;
unsigned int cmpl_status_acc = 0; unsigned int cmpl_status_acc = 0;
if (!pdev)
return -EINVAL;
xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev);
if (!xpdev) if (!xpdev)
return -EINVAL; return -EINVAL;
...@@ -335,15 +322,11 @@ static ssize_t set_cmpl_status_acc(struct device *dev, ...@@ -335,15 +322,11 @@ static ssize_t set_cmpl_status_acc(struct device *dev,
static ssize_t show_c2h_buf_sz(struct device *dev, static ssize_t show_c2h_buf_sz(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
struct pci_dev *pdev = to_pci_dev(dev);
struct xlnx_pci_dev *xpdev; struct xlnx_pci_dev *xpdev;
int len = 0; int len = 0;
int i; int i;
unsigned int c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; unsigned int c2h_buf_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0};
if (!pdev)
return -EINVAL;
xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev);
if (!xpdev) if (!xpdev)
return -EINVAL; return -EINVAL;
...@@ -449,15 +432,11 @@ input_err: ...@@ -449,15 +432,11 @@ input_err:
static ssize_t show_glbl_rng_sz(struct device *dev, static ssize_t show_glbl_rng_sz(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
struct pci_dev *pdev = to_pci_dev(dev);
struct xlnx_pci_dev *xpdev; struct xlnx_pci_dev *xpdev;
int len = 0; int len = 0;
int i; int i;
unsigned int glbl_ring_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; unsigned int glbl_ring_sz[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0};
if (!pdev)
return -EINVAL;
xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev);
if (!xpdev) if (!xpdev)
return -EINVAL; return -EINVAL;
...@@ -562,15 +541,11 @@ input_err: ...@@ -562,15 +541,11 @@ input_err:
static ssize_t show_c2h_timer_cnt(struct device *dev, static ssize_t show_c2h_timer_cnt(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
struct pci_dev *pdev = to_pci_dev(dev);
struct xlnx_pci_dev *xpdev; struct xlnx_pci_dev *xpdev;
int len = 0; int len = 0;
int i; int i;
unsigned int c2h_timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; unsigned int c2h_timer_cnt[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0};
if (!pdev)
return -EINVAL;
xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev);
if (!xpdev) if (!xpdev)
return -EINVAL; return -EINVAL;
...@@ -679,15 +654,11 @@ input_err: ...@@ -679,15 +654,11 @@ input_err:
static ssize_t show_c2h_cnt_th(struct device *dev, static ssize_t show_c2h_cnt_th(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
struct pci_dev *pdev = to_pci_dev(dev);
struct xlnx_pci_dev *xpdev; struct xlnx_pci_dev *xpdev;
int len = 0; int len = 0;
int i; int i;
unsigned int c2h_cnt_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0}; unsigned int c2h_cnt_th[QDMA_GLOBAL_CSR_ARRAY_SZ] = {0};
if (!pdev)
return -EINVAL;
xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev); xpdev = (struct xlnx_pci_dev *)dev_get_drvdata(dev);
if (!xpdev) if (!xpdev)
return -EINVAL; return -EINVAL;
...@@ -1295,28 +1266,6 @@ q_start: ...@@ -1295,28 +1266,6 @@ q_start:
goto send_resp; goto send_resp;
} }
#ifndef __QDMA_VF__
{
struct xlnx_dma_dev *xdev =
(struct xlnx_dma_dev *)(xpdev->dev_hndl);
if (xdev->stm_en) {
rv = qdma_queue_prog_stm(xpdev->dev_hndl,
qdata->qhndl,
ebuf, nl_work->buflen);
if (rv < 0) {
pr_info("%s, idx %u, c2h %u, prog stm failed %d.\n",
dev_name(&xpdev->pdev->dev),
qidx, c2h, rv);
snprintf(ebuf, nl_work->buflen,
"Q idx %u, c2h %u, prog stm failed %d.\n",
qidx, c2h, rv);
goto send_resp;
}
}
}
#endif
if (is_qp && c2h == qctrl->is_c2h) { if (is_qp && c2h == qctrl->is_c2h) {
c2h = !qctrl->is_c2h; c2h = !qctrl->is_c2h;
goto q_start; goto q_start;
...@@ -1378,7 +1327,7 @@ int xpdev_nl_queue_start(struct xlnx_pci_dev *xpdev, void *nl_info, u8 is_qp, ...@@ -1378,7 +1327,7 @@ int xpdev_nl_queue_start(struct xlnx_pci_dev *xpdev, void *nl_info, u8 is_qp,
wait_event_interruptible(nl_work->wq, nl_work->q_start_handled); wait_event_interruptible(nl_work->wq, nl_work->q_start_handled);
rv = nl_work->ret; rv = nl_work->ret;
kfree(nl_work); kfree(nl_work);
xnl_respond_buffer(nl_info, ebuf, strlen(ebuf)); xnl_respond_buffer(nl_info, ebuf, strlen(ebuf), rv);
return rv; return rv;
} }
...@@ -1633,8 +1582,6 @@ static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id) ...@@ -1633,8 +1582,6 @@ static int probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
intr_legacy_init(); intr_legacy_init();
conf.intr_rngsz = QDMA_INTR_COAL_RING_SIZE; conf.intr_rngsz = QDMA_INTR_COAL_RING_SIZE;
conf.tm_mode_en = tm_mode_en;
conf.tm_one_cdh_en = tm_one_cdh_en;
conf.pdev = pdev; conf.pdev = pdev;
/* initialize all the bar numbers with -1 */ /* initialize all the bar numbers with -1 */
...@@ -1903,7 +1850,7 @@ static int __init qdma_mod_init(void) ...@@ -1903,7 +1850,7 @@ static int __init qdma_mod_init(void)
pr_info("%s", version); pr_info("%s", version);
rv = libqdma_init(num_threads); rv = libqdma_init(num_threads, NULL);
if (rv < 0) if (rv < 0)
return rv; return rv;
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is licensed under both the BSD-style license (found in the * This source code is licensed under both the BSD-style license (found in the
...@@ -22,11 +22,11 @@ ...@@ -22,11 +22,11 @@
#define DRV_MODULE_NAME "qdma_pf" #define DRV_MODULE_NAME "qdma_pf"
#define DRV_MODULE_DESC "Xilinx QDMA PF Reference Driver" #define DRV_MODULE_DESC "Xilinx QDMA PF Reference Driver"
#endif /* #ifdef __QDMA_VF__ */ #endif /* #ifdef __QDMA_VF__ */
#define DRV_MODULE_RELDATE "Jun. 2019" #define DRV_MODULE_RELDATE "July 2019"
#define DRV_MOD_MAJOR 2019 #define DRV_MOD_MAJOR 2019
#define DRV_MOD_MINOR 1 #define DRV_MOD_MINOR 1
#define DRV_MOD_PATCHLEVEL 121 #define DRV_MOD_PATCHLEVEL 125
#define DRV_MODULE_VERSION \ #define DRV_MODULE_VERSION \
__stringify(DRV_MOD_MAJOR) "." \ __stringify(DRV_MOD_MAJOR) "." \
...@@ -35,6 +35,6 @@ ...@@ -35,6 +35,6 @@
__stringify(LIBQDMA_VERSION_PATCH) "." \ __stringify(LIBQDMA_VERSION_PATCH) "." \
#define DRV_MOD_VERSION_NUMBER \ #define DRV_MOD_VERSION_NUMBER \
((DRV_MOD_MAJOR)*1000 + (DRV_MOD_MINOR)*100 + DRV_MOD_PATCHLEVEL) ((DRV_MOD_MAJOR)*10000 + (DRV_MOD_MINOR)*1000 + DRV_MOD_PATCHLEVEL)
#endif /* ifndef __QDMA_VERSION_H__ */ #endif /* ifndef __QDMA_VERSION_H__ */
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
...@@ -140,6 +140,7 @@ enum xnl_attr_t { ...@@ -140,6 +140,7 @@ enum xnl_attr_t {
XNL_ATTR_CMPT_TIMER_IDX, /**< completion timer index */ XNL_ATTR_CMPT_TIMER_IDX, /**< completion timer index */
XNL_ATTR_CMPT_CNTR_IDX, /**< completion counter index */ XNL_ATTR_CMPT_CNTR_IDX, /**< completion counter index */
XNL_ATTR_CMPT_TRIG_MODE, /**< completion trigger mode */ XNL_ATTR_CMPT_TRIG_MODE, /**< completion trigger mode */
XNL_ATTR_CMPT_ENTRIES_CNT, /**< completion entries count */
XNL_ATTR_RANGE_START, /**< range start */ XNL_ATTR_RANGE_START, /**< range start */
XNL_ATTR_RANGE_END, /**< range end */ XNL_ATTR_RANGE_END, /**< range end */
...@@ -155,6 +156,7 @@ enum xnl_attr_t { ...@@ -155,6 +156,7 @@ enum xnl_attr_t {
XNL_ATTR_PIPE_TDEST, /**< pipe tdest */ XNL_ATTR_PIPE_TDEST, /**< pipe tdest */
XNL_ATTR_DEV_STM_BAR, /**< device STM bar number */ XNL_ATTR_DEV_STM_BAR, /**< device STM bar number */
XNL_ATTR_Q_STATE, XNL_ATTR_Q_STATE,
XNL_ATTR_ERROR,
#ifdef ERR_DEBUG #ifdef ERR_DEBUG
XNL_ATTR_QPARAM_ERR_INFO, /**< queue param info */ XNL_ATTR_QPARAM_ERR_INFO, /**< queue param info */
#endif #endif
...@@ -213,6 +215,15 @@ static const char *xnl_attr_str[XNL_ATTR_MAX + 1] = { ...@@ -213,6 +215,15 @@ static const char *xnl_attr_str[XNL_ATTR_MAX + 1] = {
"DEV_USR_BAR", /**< XNL_ATTR_DEV_USER_BAR */ "DEV_USR_BAR", /**< XNL_ATTR_DEV_USER_BAR */
"DEV_QSETMAX", /**< XNL_ATTR_DEV_QSET_MAX */ "DEV_QSETMAX", /**< XNL_ATTR_DEV_QSET_MAX */
"DEV_QBASE", /**< XNL_ATTR_DEV_QSET_QBASE */ "DEV_QBASE", /**< XNL_ATTR_DEV_QSET_QBASE */
"VERSION_INFO", /**< XNL_ATTR_VERSION_INFO */
"DEV_NUMQS", /**<XNL_ATTR_DEV_NUMQS */
"DEV_NUM_PFS", /**<XNL_ATTR_DEV_NUM_PFS */
"DEV_MM_CHANNEL_MAX", /**<XNL_ATTR_DEV_MM_CHANNEL_MAX */
"DEV_MAILBOX_ENABLE", /**<XNL_ATTR_DEV_MAILBOX_ENABLE */
"DEV_FLR_PRESENT", /**<XNL_ATTR_DEV_FLR_PRESENT */
"DEV_ST_ENABLE", /**<XNL_ATTR_DEV_ST_ENABLE */
"DEV_MM_ENABLE", /**<XNL_ATTR_DEV_MM_ENABLE */
"DEV_MM_CMPT_ENABLE", /**<XNL_ATTR_DEV_MM_CMPT_ENABLE */
"REG_BAR", /**< XNL_ATTR_REG_BAR_NUM */ "REG_BAR", /**< XNL_ATTR_REG_BAR_NUM */
"REG_ADDR", /**< XNL_ATTR_REG_ADDR */ "REG_ADDR", /**< XNL_ATTR_REG_ADDR */
"REG_VAL", /**< XNL_ATTR_REG_VAL */ "REG_VAL", /**< XNL_ATTR_REG_VAL */
...@@ -245,6 +256,7 @@ static const char *xnl_attr_str[XNL_ATTR_MAX + 1] = { ...@@ -245,6 +256,7 @@ static const char *xnl_attr_str[XNL_ATTR_MAX + 1] = {
"QPARAM_ERR_INFO", /**< queue param info */ "QPARAM_ERR_INFO", /**< queue param info */
#endif #endif
"ATTR_MAX", "ATTR_MAX",
}; };
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2018-present, Xilinx, Inc. * Copyright (c) 2018-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is licensed under both the BSD-style license (found in the * This source code is licensed under both the BSD-style license (found in the
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2018-present, Xilinx, Inc. * Copyright (c) 2018-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is licensed under both the BSD-style license (found in the * This source code is licensed under both the BSD-style license (found in the
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
...@@ -63,23 +63,30 @@ int qdma_set_qmax(unsigned long dev_hndl, int qbase, u32 qsets_max) ...@@ -63,23 +63,30 @@ int qdma_set_qmax(unsigned long dev_hndl, int qbase, u32 qsets_max)
/* update the device with requested qmax and qbase */ /* update the device with requested qmax and qbase */
rv = qdma_dev_update(xdev->conf.pdev->bus->number, rv = qdma_dev_update(xdev->conf.pdev->bus->number,
xdev->func_id, qsets_max, &qbase); xdev->func_id, qsets_max, &qbase);
if (rv < 0) if (unlikely(rv < 0)) {
pr_err("Failed to update dev entry with error = %d", rv);
return -EINVAL; return -EINVAL;
}
qdma_device_cleanup(xdev); qdma_device_cleanup(xdev);
rv = qdma_dev_qinfo_get(xdev->conf.pdev->bus->number, rv = qdma_dev_qinfo_get(xdev->conf.pdev->bus->number,
xdev->func_id, &qbase, &qsets_max); xdev->func_id, &qbase, &qsets_max);
if (rv < 0) if (unlikely(rv < 0)) {
pr_err("Failed to get qinfo with error = %d", rv);
return -EINVAL; return -EINVAL;
}
xdev->conf.qsets_max = qsets_max; xdev->conf.qsets_max = qsets_max;
xdev->conf.qsets_base = qbase; xdev->conf.qsets_base = qbase;
rv = qdma_device_init(xdev); rv = qdma_device_init(xdev);
if (rv < 0) { if (unlikely(rv < 0)) {
pr_warn("qdma_init failed %d.\n", rv); pr_warn("qdma_init failed with error = %d.\n", rv);
qdma_device_cleanup(xdev); qdma_device_cleanup(xdev);
return -EINVAL;
} }
return QDMA_OPERATION_SUCCESSFUL; return 0;
} }
/*****************************************************************************/ /*****************************************************************************/
/** /**
...@@ -171,7 +178,7 @@ int qdma_set_intr_rngsz(unsigned long dev_hndl, u32 intr_rngsz) ...@@ -171,7 +178,7 @@ int qdma_set_intr_rngsz(unsigned long dev_hndl, u32 intr_rngsz)
xdev->conf.intr_rngsz = intr_rngsz; xdev->conf.intr_rngsz = intr_rngsz;
qdma_device_interrupt_setup(xdev); qdma_device_interrupt_setup(xdev);
return QDMA_OPERATION_SUCCESSFUL; return 0;
} }
/*****************************************************************************/ /*****************************************************************************/
...@@ -249,14 +256,16 @@ int qdma_set_buf_sz(unsigned long dev_hndl, u32 *buf_sz) ...@@ -249,14 +256,16 @@ int qdma_set_buf_sz(unsigned long dev_hndl, u32 *buf_sz)
*/ */
rv = qdma_set_global_buffer_sizes(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, rv = qdma_set_global_buffer_sizes(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ,
buf_sz); buf_sz);
if (rv < 0) if (unlikely(rv < 0)) {
return -EINVAL; pr_err("set global buffer size failed with error = %d", rv);
return qdma_get_error_code(rv);
qdma_csr_read(xdev, &xdev->csr_info); }
rv = qdma_csr_read(xdev, &xdev->csr_info);
if (unlikely(rv < 0))
return rv;
return rv; return 0;
} }
#endif #endif
...@@ -284,7 +293,7 @@ unsigned int qdma_get_buf_sz(unsigned long dev_hndl, u32 *buf_sz) ...@@ -284,7 +293,7 @@ unsigned int qdma_get_buf_sz(unsigned long dev_hndl, u32 *buf_sz)
buf_sz)) buf_sz))
return -EINVAL; return -EINVAL;
return QDMA_OPERATION_SUCCESSFUL; return 0;
} }
#ifdef QDMA_CSR_REG_UPDATE #ifdef QDMA_CSR_REG_UPDATE
...@@ -324,12 +333,14 @@ int qdma_set_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz) ...@@ -324,12 +333,14 @@ int qdma_set_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz)
*/ */
rv = qdma_set_ring_sizes(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, rv = qdma_set_ring_sizes(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ,
glbl_rng_sz); glbl_rng_sz);
if (rv < 0) if (unlikely(rv < 0))
return -EINVAL; return -EINVAL;
qdma_csr_read(xdev, &xdev->csr_info); rv = qdma_csr_read(xdev, &xdev->csr_info);
if (unlikely(rv < 0))
return rv;
return rv; return 0;
} }
#endif #endif
...@@ -357,7 +368,7 @@ unsigned int qdma_get_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz) ...@@ -357,7 +368,7 @@ unsigned int qdma_get_glbl_rng_sz(unsigned long dev_hndl, u32 *glbl_rng_sz)
glbl_rng_sz)) glbl_rng_sz))
return -EINVAL; return -EINVAL;
return QDMA_OPERATION_SUCCESSFUL; return 0;
} }
#ifdef QDMA_CSR_REG_UPDATE #ifdef QDMA_CSR_REG_UPDATE
...@@ -391,15 +402,16 @@ int qdma_set_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt) ...@@ -391,15 +402,16 @@ int qdma_set_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt)
rv = qdma_set_global_timer_count(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, rv = qdma_set_global_timer_count(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ,
tmr_cnt); tmr_cnt);
if (rv < 0) { if (unlikely(rv < 0)) {
if (rv == -QDMA_FEATURE_NOT_SUPPORTED) pr_err("global timer set failed with error = %d", rv);
return -EPERM; return qdma_get_error_code(rv);
else
return -EINVAL;
} }
qdma_csr_read(xdev, &xdev->csr_info);
return rv; rv = qdma_csr_read(xdev, &xdev->csr_info);
if (unlikely(rv < 0))
return rv;
return 0;
} }
#endif #endif
...@@ -426,14 +438,12 @@ unsigned int qdma_get_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt) ...@@ -426,14 +438,12 @@ unsigned int qdma_get_timer_cnt(unsigned long dev_hndl, u32 *tmr_cnt)
rv = qdma_get_global_timer_count(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ, rv = qdma_get_global_timer_count(xdev, 0, QDMA_GLOBAL_CSR_ARRAY_SZ,
tmr_cnt); tmr_cnt);
if (rv < 0) { if (unlikely(rv < 0)) {
if (rv == -QDMA_FEATURE_NOT_SUPPORTED) pr_err("get global timer failed with error = %d", rv);
return -EPERM; return qdma_get_error_code(rv);
else
return -EINVAL;
} }
return QDMA_OPERATION_SUCCESSFUL; return 0;
} }
#ifdef QDMA_CSR_REG_UPDATE #ifdef QDMA_CSR_REG_UPDATE
...@@ -466,15 +476,16 @@ int qdma_set_cnt_thresh(unsigned long dev_hndl, unsigned int *cnt_th) ...@@ -466,15 +476,16 @@ int qdma_set_cnt_thresh(unsigned long dev_hndl, unsigned int *cnt_th)
rv = qdma_set_global_counter_threshold(xdev, 0, rv = qdma_set_global_counter_threshold(xdev, 0,
QDMA_GLOBAL_CSR_ARRAY_SZ, cnt_th); QDMA_GLOBAL_CSR_ARRAY_SZ, cnt_th);
if (rv < 0) { if (unlikely(rv < 0)) {
if (rv == -QDMA_FEATURE_NOT_SUPPORTED) pr_err("set global counter failed with error = %d", rv);
return -EPERM; return qdma_get_error_code(rv);
else
return -EINVAL;
} }
qdma_csr_read(xdev, &xdev->csr_info);
return rv; rv = qdma_csr_read(xdev, &xdev->csr_info);
if (unlikely(rv < 0))
return rv;
return 0;
} }
#endif #endif
...@@ -501,14 +512,12 @@ unsigned int qdma_get_cnt_thresh(unsigned long dev_hndl, u32 *cnt_th) ...@@ -501,14 +512,12 @@ unsigned int qdma_get_cnt_thresh(unsigned long dev_hndl, u32 *cnt_th)
rv = qdma_get_global_counter_threshold(xdev, 0, rv = qdma_get_global_counter_threshold(xdev, 0,
QDMA_GLOBAL_CSR_ARRAY_SZ, cnt_th); QDMA_GLOBAL_CSR_ARRAY_SZ, cnt_th);
if (rv < 0) { if (unlikely(rv < 0)) {
if (rv == -QDMA_FEATURE_NOT_SUPPORTED) pr_err("get global counter failed with error = %d", rv);
return -EPERM; return qdma_get_error_code(rv);
else
return -EINVAL;
} }
return QDMA_OPERATION_SUCCESSFUL; return 0;
} }
#ifdef QDMA_CSR_REG_UPDATE #ifdef QDMA_CSR_REG_UPDATE
...@@ -546,15 +555,16 @@ int qdma_set_cmpl_status_acc(unsigned long dev_hndl, u32 cmpl_status_acc) ...@@ -546,15 +555,16 @@ int qdma_set_cmpl_status_acc(unsigned long dev_hndl, u32 cmpl_status_acc)
* Write the given cmpl_status_acc value to the register * Write the given cmpl_status_acc value to the register
*/ */
rv = qdma_set_global_writeback_interval(xdev, cmpl_status_acc); rv = qdma_set_global_writeback_interval(xdev, cmpl_status_acc);
if (rv < 0) { if (unlikely(rv < 0)) {
if (rv == -QDMA_FEATURE_NOT_SUPPORTED) pr_err("set global writeback intvl failed with error = %d", rv);
return -EPERM; return qdma_get_error_code(rv);
else
return -EINVAL;
} }
qdma_csr_read(xdev, &xdev->csr_info);
return QDMA_OPERATION_SUCCESSFUL; rv = qdma_csr_read(xdev, &xdev->csr_info);
if (unlikely(rv < 0))
return rv;
return 0;
} }
#endif #endif
...@@ -587,11 +597,9 @@ unsigned int qdma_get_wb_intvl(unsigned long dev_hndl) ...@@ -587,11 +597,9 @@ unsigned int qdma_get_wb_intvl(unsigned long dev_hndl)
* Read the current cmpl_status_acc value from the register and return * Read the current cmpl_status_acc value from the register and return
*/ */
rv = qdma_get_global_writeback_interval(xdev, &wb_intvl); rv = qdma_get_global_writeback_interval(xdev, &wb_intvl);
if (rv < 0) { if (unlikely(rv < 0)) {
if (rv == -QDMA_FEATURE_NOT_SUPPORTED) pr_err("get global writeback intvl failed with error = %d", rv);
return -EPERM; return qdma_get_error_code(rv);
else
return -EINVAL;
} }
return wb_intvl; return wb_intvl;
......
/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
......
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/* /*
* This file is part of the Xilinx DMA IP Core driver for Linux * This file is part of the Xilinx DMA IP Core driver for Linux
* *
* Copyright (c) 2017-present, Xilinx, Inc. * Copyright (c) 2017-2019, Xilinx, Inc.
* All rights reserved. * All rights reserved.
* *
* This source code is free software; you can redistribute it and/or modify it * This source code is free software; you can redistribute it and/or modify it
...@@ -38,69 +38,23 @@ ...@@ -38,69 +38,23 @@
#define QDMA_FUNC_ID_INVALID (QDMA_PF_MAX + QDMA_VF_MAX) #define QDMA_FUNC_ID_INVALID (QDMA_PF_MAX + QDMA_VF_MAX)
/** /**
* enum qdma_error_codes - List of QDMA error codes * enum qdma_q_mode - mode in which Q is initialized
*
* When libqdma APIs are invoked by application, if any error occured,
* the corresponding error code would be returned.
*
*/ */
enum qdma_error_codes { enum qdma_q_mode {
/** @QDMA_OPERATION_SUCCESSFUL: QDMA driver API operation successful */ /** @QDMA_Q_MODE_MM: MM mode */
QDMA_OPERATION_SUCCESSFUL = 0, QDMA_Q_MODE_MM,
/** @QDMA_ERR_PCI_DEVICE_NOT_FOUND: not found on the PCIe bus */ /** @QDMA_Q_MODE_ST: ST mode */
QDMA_ERR_PCI_DEVICE_NOT_FOUND = -1, QDMA_Q_MODE_ST
/** @QDMA_ERR_PCI_DEVICE_ALREADY_ATTACHED: device already attached */ };
QDMA_ERR_PCI_DEVICE_ALREADY_ATTACHED = -2,
/** /**
* @QDMA_ERR_PCI_DEVICE_ENABLE_FAILED: Failed to enable the PCIe device * enum qdma_q_dir - direction in which Q is initialized
*/ */
QDMA_ERR_PCI_DEVICE_ENABLE_FAILED = -3, enum qdma_q_dir {
/** @QDMA_ERR_PCI_DEVICE_INIT_FAILED: Failed to initialize the device */ /** @QDMA_Q_DIR_H2C: host to card */
QDMA_ERR_PCI_DEVICE_INIT_FAILED = -4, QDMA_Q_DIR_H2C,
/** @QDMA_ERR_INVALID_INPUT_PARAM: Invalid input parameter received */ /** @QDMA_Q_DIR_C2H: card to host */
QDMA_ERR_INVALID_INPUT_PARAM = -5, QDMA_Q_DIR_C2H
/** @QDMA_ERR_INVALID_PCI_DEV: Invalid PCIe device */
QDMA_ERR_INVALID_PCI_DEV = -6,
/** @QDMA_ERR_INVALID_QIDX: Invalid Queue ID provided as input */
QDMA_ERR_INVALID_QIDX = -7,
/**
* @QDMA_ERR_INVALID_DESCQ_STATE: Invalid descriptor queue state
*/
QDMA_ERR_INVALID_DESCQ_STATE = -8,
/**
* @QDMA_ERR_INVALID_DIRECTION: Invalid descriptor direction provided
*/
QDMA_ERR_INVALID_DIRECTION = -9,
/**
* @QDMA_ERR_DESCQ_SETUP_FAILED: Failed to setup the descriptor queue
*/
QDMA_ERR_DESCQ_SETUP_FAILED = -10,
/** @QDMA_ERR_DESCQ_FULL: Descriptor queue is full */
QDMA_ERR_DESCQ_FULL = -11,
/**
* @QDMA_ERR_DESCQ_IDX_ALREADY_ADDED: Descriptor queue
* index is already added
*/
QDMA_ERR_DESCQ_IDX_ALREADY_ADDED = -12,
/** @QDMA_ERR_QUEUE_ALREADY_CONFIGURED: Queue is already configured */
QDMA_ERR_QUEUE_ALREADY_CONFIGURED = -13,
/** @QDMA_ERR_OUT_OF_MEMORY: Out of memory */
QDMA_ERR_OUT_OF_MEMORY = -14,
/**
* @QDMA_ERR_INVALID_QDMA_DEVICE: Invalid QDMA device, QDMA device
* is not yet created
*/
QDMA_ERR_INVALID_QDMA_DEVICE = -15,
/**
* @QDMA_ERR_INTERFACE_NOT_ENABLED_IN_DEVICE : The ST or MM or Both
* interface not enabled in the device
*/
QDMA_ERR_INTERFACE_NOT_ENABLED_IN_DEVICE = -16,
/**
* @QDMA_ERR_MISSING_DEVICE_CAPABILITY : Device capability is
* missing
*/
QDMA_ERR_MISSING_DEVICE_CAPABILITY = -17,
}; };
/** /**
...@@ -144,6 +98,26 @@ struct drv_mode_name { ...@@ -144,6 +98,26 @@ struct drv_mode_name {
char name[20]; char name[20];
}; };
struct qdma_ul_cmpt_info {
/* cmpl entry stat bits */
union {
u8 fbits;
struct cmpl_flag {
u8 format:1;
u8 color:1;
u8 err:1;
u8 desc_used:1;
u8 eot:1;
u8 filler:3;
} f;
};
u8 rsvd;
u16 len;
/* for tracking */
unsigned int pidx;
__be64 *entry;
};
extern struct drv_mode_name mode_name_list[]; extern struct drv_mode_name mode_name_list[];
struct pci_dev; struct pci_dev;
...@@ -155,10 +129,12 @@ struct pci_dev; ...@@ -155,10 +129,12 @@ struct pci_dev;
* @num_threads: number of threads to be created each for request * @num_threads: number of threads to be created each for request
* processing and writeback processing * processing and writeback processing
* *
* @debugfs_root: root path for debugfs
*
* Return: 0: success <0: error * Return: 0: success <0: error
* *
*****************************************************************************/ *****************************************************************************/
int libqdma_init(unsigned int num_threads); int libqdma_init(unsigned int num_threads, void *debugfs_root);
/*****************************************************************************/ /*****************************************************************************/
/** /**
...@@ -250,11 +226,6 @@ struct qdma_dev_conf { ...@@ -250,11 +226,6 @@ struct qdma_dev_conf {
* is master_pf or not * is master_pf or not
*/ */
u8 master_pf:1; u8 master_pf:1;
/**
* @isr_top_q_en: extra handling of per descq handling in top half
* (i.e., qdma_descq.fp_descq_isr_top will be set)
*/
u8 isr_top_q_en:1;
/** @rsvd1: Reserved1 */ /** @rsvd1: Reserved1 */
u8 rsvd1:5; u8 rsvd1:5;
/** /**
...@@ -304,19 +275,12 @@ struct qdma_dev_conf { ...@@ -304,19 +275,12 @@ struct qdma_dev_conf {
char bar_num_user; char bar_num_user;
/** @bar_num_bypass: bypass bar */ /** @bar_num_bypass: bypass bar */
char bar_num_bypass; char bar_num_bypass;
/** @bar_num_stm: STM bar, PF only */
char bar_num_stm;
/** @qsets_base: queue base for this funciton */ /** @qsets_base: queue base for this funciton */
int qsets_base; int qsets_base;
/** @bdf: device index */ /** @bdf: device index */
u32 bdf; u32 bdf;
/** @idx: index of device in device list */ /** @idx: index of device in device list */
u32 idx; u32 idx;
/** @tm_mode_en: xmit in traffic manager mode */
u8 tm_mode_en;
/** @tm_one_cdh_en: enable 1 CDH for Traffic Manager */
u8 tm_one_cdh_en;
/** /**
* @fp_user_isr_handler: user interrupt, if null, * @fp_user_isr_handler: user interrupt, if null,
* default libqdma handler is used * default libqdma handler is used
...@@ -328,6 +292,10 @@ struct qdma_dev_conf { ...@@ -328,6 +292,10 @@ struct qdma_dev_conf {
* per-device addtional handling code * per-device addtional handling code
*/ */
void (*fp_q_isr_top_dev)(unsigned long dev_hndl, unsigned long uld); void (*fp_q_isr_top_dev)(unsigned long dev_hndl, unsigned long uld);
/**
* @debugfs_dev_root: root path for debugfs
*/
void *debugfs_dev_root;
}; };
/*****************************************************************************/ /*****************************************************************************/
...@@ -713,6 +681,9 @@ struct qdma_sw_sg { ...@@ -713,6 +681,9 @@ struct qdma_sw_sg {
/** invalid MSI-x vector index */ /** invalid MSI-x vector index */
#define QDMA_QUEUE_VEC_INVALID 0xFF #define QDMA_QUEUE_VEC_INVALID 0xFF
/** struct qdma_request forward declaration*/
struct qdma_request;
/** /**
* struct qdma_queue_conf - qdma configuration parameters * struct qdma_queue_conf - qdma configuration parameters
* *
...@@ -760,8 +731,6 @@ struct qdma_queue_conf { ...@@ -760,8 +731,6 @@ struct qdma_queue_conf {
* (i.e., with TLAST to identify the packet boundary) * (i.e., with TLAST to identify the packet boundary)
*/ */
u8 st_pkt_mode:1; u8 st_pkt_mode:1;
/** @c2h_use_fl: c2h use pre-alloc free list */
u8 c2h_use_fl:1;
/** config flags: byte #3 */ /** config flags: byte #3 */
/** @c2h_buf_sz_idx: global_csr_conf.c2h_buf_sz[N] */ /** @c2h_buf_sz_idx: global_csr_conf.c2h_buf_sz[N] */
...@@ -800,6 +769,8 @@ struct qdma_queue_conf { ...@@ -800,6 +769,8 @@ struct qdma_queue_conf {
u8 port_id:3; u8 port_id:3;
/** @at: Address Translation */ /** @at: Address Translation */
u8 at:1; u8 at:1;
/** @init_pidx_dis : Disable pidx initialiaztion for ST C2H */
u8 init_pidx_dis:1;
/** @en_mm_cmpt: MM Completions enabled? */ /** @en_mm_cmpt: MM Completions enabled? */
u8 en_mm_cmpt; u8 en_mm_cmpt;
...@@ -855,6 +826,34 @@ struct qdma_queue_conf { ...@@ -855,6 +826,34 @@ struct qdma_queue_conf {
int (*fp_descq_c2h_packet)(unsigned long qhndl, unsigned long quld, int (*fp_descq_c2h_packet)(unsigned long qhndl, unsigned long quld,
unsigned int len, unsigned int sgcnt, unsigned int len, unsigned int sgcnt,
struct qdma_sw_sg *sgl, void *udd); struct qdma_sw_sg *sgl, void *udd);
/**
* @fp_bypass_desc_fill: fill the all the descriptors required for
* transfer
*
* q_hndl: handle with which bypass module can request back info from libqdma
* q_mode: mode in which q is initialized
* q_dir: diretion in which q is intialized
* sgcnt: number of sctter gather entries for this request
* sgl: lsit of scatter gather entries
*
*
* On calling this API, bypass module can request for descriptor using
* qdma_q_desc_get and set up as many descriptors as required for each
* scatter gather entry. If descriptors required are not available,
* it can return the number of sgcnt addressed till now and return <0
* in case of any failure
*/
int (*fp_bypass_desc_fill)(void *q_hndl, enum qdma_q_mode q_mode,
enum qdma_q_dir, struct qdma_request *req);
/**
* @fp_proc_ul_cmpt_entry: parse cmpt entry in bypass mode
* q_mode: mode in which q is initialized
* cmpt_entry: cmpt entry descriptor
* cmpt_info: parsed bypass releated info from cmpt_entry
*
*/
int (*fp_proc_ul_cmpt_entry)(void *cmpt_entry,
struct qdma_ul_cmpt_info *cmpt_info);
/** fill in by libqdma */ /** fill in by libqdma */
/** @name: name of the qdma device */ /** @name: name of the qdma device */
...@@ -952,21 +951,6 @@ struct qdma_q_state { ...@@ -952,21 +951,6 @@ struct qdma_q_state {
int qdma_get_queue_state(unsigned long dev_hndl, unsigned long id, int qdma_get_queue_state(unsigned long dev_hndl, unsigned long id,
struct qdma_q_state *qstate, char *buf, int buflen); struct qdma_q_state *qstate, char *buf, int buflen);
/*****************************************************************************/
/**
* qdma_queue_prog_stm() - Program STM for queue (context, map, etc)
*
* @dev_hndl: dev_hndl returned from qdma_device_open()
* @id: queue index
* @buflen: length of the input buffer
* @buf: message buffer
*
* Return: 0 for success and <0 for error
*
*****************************************************************************/
int qdma_queue_prog_stm(unsigned long dev_hndl, unsigned long id, char *buf,
int buflen);
/*****************************************************************************/ /*****************************************************************************/
/** /**
* qdma_queue_remove() - remove a queue * qdma_queue_remove() - remove a queue
...@@ -1090,7 +1074,7 @@ int qdma_queue_set_err_induction(unsigned long dev_hndl, unsigned long id, ...@@ -1090,7 +1074,7 @@ int qdma_queue_set_err_induction(unsigned long dev_hndl, unsigned long id,
/** maximum request length */ /** maximum request length */
#define QDMA_REQ_OPAQUE_SIZE 72 #define QDMA_REQ_OPAQUE_SIZE 80
/** Max length of the user defined data */ /** Max length of the user defined data */
#define QDMA_UDD_MAXLEN 32 #define QDMA_UDD_MAXLEN 32
......
/*
* Copyright(c) 2019 Xilinx, Inc. All rights reserved.
*/
#ifndef QDMA_ACCESS_ERRORS_H_
#define QDMA_ACCESS_ERRORS_H_
/**
* DOC: QDMA common library error codes definitions
*
* Header file *qdma_access_errors.h* defines error codes for common library
*/
struct err_code_map {
int acc_err_code;
int err_code;
};
#define QDMA_HW_ERR_NOT_DETECTED 1
enum qdma_access_error_codes {
QDMA_SUCCESS = 0,
QDMA_ERR_INV_PARAM,
QDMA_ERR_NO_MEM,
QDMA_ERR_HWACC_BUSY_TIMEOUT,
QDMA_ERR_HWACC_INV_CONFIG_BAR,
QDMA_ERR_HWACC_NO_PEND_LEGCY_INTR,
QDMA_ERR_HWACC_BAR_NOT_FOUND,
QDMA_ERR_HWACC_FEATURE_NOT_SUPPORTED, /* 7 */
QDMA_ERR_RM_RES_EXISTS, /* 8 */
QDMA_ERR_RM_RES_NOT_EXISTS,
QDMA_ERR_RM_DEV_EXISTS,
QDMA_ERR_RM_DEV_NOT_EXISTS,
QDMA_ERR_RM_NO_QUEUES_LEFT,
QDMA_ERR_RM_QMAX_CONF_REJECTED, /* 13 */
QDMA_ERR_MBOX_FMAP_WR_FAILED, /* 14 */
QDMA_ERR_MBOX_NUM_QUEUES,
QDMA_ERR_MBOX_INV_QID,
QDMA_ERR_MBOX_INV_RINGSZ,
QDMA_ERR_MBOX_INV_BUFSZ,
QDMA_ERR_MBOX_INV_CNTR_TH,
QDMA_ERR_MBOX_INV_TMR_TH,
QDMA_ERR_MBOX_INV_MSG,
QDMA_ERR_MBOX_SEND_BUSY,
QDMA_ERR_MOBX_NO_MSG_IN,
QDMA_ERR_MBOX_ALL_ZERO_MSG, /* 24 */
};
#endif /* QDMA_ACCESS_H_ */
/* /*
* Copyright(c) 2019 Xilinx, Inc. All rights reserved. * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
*
* This source code is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*/ */
#ifndef QDMA_ACCESS_EXPORT_H_ #ifndef QDMA_ACCESS_EXPORT_H_
......
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