simde-arch.h · ca1e942d98a418c784b3a9f28db5203e427f18d6 · Libraries / simde · GitLab

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neon riscv64: Enable RVV segment load/store only when we have `__riscv_zvlsseg` flag. (#1285) · ca1e942d
Ruhung authored Feb 27, 2025
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Co-authored-by: Juhung Li <jhlee755@andestech.com>
Co-authored-by: Michael R. Crusoe <1330696+mr-c@users.noreply.github.com>
```
ca1e942d

simde-arch.h 20.6 KB