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Commit 4ab8749d authored by Michael R. Crusoe's avatar Michael R. Crusoe
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sse{,2,3,4.1},avx: more WASM shuffle implementations

parent b49fa29d
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x86/avx.h
View file @ 4ab8749d
......@@ -4637,6 +4637,8 @@ simde_mm_permute_ps (simde__m128 a, const int imm8)
}
#if defined(SIMDE_X86_AVX_NATIVE)
# define simde_mm_permute_ps(a, imm8) _mm_permute_ps(a, imm8)
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
# define simde_mm_permute_ps(a, imm8) simde__m128_from_wasm_v128(wasm_i32x4_shuffle(simde__m128_to_wasm_v128(a), simde__m128_to_wasm_v128(a), ((imm8) & 3), (((imm8) >> 2) & 3 ), (((imm8) >> 4) & 3), (((imm8) >> 6) & 3)))
#endif
#if defined(SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)
#undef _mm_permute_ps
......@@ -4661,6 +4663,8 @@ simde_mm_permute_pd (simde__m128d a, const int imm8)
}
#if defined(SIMDE_X86_AVX_NATIVE)
# define simde_mm_permute_pd(a, imm8) _mm_permute_pd(a, imm8)
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
# define simde_mm_permute_pd(a, imm8) simde__m128d_from_wasm_v128(wasm_i64x2_shuffle(simde__m128d_to_wasm_v128(a), simde__m128d_to_wasm_v128(a), ((imm8) & 1), (((imm8) >> 1) & 1 )))
#endif
#if defined(SIMDE_X86_AVX_ENABLE_NATIVE_ALIASES)
#undef _mm_permute_pd
......
x86/sse.h
View file @ 4ab8749d
......@@ -761,9 +761,7 @@ simde_mm_move_ss (simde__m128 a, simde__m128 b) {
a_ = simde__m128_to_private(a),
b_ = simde__m128_to_private(b);
#if defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 4, 1, 2, 3);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
r_.neon_f32 = vsetq_lane_f32(vgetq_lane_f32(b_.neon_f32, 0), a_.neon_f32, 0);
#elif defined(SIMDE_POWER_ALTIVEC_P6_NATIVE)
static const SIMDE_POWER_ALTIVEC_VECTOR(unsigned int) m = { ~0U, 0U, 0U, 0U };
......@@ -772,6 +770,8 @@ simde_mm_move_ss (simde__m128 a, simde__m128 b) {
r_.wasm_v128 = wasm_i8x16_shuffle(b_.wasm_v128, a_.wasm_v128, 0, 1, 2, 3, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vextrins_w(a_.lsx_i64, b_.lsx_i64, 0);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 4, 1, 2, 3);
#else
r_.f32[0] = b_.f32[0];
r_.f32[1] = a_.f32[1];
......@@ -3238,9 +3238,7 @@ simde_mm_movelh_ps (simde__m128 a, simde__m128 b) {
a_ = simde__m128_to_private(a),
b_ = simde__m128_to_private(b);
#if defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 0, 1, 4, 5);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
#if defined(SIMDE_ARM_NEON_A32V7_NATIVE)
float32x2_t a10 = vget_low_f32(a_.neon_f32);
float32x2_t b10 = vget_low_f32(b_.neon_f32);
r_.neon_f32 = vcombine_f32(a10, b10);
......@@ -3249,6 +3247,8 @@ simde_mm_movelh_ps (simde__m128 a, simde__m128 b) {
vec_mergeh(a_.altivec_i64, b_.altivec_i64));
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vilvl_d(b_.lsx_i64, a_.lsx_i64);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 0, 1, 4, 5);
#else
r_.f32[0] = a_.f32[0];
r_.f32[1] = a_.f32[1];
......@@ -4081,21 +4081,21 @@ simde_mm_shuffle_ps (simde__m128 a, simde__m128 b, const int imm8)
}
#if defined(SIMDE_X86_SSE_NATIVE) && !defined(__PGI)
# define simde_mm_shuffle_ps(a, b, imm8) _mm_shuffle_ps(a, b, imm8)
#elif defined(SIMDE_SHUFFLE_VECTOR_)
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
#define simde_mm_shuffle_ps(a, b, imm8) (__extension__ ({ \
simde__m128_from_private((simde__m128_private) { .f32 = \
SIMDE_SHUFFLE_VECTOR_(32, 16, \
simde__m128_to_private(a).f32, \
simde__m128_to_private(b).f32, \
(((imm8) ) & 3), \
(((imm8) >> 2) & 3), \
(((imm8) >> 4) & 3) + 4, \
(((imm8) >> 6) & 3) + 4) }); }))
simde__m128_from_private((simde__m128_private) { .wasm_v128 = \
wasm_i32x4_shuffle( \
simde__m128_to_private(a).wasm_v128, \
simde__m128_to_private(b).wasm_v128, \
(((imm8) ) & 3), \
(((imm8) >> 2) & 3), \
(((imm8) >> 4) & 3) + 4, \
(((imm8) >> 6) & 3) + 4) }); }))
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_STATEMENT_EXPR_)
#define simde_mm_shuffle_ps(a, b, imm8) \
(__extension__({ \
float32x4_t simde_mm_shuffle_ps_a_ = simde__m128i_to_neon_f32(a); \
float32x4_t simde_mm_shuffle_ps_b_ = simde__m128i_to_neon_f32(b); \
float32x4_t simde_mm_shuffle_ps_a_ = simde__m128_to_neon_f32(a); \
float32x4_t simde_mm_shuffle_ps_b_ = simde__m128_to_neon_f32(b); \
float32x4_t simde_mm_shuffle_ps_r_; \
\
simde_mm_shuffle_ps_r_ = vmovq_n_f32(vgetq_lane_f32(simde_mm_shuffle_ps_a_, (imm8) & (0x3))); \
......@@ -4103,6 +4103,16 @@ simde_mm_shuffle_ps (simde__m128 a, simde__m128 b, const int imm8)
simde_mm_shuffle_ps_r_ = vsetq_lane_f32(vgetq_lane_f32(simde_mm_shuffle_ps_b_, ((imm8) >> 4) & 0x3), simde_mm_shuffle_ps_r_, 2); \
vsetq_lane_f32(vgetq_lane_f32(simde_mm_shuffle_ps_b_, ((imm8) >> 6) & 0x3), simde_mm_shuffle_ps_r_, 3); \
}))
#elif defined(SIMDE_SHUFFLE_VECTOR_)
#define simde_mm_shuffle_ps(a, b, imm8) (__extension__ ({ \
simde__m128_from_private((simde__m128_private) { .f32 = \
SIMDE_SHUFFLE_VECTOR_(32, 16, \
simde__m128_to_private(a).f32, \
simde__m128_to_private(b).f32, \
(((imm8) ) & 3), \
(((imm8) >> 2) & 3), \
(((imm8) >> 4) & 3) + 4, \
(((imm8) >> 6) & 3) + 4) }); }))
#endif
#if defined(SIMDE_X86_SSE_ENABLE_NATIVE_ALIASES)
# define _mm_shuffle_ps(a, b, imm8) simde_mm_shuffle_ps((a), (b), imm8)
......@@ -4675,6 +4685,8 @@ simde_mm_unpackhi_ps (simde__m128 a, simde__m128 b) {
r_.neon_f32 = vcombine_f32(result.val[0], result.val[1]);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vilvh_w(b_.lsx_i64, a_.lsx_i64);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i32x4_shuffle(a_.wasm_v128, b_.wasm_v128, 2, 6, 3, 7);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 2, 6, 3, 7);
#else
......@@ -4708,13 +4720,15 @@ simde_mm_unpacklo_ps (simde__m128 a, simde__m128 b) {
r_.altivec_f32 = vec_mergeh(a_.altivec_f32, b_.altivec_f32);
#elif defined(SIMDE_LOONGARCH_LSX_NATIVE)
r_.lsx_i64 = __lsx_vilvl_w(b_.lsx_i64, a_.lsx_i64);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 0, 4, 1, 5);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i32x4_shuffle(a_.wasm_v128, b_.wasm_v128, 0, 4, 1, 5);
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
float32x2_t a1 = vget_low_f32(a_.neon_f32);
float32x2_t b1 = vget_low_f32(b_.neon_f32);
float32x2x2_t result = vzip_f32(a1, b1);
r_.neon_f32 = vcombine_f32(result.val[0], result.val[1]);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 0, 4, 1, 5);
#else
r_.f32[0] = a_.f32[0];
r_.f32[1] = b_.f32[0];
......
x86/sse2.h
View file @ 4ab8749d
This diff is collapsed.
x86/sse3.h
View file @ 4ab8749d
......@@ -46,6 +46,8 @@ simde_x_mm_deinterleaveeven_epi16 (simde__m128i a, simde__m128i b) {
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
int16x8x2_t t = vuzpq_s16(a_.neon_i16, b_.neon_i16);
r_.neon_i16 = t.val[0];
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i16x8_shuffle(a_.wasm_v128, b_.wasm_v128, 0, 2, 4, 6, 8, 10, 12, 14);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.i16 = SIMDE_SHUFFLE_VECTOR_(16, 16, a_.i16, b_.i16, 0, 2, 4, 6, 8, 10, 12, 14);
#else
......@@ -72,6 +74,8 @@ simde_x_mm_deinterleaveodd_epi16 (simde__m128i a, simde__m128i b) {
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
int16x8x2_t t = vuzpq_s16(a_.neon_i16, b_.neon_i16);
r_.neon_i16 = t.val[1];
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i16x8_shuffle(a_.wasm_v128, b_.wasm_v128, 1, 3, 5, 7, 9, 11, 13, 15);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.i16 = SIMDE_SHUFFLE_VECTOR_(16, 16, a_.i16, b_.i16, 1, 3, 5, 7, 9, 11, 13, 15);
#else
......@@ -98,6 +102,8 @@ simde_x_mm_deinterleaveeven_epi32 (simde__m128i a, simde__m128i b) {
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
int32x4x2_t t = vuzpq_s32(a_.neon_i32, b_.neon_i32);
r_.neon_i32 = t.val[0];
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i32x4_shuffle(a_.wasm_v128, b_.wasm_v128, 0, 2, 4, 6);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.i32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.i32, b_.i32, 0, 2, 4, 6);
#else
......@@ -124,6 +130,8 @@ simde_x_mm_deinterleaveodd_epi32 (simde__m128i a, simde__m128i b) {
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
int32x4x2_t t = vuzpq_s32(a_.neon_i32, b_.neon_i32);
r_.neon_i32 = t.val[1];
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i32x4_shuffle(a_.wasm_v128, b_.wasm_v128, 1, 3, 5, 7);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.i32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.i32, b_.i32, 1, 3, 5, 7);
#else
......@@ -150,6 +158,8 @@ simde_x_mm_deinterleaveeven_ps (simde__m128 a, simde__m128 b) {
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
float32x4x2_t t = vuzpq_f32(a_.neon_f32, b_.neon_f32);
r_.neon_f32 = t.val[0];
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i32x4_shuffle(a_.wasm_v128, b_.wasm_v128, 0, 2, 4, 6);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 0, 2, 4, 6);
#else
......@@ -176,6 +186,8 @@ simde_x_mm_deinterleaveodd_ps (simde__m128 a, simde__m128 b) {
#elif defined(SIMDE_ARM_NEON_A32V7_NATIVE)
float32x4x2_t t = vuzpq_f32(a_.neon_f32, b_.neon_f32);
r_.neon_f32 = t.val[1];
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i32x4_shuffle(a_.wasm_v128, b_.wasm_v128, 1, 3, 5, 7);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f32 = SIMDE_SHUFFLE_VECTOR_(32, 16, a_.f32, b_.f32, 1, 3, 5, 7);
#else
......@@ -199,6 +211,8 @@ simde_x_mm_deinterleaveeven_pd (simde__m128d a, simde__m128d b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
r_.neon_f64 = vuzp1q_f64(a_.neon_f64, b_.neon_f64);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i64x2_shuffle(a_.wasm_v128, b_.wasm_v128, 0, 2);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f64 = SIMDE_SHUFFLE_VECTOR_(64, 16, a_.f64, b_.f64, 0, 2);
#else
......@@ -222,6 +236,8 @@ simde_x_mm_deinterleaveodd_pd (simde__m128d a, simde__m128d b) {
#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
r_.neon_f64 = vuzp2q_f64(a_.neon_f64, b_.neon_f64);
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
r_.wasm_v128 = wasm_i64x2_shuffle(a_.wasm_v128, b_.wasm_v128, 1, 3);
#elif defined(SIMDE_SHUFFLE_VECTOR_)
r_.f64 = SIMDE_SHUFFLE_VECTOR_(64, 16, a_.f64, b_.f64, 1, 3);
#else
......
x86/sse4.1.h
View file @ 4ab8749d
......@@ -705,6 +705,10 @@ simde_mm_cvtepi8_epi64 (simde__m128i a) {
int32x4_t s32x4 = vmovl_s16(vget_low_s16(s16x8)); /* 000x 000x 000B 000A */
int64x2_t s64x2 = vmovl_s32(vget_low_s32(s32x4)); /* 0000 000B 0000 000A */
r_.neon_i64 = s64x2;
#elif defined(SIMDE_WASM_SIMD128_NATIVE)
v128_t extra = wasm_i32x4_extend_low_i16x8(wasm_i16x8_extend_low_i8x16(a_.wasm_v128));
v128_t sign = wasm_i32x4_gt(wasm_i64x2_const(0, 0), extra);
r_.wasm_v128 = wasm_i32x4_shuffle(extra, sign, 0, 4, 1, 5);
#elif (!defined(SIMDE_ARCH_X86) && !defined(SIMDE_ARCH_AMD64)) && defined(SIMDE_SHUFFLE_VECTOR_) && defined(SIMDE_VECTOR_SCALAR) && (SIMDE_ENDIAN_ORDER == SIMDE_ENDIAN_LITTLE)
/* Disabled on x86 due to lack of 64-bit arithmetic shift until
* until AVX-512 (at which point we would be using the native
......
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