NEON: part 1 of implement all intrinsics supported by architecture A64 (#1090)

Add 368 initial implementations and corresponding test cases in 88 families which are listed below:
- `abd`, `abdl_high`, `add`, `addhn_high`, `bsl`, `ceq`, `ceqz`, `cgez`, `cgtz`, `cle`,
- `cltz`, `cmla`, `cmla_rot180`, `cmla_rot270`, `cmla_rot90`, `cnt`, `copy_lane`, `cvt`, `cvt_n`, `cvtm`,
-  `cvtp`, `dot`, `dot_lane`, `dup_n`, `eor`, `fms_n`, `ld1`, `ld3`, `ld4`, `maxnm`,
-  `maxv`, `minnm`, `minv`, `mull`, `mull_high`, `mvn`, `pmin`, `qrdmulh_lane`, `qrshl`, `qrshrn_high_n`,
-  `qrshrun_high_n`, `qshl_n`, `qshlu_n`, `qshrn_high_n`, `qshrn_n`, `qshrun_n`, `qtbl`, `qtbx`, `raddhn`, `raddhn_high`,
-  `rbit`, `reinterpret`, `rev16`, `rev32`, `rev64`, `rnd`, `rndi`, `rndm`, `rndp`, `rshrn_high_n`,
-  `rsubhn`, `rsubhn_high`, `shr_n`, `shrn_n`, `sli_n`, `sri_n`, `st1`, `st1_lane`, `st1_x2`, `st1_x3`,
-  `st1_x4`, `st1q_x2`, `st1q_x3`, `st1q_x4`, `st2_lane`, `st3`, `st3_lane`, `st4`, `st4_lane`, `tbl`,
-  `tbx`, `trn`, `trn1`, `trn2`, `tst`, `uzp`, `uzp1`, `uzp2`

arm/neon.h

@@ -35,9 +35,11 @@
 #include "neon/abal_high.h"
 #include "neon/abd.h"
 #include "neon/abdl.h"
+#include "neon/abdl_high.h"
 #include "neon/abs.h"
 #include "neon/add.h"
 #include "neon/addhn.h"
+#include "neon/addhn_high.h"
 #include "neon/addl.h"
 #include "neon/addlv.h"
 #include "neon/addl_high.h"
@@ -77,8 +79,11 @@
 #include "neon/cnt.h"
 #include "neon/cvt.h"
 #include "neon/cvt_n.h"
+#include "neon/cvtm.h"
 #include "neon/cvtn.h"
+#include "neon/cvtp.h"
 #include "neon/combine.h"
+#include "neon/copy_lane.h"
 #include "neon/create.h"
 #include "neon/div.h"
 #include "neon/dot.h"
@@ -187,7 +192,10 @@
 #include "neon/qrdmulh.h"
 #include "neon/qrdmulh_lane.h"
 #include "neon/qrdmulh_n.h"
+#include "neon/qrshl.h"
+#include "neon/qrshrn_high_n.h"
 #include "neon/qrshrn_n.h"
+#include "neon/qrshrun_high_n.h"
 #include "neon/qrshrun_n.h"
 #include "neon/qmovn.h"
 #include "neon/qmovun.h"
@@ -195,11 +203,15 @@
 #include "neon/qneg.h"
 #include "neon/qsub.h"
 #include "neon/qshl.h"
+#include "neon/qshl_n.h"
 #include "neon/qshlu_n.h"
+#include "neon/qshrn_high_n.h"
 #include "neon/qshrn_n.h"
 #include "neon/qshrun_n.h"
 #include "neon/qtbl.h"
 #include "neon/qtbx.h"
+#include "neon/raddhn.h"
+#include "neon/raddhn_high.h"
 #include "neon/rbit.h"
 #include "neon/recpe.h"
 #include "neon/recps.h"
@@ -215,16 +227,20 @@
 #include "neon/rndp.h"
 #include "neon/rshl.h"
 #include "neon/rshr_n.h"
+#include "neon/rshrn_high_n.h"
 #include "neon/rshrn_n.h"
 #include "neon/rsqrte.h"
 #include "neon/rsqrts.h"
 #include "neon/rsra_n.h"
+#include "neon/rsubhn.h"
+#include "neon/rsubhn_high.h"
 #include "neon/set_lane.h"
 #include "neon/shl.h"
 #include "neon/shl_n.h"
 #include "neon/shll_n.h"
 #include "neon/shr_n.h"
 #include "neon/shrn_n.h"
+#include "neon/sli_n.h"
 #include "neon/sqadd.h"
 #include "neon/sqrt.h"
 #include "neon/sra_n.h"

arm/neon/abd.h

@@ -22,6 +22,7 @@
  *
  * Copyright:
  *   2020      Evan Nemerson <evan@nemerson.com>
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
  */
 
 #if !defined(SIMDE_ARM_NEON_ABD_H)
@@ -37,6 +38,23 @@ HEDLEY_DIAGNOSTIC_PUSH
 SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
 SIMDE_BEGIN_DECLS_
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_float16_t
+simde_vabdh_f16(simde_float16_t a, simde_float16_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vabdh_f16(a, b);
+  #else
+    simde_float32_t a_ = simde_float16_to_float32(a);
+    simde_float32_t b_ = simde_float16_to_float32(b);
+    simde_float32_t r_ = a_ - b_;
+    return r_ < 0 ? simde_float16_from_float32(-r_) : simde_float16_from_float32(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdh_f16
+  #define vabdh_f16(a, b) simde_vabdh_f16((a), (b))
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_float32_t
 simde_vabds_f32(simde_float32_t a, simde_float32_t b) {
@@ -67,6 +85,20 @@ simde_vabdd_f64(simde_float64_t a, simde_float64_t b) {
   #define vabdd_f64(a, b) simde_vabdd_f64((a), (b))
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_float16x4_t
+simde_vabd_f16(simde_float16x4_t a, simde_float16x4_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vabd_f16(a, b);
+  #else
+    return simde_vabs_f16(simde_vsub_f16(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vabd_f16
+  #define vabd_f16(a, b) simde_vabd_f16((a), (b))
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_float32x2_t
 simde_vabd_f32(simde_float32x2_t a, simde_float32x2_t b) {
@@ -220,6 +252,20 @@ simde_vabd_u32(simde_uint32x2_t a, simde_uint32x2_t b) {
   #define vabd_u32(a, b) simde_vabd_u32((a), (b))
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_float16x8_t
+simde_vabdq_f16(simde_float16x8_t a, simde_float16x8_t b) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vabdq_f16(a, b);
+  #else
+    return simde_vabsq_f16(simde_vsubq_f16(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdq_f16
+  #define vabdq_f16(a, b) simde_vabdq_f16((a), (b))
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_float32x4_t
 simde_vabdq_f32(simde_float32x4_t a, simde_float32x4_t b) {

arm/neon/abdl_high.h

+/* SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Copyright:
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
+ */
+
+#if !defined(SIMDE_ARM_NEON_ABDL_HIGH_H)
+#define SIMDE_ARM_NEON_ABDL_HIGH_H
+
+#include "abdl.h"
+
+HEDLEY_DIAGNOSTIC_PUSH
+SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
+SIMDE_BEGIN_DECLS_
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_int16x8_t
+simde_vabdl_high_s8(simde_int8x16_t a, simde_int8x16_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vabdl_high_s8(a, b);
+  #else
+    return simde_vabdl_s8(simde_vget_high_s8(a), simde_vget_high_s8(b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdl_high_s8
+  #define vabdl_high_s8(a, b) simde_vabdl_high_s8((a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_int32x4_t
+simde_vabdl_high_s16(simde_int16x8_t a, simde_int16x8_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vabdl_high_s16(a, b);
+  #else
+    return simde_vabdl_s16(simde_vget_high_s16(a), simde_vget_high_s16(b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdl_high_s16
+  #define vabdl_high_s16(a, b) simde_vabdl_high_s16((a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_int64x2_t
+simde_vabdl_high_s32(simde_int32x4_t a, simde_int32x4_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vabdl_high_s32(a, b);
+  #else
+    return simde_vabdl_s32(simde_vget_high_s32(a), simde_vget_high_s32(b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdl_high_s32
+  #define vabdl_high_s32(a, b) simde_vabdl_high_s32((a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x8_t
+simde_vabdl_high_u8(simde_uint8x16_t a, simde_uint8x16_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vabdl_high_u8(a, b);
+  #else
+    return simde_vabdl_u8(simde_vget_high_u8(a), simde_vget_high_u8(b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdl_high_u8
+  #define vabdl_high_u8(a, b) simde_vabdl_high_u8((a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint32x4_t
+simde_vabdl_high_u16(simde_uint16x8_t a, simde_uint16x8_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vabdl_high_u16(a, b);
+  #else
+    return simde_vabdl_u16(simde_vget_high_u16(a), simde_vget_high_u16(b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdl_high_u16
+  #define vabdl_high_u16(a, b) simde_vabdl_high_u16((a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint64x2_t
+simde_vabdl_high_u32(simde_uint32x4_t a, simde_uint32x4_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vabdl_high_u32(a, b);
+  #else
+    return simde_vabdl_u32(simde_vget_high_u32(a), simde_vget_high_u32(b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vabdl_high_u32
+  #define vabdl_high_u32(a, b) simde_vabdl_high_u32((a), (b))
+#endif
+
+SIMDE_END_DECLS_
+HEDLEY_DIAGNOSTIC_POP
+
+#endif /* !defined(SIMDE_ARM_NEON_ABDL_HIGH_H) */

arm/neon/addhn_high.h

+/* SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Copyright:
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
+ */
+
+#if !defined(SIMDE_ARM_NEON_ADDHN_HIGH_H)
+#define SIMDE_ARM_NEON_ADDHN_HIGH_H
+
+#include "addhn.h"
+#include "combine.h"
+
+HEDLEY_DIAGNOSTIC_PUSH
+SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
+SIMDE_BEGIN_DECLS_
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_int8x16_t
+simde_vaddhn_high_s16(simde_int8x8_t r, simde_int16x8_t a, simde_int16x8_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vaddhn_high_s16(r, a, b);
+  #else
+    return simde_vcombine_s8(r, simde_vaddhn_s16(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vaddhn_high_s16
+  #define vaddhn_high_s16(r, a, b) simde_vaddhn_high_s16((r), (a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_int16x8_t
+simde_vaddhn_high_s32(simde_int16x4_t r, simde_int32x4_t a, simde_int32x4_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vaddhn_high_s32(r, a, b);
+  #else
+    return simde_vcombine_s16(r, simde_vaddhn_s32(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vaddhn_high_s32
+  #define vaddhn_high_s32(r, a, b) simde_vaddhn_high_s32((r), (a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_int32x4_t
+simde_vaddhn_high_s64(simde_int32x2_t r, simde_int64x2_t a, simde_int64x2_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vaddhn_high_s64(r, a, b);
+  #else
+    return simde_vcombine_s32(r, simde_vaddhn_s64(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vaddhn_high_s64
+  #define vaddhn_high_s64(r, a, b) simde_vaddhn_high_s64((r), (a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint8x16_t
+simde_vaddhn_high_u16(simde_uint8x8_t r, simde_uint16x8_t a, simde_uint16x8_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vaddhn_high_u16(r, a, b);
+  #else
+    return simde_vcombine_u8(r, simde_vaddhn_u16(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vaddhn_high_u16
+  #define vaddhn_high_u16(r, a, b) simde_vaddhn_high_u16((r), (a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x8_t
+simde_vaddhn_high_u32(simde_uint16x4_t r, simde_uint32x4_t a, simde_uint32x4_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vaddhn_high_u32(r, a, b);
+  #else
+    return simde_vcombine_u16(r, simde_vaddhn_u32(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vaddhn_high_u32
+  #define vaddhn_high_u32(r, a, b) simde_vaddhn_high_u32((r), (a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint32x4_t
+simde_vaddhn_high_u64(simde_uint32x2_t r, simde_uint64x2_t a, simde_uint64x2_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+    return vaddhn_high_u64(r, a, b);
+  #else
+    return simde_vcombine_u32(r, simde_vaddhn_u64(a, b));
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vaddhn_high_u64
+  #define vaddhn_high_u64(r, a, b) simde_vaddhn_high_u64((r), (a), (b))
+#endif
+
+SIMDE_END_DECLS_
+HEDLEY_DIAGNOSTIC_POP
+
+#endif /* !defined(SIMDE_ARM_NEON_ADDHN_HIGH_H) */

arm/neon/cgez.h

@@ -23,6 +23,7 @@
  * Copyright:
  *   2020      Evan Nemerson <evan@nemerson.com>
  *   2020      Christopher Moore <moore@free.fr>
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
  */
 
 #if !defined(SIMDE_ARM_NEON_CGEZ_H)
@@ -78,6 +79,42 @@ simde_vcgezs_f32(simde_float32_t a) {
   #define vcgezs_f32(a) simde_vcgezs_f32(a)
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+uint16_t
+simde_vcgezh_f16(simde_float16_t a) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return HEDLEY_STATIC_CAST(uint16_t, vcgezh_f16(a));
+  #else
+    return (simde_float16_to_float32(a) >= SIMDE_FLOAT32_C(0.0)) ? UINT16_MAX : 0;
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vcgezh_f16
+  #define vcgezh_f16(a) simde_vcgezh_f16(a)
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x8_t
+simde_vcgezq_f16(simde_float16x8_t a) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcgezq_f16(a);
+  #else
+    simde_float16x8_private a_ = simde_float16x8_to_private(a);
+    simde_uint16x8_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcgezh_f16(a_.values[i]);
+    }
+
+    return simde_uint16x8_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vcgezq_f16
+  #define vcgezq_f16(a) simde_vcgezq_f16(a)
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint32x4_t
 simde_vcgezq_f32(simde_float32x4_t a) {
@@ -246,6 +283,28 @@ simde_vcgezq_s64(simde_int64x2_t a) {
   #define vcgezq_s64(a) simde_vcgezq_s64(a)
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x4_t
+simde_vcgez_f16(simde_float16x4_t a) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcgez_f16(a);
+  #else
+    simde_float16x4_private a_ = simde_float16x4_to_private(a);
+    simde_uint16x4_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcgezh_f16(a_.values[i]);
+    }
+
+    return simde_uint16x4_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vcgez_f16
+  #define vcgez_f16(a) simde_vcgez_f16(a)
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint32x2_t
 simde_vcgez_f32(simde_float32x2_t a) {

arm/neon/cgtz.h

@@ -23,6 +23,7 @@
  * Copyright:
  *   2020      Evan Nemerson <evan@nemerson.com>
  *   2020      Christopher Moore <moore@free.fr>
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
  */
 
 #if !defined(SIMDE_ARM_NEON_CGTZ_H)
@@ -66,6 +67,42 @@ simde_vcgtzd_f64(simde_float64_t a) {
   #define vcgtzd_f64(a) simde_vcgtzd_f64(a)
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+uint16_t
+simde_vcgtzh_f16(simde_float16_t a) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return HEDLEY_STATIC_CAST(uint16_t, vcgtzh_f16(a));
+  #else
+    return (simde_float16_to_float32(a) > SIMDE_FLOAT32_C(0.0)) ? UINT16_MAX : 0;
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vcgtzh_f16
+  #define vcgtzh_f16(a) simde_vcgtzh_f16(a)
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x8_t
+simde_vcgtzq_f16(simde_float16x8_t a) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcgtzq_f16(a);
+  #else
+    simde_float16x8_private a_ = simde_float16x8_to_private(a);
+    simde_uint16x8_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcgtzh_f16(a_.values[i]);
+    }
+
+    return simde_uint16x8_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vcgtzq_f16
+  #define vcgtzq_f16(a) simde_vcgtzq_f16(a)
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 uint32_t
 simde_vcgtzs_f32(simde_float32_t a) {
@@ -248,6 +285,28 @@ simde_vcgtzq_s64(simde_int64x2_t a) {
   #define vcgtzq_s64(a) simde_vcgtzq_s64(a)
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x4_t
+simde_vcgtz_f16(simde_float16x4_t a) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcgtz_f16(a);
+  #else
+    simde_float16x4_private a_ = simde_float16x4_to_private(a);
+    simde_uint16x4_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcgtzh_f16(a_.values[i]);
+    }
+
+    return simde_uint16x4_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vcgtz_f16
+  #define vcgtz_f16(a) simde_vcgtz_f16(a)
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint32x2_t
 simde_vcgtz_f32(simde_float32x2_t a) {

arm/neon/cle.h

@@ -23,6 +23,7 @@
  * Copyright:
  *   2020      Evan Nemerson <evan@nemerson.com>
  *   2020      Christopher Moore <moore@free.fr>
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
  */
 
 #if !defined(SIMDE_ARM_NEON_CLE_H)
@@ -90,6 +91,44 @@ simde_vcles_f32(simde_float32_t a, simde_float32_t b) {
   #define vcles_f32(a, b) simde_vcles_f32((a), (b))
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+uint16_t
+simde_vcleh_f16(simde_float16_t a, simde_float16_t b) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return HEDLEY_STATIC_CAST(uint16_t, vcleh_f16(a, b));
+  #else
+    return (simde_float16_to_float32(a) <= simde_float16_to_float32(b)) ? UINT16_MAX : 0;
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vcleh_f16
+  #define vcleh_f16(a, b) simde_vcleh_f16((a), (b))
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x8_t
+simde_vcleq_f16(simde_float16x8_t a, simde_float16x8_t b) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcleq_f16(a, b);
+  #else
+    simde_float16x8_private
+      a_ = simde_float16x8_to_private(a),
+      b_ = simde_float16x8_to_private(b);
+    simde_uint16x8_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcleh_f16(a_.values[i], b_.values[i]);
+    }
+
+    return simde_uint16x8_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vcleq_f16
+  #define vcleq_f16(a, b) simde_vcleq_f16((a), (b))
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint32x4_t
 simde_vcleq_f32(simde_float32x4_t a, simde_float32x4_t b) {
@@ -475,6 +514,30 @@ simde_vcleq_u64(simde_uint64x2_t a, simde_uint64x2_t b) {
   #define vcleq_u64(a, b) simde_vcleq_u64((a), (b))
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x4_t
+simde_vcle_f16(simde_float16x4_t a, simde_float16x4_t b) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcle_f16(a, b);
+  #else
+    simde_float16x4_private
+      a_ = simde_float16x4_to_private(a),
+      b_ = simde_float16x4_to_private(b);
+    simde_uint16x4_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcleh_f16(a_.values[i], b_.values[i]);
+    }
+
+    return simde_uint16x4_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vcle_f16
+  #define vcle_f16(a, b) simde_vcle_f16((a), (b))
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint32x2_t
 simde_vcle_f32(simde_float32x2_t a, simde_float32x2_t b) {

arm/neon/cltz.h

@@ -22,6 +22,7 @@
  *
  * Copyright:
  *   2020      Evan Nemerson <evan@nemerson.com>
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
  */
 
 /* TODO: float fallbacks should use vclt(a, vdup_n(0.0)) */
@@ -81,6 +82,42 @@ simde_vcltzs_f32(simde_float32_t a) {
   #define vcltzs_f32(a) simde_vcltzs_f32(a)
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+uint16_t
+simde_vcltzh_f16(simde_float16_t a) {
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return HEDLEY_STATIC_CAST(uint16_t, vcltzh_f16(a));
+  #else
+    return (simde_float16_to_float32(a) < SIMDE_FLOAT32_C(0.0)) ? UINT16_MAX : 0;
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vcltzh_f16
+  #define vcltzh_f16(a) simde_vcltzh_f16(a)
+#endif
+
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x4_t
+simde_vcltz_f16(simde_float16x4_t a) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcltz_f16(a);
+  #else
+    simde_float16x4_private a_ = simde_float16x4_to_private(a);
+    simde_uint16x4_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcltzh_f16(a_.values[i]);
+    }
+
+    return simde_uint16x4_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
+  #undef vcltz_f16
+  #define vcltz_f16(a) simde_vcltz_f16(a)
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint32x2_t
 simde_vcltz_f32(simde_float32x2_t a) {
@@ -201,6 +238,28 @@ simde_vcltz_s64(simde_int64x1_t a) {
   #define vcltz_s64(a) simde_vcltz_s64(a)
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_uint16x8_t
+simde_vcltzq_f16(simde_float16x8_t a) {
+  #if defined(SIMDE_ARM_NEON_A32V8_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vcltzq_f16(a);
+  #else
+    simde_float16x8_private a_ = simde_float16x8_to_private(a);
+    simde_uint16x8_private r_;
+
+    SIMDE_VECTORIZE
+    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      r_.values[i] = simde_vcltzh_f16(a_.values[i]);
+    }
+
+    return simde_uint16x8_from_private(r_);
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V8_ENABLE_NATIVE_ALIASES)
+  #undef vcltzq_f16
+  #define vcltzq_f16(a) simde_vcltzq_f16(a)
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint32x4_t
 simde_vcltzq_f32(simde_float32x4_t a) {

arm/neon/fms_n.h

@@ -66,13 +66,13 @@ simde_vfmsq_n_f16(simde_float16x8_t a, simde_float16x8_t b, simde_float16_t c) {
 SIMDE_FUNCTION_ATTRIBUTES
 simde_float32x2_t
 simde_vfms_n_f32(simde_float32x2_t a, simde_float32x2_t b, simde_float32_t c) {
-  #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399)
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399)
     return vfms_n_f32(a, b, c);
   #else
     return simde_vfms_f32(a, b, simde_vdup_n_f32(c));
   #endif
 }
-#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
   #undef vfms_n_f32
   #define vfms_n_f32(a, b, c) simde_vfms_n_f32(a, b, c)
 #endif
@@ -94,13 +94,13 @@ simde_vfms_n_f64(simde_float64x1_t a, simde_float64x1_t b, simde_float64_t c) {
 SIMDE_FUNCTION_ATTRIBUTES
 simde_float32x4_t
 simde_vfmsq_n_f32(simde_float32x4_t a, simde_float32x4_t b, simde_float32_t c) {
-  #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399)
+  #if defined(SIMDE_ARM_NEON_A64V8_NATIVE) && defined(SIMDE_ARCH_ARM_FMA) && (!defined(__clang__) || SIMDE_DETECT_CLANG_VERSION_CHECK(7,0,0)) && !defined(SIMDE_BUG_GCC_95399)
     return vfmsq_n_f32(a, b, c);
   #else
     return simde_vfmsq_f32(a, b, simde_vdupq_n_f32(c));
   #endif
 }
-#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
   #undef vfmsq_n_f32
   #define vfmsq_n_f32(a, b, c) simde_vfmsq_n_f32(a, b, c)
 #endif

arm/neon/ld3.h

@@ -349,6 +349,34 @@ simde_vld3_u64(uint64_t const *ptr) {
   #define vld3_u64(a) simde_vld3_u64((a))
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_float16x8x3_t
+simde_vld3q_f16(simde_float16 const *ptr) {
+  #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vld3q_f16(ptr);
+  #else
+    simde_float16x8_private r_[3];
+
+    for (size_t i = 0; i < (sizeof(r_) / sizeof(r_[0])); i++) {
+      for (size_t j = 0 ; j < (sizeof(r_[0].values) / sizeof(r_[0].values[0])) ; j++) {
+        r_[i].values[j] = ptr[i + (j * (sizeof(r_) / sizeof(r_[0])))];
+      }
+    }
+
+    simde_float16x8x3_t r = { {
+      simde_float16x8_from_private(r_[0]),
+      simde_float16x8_from_private(r_[1]),
+      simde_float16x8_from_private(r_[2])
+    } };
+
+    return r;
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
+  #undef vld3q_f16
+  #define vld3q_f16(a) simde_vld3q_f16((a))
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_float32x4x3_t
 simde_vld3q_f32(simde_float32 const *ptr) {

arm/neon/ld4.h

@@ -260,6 +260,26 @@ simde_vld4_u64(uint64_t const ptr[HEDLEY_ARRAY_PARAM(4)]) {
   #define vld4_u64(a) simde_vld4_u64((a))
 #endif
 
+SIMDE_FUNCTION_ATTRIBUTES
+simde_float16x8x4_t
+simde_vld4q_f16(simde_float16 const ptr[HEDLEY_ARRAY_PARAM(32)]) {
+  #if defined(SIMDE_ARM_NEON_A32V7_NATIVE) && defined(SIMDE_ARM_NEON_FP16)
+    return vld4q_f16(ptr);
+  #else
+    simde_float16x8_private a_[4];
+    for (size_t i = 0; i < (sizeof(simde_float16x8_t) / sizeof(*ptr)) * 4 ; i++) {
+      a_[i % 4].values[i / 4] = ptr[i];
+    }
+    simde_float16x8x4_t s_ = { { simde_float16x8_from_private(a_[0]), simde_float16x8_from_private(a_[1]),
+                                 simde_float16x8_from_private(a_[2]), simde_float16x8_from_private(a_[3]) } };
+    return s_;
+  #endif
+}
+#if defined(SIMDE_ARM_NEON_A32V7_ENABLE_NATIVE_ALIASES)
+  #undef vld4q_f16
+  #define vld4q_f16(a) simde_vld4q_f16((a))
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_float32x4x4_t
 simde_vld4q_f32(simde_float32 const ptr[HEDLEY_ARRAY_PARAM(16)]) {

arm/neon/qshrn_high_n.h

+/* SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Copyright:
+ *   2023      Yi-Yen Chung <eric681@andestech.com> (Copyright owned by Andes Technology)
+ */
+
+#if !defined(SIMDE_ARM_NEON_QSHRN_HIGH_N_H)
+#define SIMDE_ARM_NEON_QSHRN_HIGH_N_H
+
+#include "types.h"
+#include "shr_n.h"
+#include "qmovn.h"
+
+HEDLEY_DIAGNOSTIC_PUSH
+SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
+SIMDE_BEGIN_DECLS_
+
+#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+  #define simde_vqshrn_high_n_s16(r, a, n) vqshrn_high_n_s16((r), (a), (n))
+#else
+  #define simde_vqshrn_high_n_s16(r, a, n) simde_vcombine_s8(r, simde_vqmovn_s16(simde_vshrq_n_s16(a, n)))
+#endif
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vqshrn_high_n_s16
+  #define vqshrn_high_n_s16(r, a, n) simde_vqshrn_high_n_s16((r), (a), (n))
+#endif
+
+#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+  #define simde_vqshrn_high_n_s32(r, a, n) vqshrn_high_n_s32((r), (a), (n))
+#else
+  #define simde_vqshrn_high_n_s32(r, a, n) simde_vcombine_s16(r, simde_vqmovn_s32(simde_vshrq_n_s32(a, n)))
+#endif
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vqshrn_high_n_s32
+  #define vqshrn_high_n_s32(r, a, n) simde_vqshrn_high_n_s32((r), (a), (n))
+#endif
+
+#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+  #define simde_vqshrn_high_n_s64(r, a, n) vqshrn_high_n_s64((r), (a), (n))
+#else
+  #define simde_vqshrn_high_n_s64(r, a, n) simde_vcombine_s32(r, simde_vqmovn_s64(simde_vshrq_n_s64(a, n)))
+#endif
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vqshrn_high_n_s64
+  #define vqshrn_high_n_s64(r, a, n) simde_vqshrn_high_n_s64((r), (a), (n))
+#endif
+
+#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+  #define simde_vqshrn_high_n_u16(r, a, n) vqshrn_high_n_u16((r), (a), (n))
+#else
+  #define simde_vqshrn_high_n_u16(r, a, n) simde_vcombine_u8(r, simde_vqmovn_u16(simde_vshrq_n_u16(a, n)))
+#endif
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vqshrn_high_n_u16
+  #define vqshrn_high_n_u16(r, a, n) simde_vqshrn_high_n_u16((r), (a), (n))
+#endif
+
+#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+  #define simde_vqshrn_high_n_u32(r, a, n) vqshrn_high_n_u32((r), (a), (n))
+#else
+  #define simde_vqshrn_high_n_u32(r, a, n) simde_vcombine_u16(r, simde_vqmovn_u32(simde_vshrq_n_u32(a, n)))
+#endif
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vqshrn_high_n_u32
+  #define vqshrn_high_n_u32(r, a, n) simde_vqshrn_high_n_u32((r), (a), (n))
+#endif
+
+#if defined(SIMDE_ARM_NEON_A64V8_NATIVE)
+  #define simde_vqshrn_high_n_u64(r, a, n) vqshrn_high_n_u64((r), (a), (n))
+#else
+  #define simde_vqshrn_high_n_u64(r, a, n) simde_vcombine_u32(r, simde_vqmovn_u64(simde_vshrq_n_u64(a, n)))
+#endif
+#if defined(SIMDE_ARM_NEON_A64V8_ENABLE_NATIVE_ALIASES)
+  #undef vqshrn_high_n_u64
+  #define vqshrn_high_n_u64(r, a, n) simde_vqshrn_high_n_u64((r), (a), (n))
+#endif
+
+SIMDE_END_DECLS_
+HEDLEY_DIAGNOSTIC_POP
+
+#endif /* !defined(SIMDE_ARM_NEON_QSHRN_HIGH_N_H) */