neon riscv64: Enable RVV segment load/store only when we have `__riscv_zvlsseg` flag. (#1285)

Co-authored-by: Juhung Li <jhlee755@andestech.com>
Co-authored-by: Michael R. Crusoe <1330696+mr-c@users.noreply.github.com>

simde-arch.h

@@ -550,6 +550,9 @@
 #if defined(__riscv_zvfhmin)
 #  define SIMDE_ARCH_RISCV_ZVFHMIN 1
 #endif
+#if defined(__riscv_zvlsseg) || defined(__riscv_v)
+#  define SIMDE_ARCH_RISCV_ZVLSSEG 1
+#endif
 
 /* SPARC
    <https://en.wikipedia.org/wiki/SPARC> */