1. 10 Sep, 2024 2 commits
  2. 20 Aug, 2024 4 commits
  3. 12 Aug, 2024 1 commit
  4. 20 Jul, 2024 1 commit
  5. 14 Jul, 2024 1 commit
  6. 02 Jul, 2024 1 commit
  7. 21 Jun, 2024 2 commits
    • Chi-Wei Chu's avatar
      arm/neon riscv64: additional RVV implementations - part 2. (#1189) · 249b9dc0
      Chi-Wei Chu authored
      Contains RVV implementations for the following Neon instructions: 
      
      `abal`, `abdl_high`, `addw`, `addw_high`, `bcax`, `bic`, `cadd_rot270`, `cadd_rot90`, `cmla_lane`, `cmla_rot180_lane` , `cmla_rot270_lane`, `cmla_rot90_lane`, `combine`, `cvt`, `dot`, `dot_lane`, `dup_n`, `eor`, `ext`, `maxnmv`, `minnmv` , `movl` , `movn` , `qdmull` , `qshlu_n`,  `rnda`,  `rsubhn` , `shl`, `shl_n`, `shll_n`, `shr_n`, `shrn_n`, `sqadd`, `sqrt` 
      249b9dc0
    • Ruhung's avatar
      arm/neon riscv64: additional RVV implementations - part1 (#1188) · 408d06a3
      Ruhung authored
      Contains RVV implementations for the following Neon instructions.
      
      `abs`, `addl`, `addl_high`, `addlv`, `addv`, `cge`, `cgt`, `cle`, `clez`, `clt`, `cnt`, `fma`, `fms`, `fms_n`, `get_high`, `get_low`, `hsub`, `mla`, `mla_n`, `mlal`, `mlal_high`, `mlal_high_n`, `mlal_n`, `mls`, `mls_n`, `mlsl`, `mlsl_high`, `mlsl_high_n`, `mlsl_n`, `qsub`, `qtbl`, `qtbx`, `rbit`, `recpe`, `rev16`, `rev32`, `rev64`, `subl`, `subl_high`, `subw`, `subw_high`, `tbl`, `tbx`
      408d06a3
  8. 23 May, 2024 3 commits
  9. 22 May, 2024 1 commit
  10. 17 May, 2024 1 commit
  11. 10 May, 2024 1 commit
  12. 02 May, 2024 1 commit
  13. 30 Apr, 2024 2 commits
  14. 25 Apr, 2024 2 commits
  15. 21 Apr, 2024 1 commit
  16. 20 Apr, 2024 1 commit
    • Zhijin Zeng's avatar
      arm: fix some neon2rvv intrinsic function error · 737e3b33
      Zhijin Zeng authored
      1. For vqdmlal_s16/s32: the doubling result maybe overflow,
      so need to use vqaddq_s16/32 to saturate it. As the same with
      vqdmlsl_s16/32.
      
      2. The vrdmulh family function need to use vqadd saturating
      function to avoid the doubling result overflow.
      
      3. The result of vrshl family function need to keep the sign
      bit of the origin data. If a > 0 && b < 0, the result of
      (a + (1 << (-b - 1))) maybe overflow into a negative value.
      And in gcc/clang, >> means the arithmetic shift left, so it
      will get the incorrect sign bit whithout unsigned extend value.
      Signed-off-by: default avatarZhijin Zeng <zhijin.zeng@spacemit.com>
      737e3b33
  17. 12 Apr, 2024 1 commit
  18. 03 Apr, 2024 4 commits
  19. 01 Apr, 2024 1 commit
  20. 25 Mar, 2024 1 commit
  21. 23 Mar, 2024 1 commit
  22. 22 Mar, 2024 1 commit
  23. 20 Mar, 2024 6 commits