Commit 6ed05c53 authored by Robert Schmidt's avatar Robert Schmidt

Merge remote-tracking branch 'origin/period_based_phytest_bitmap' into integration_2025_w06 (!3242)

Period based phytest bitmap

phy-test slot bitmap tdd period based to minimize the chance to need it
larger than 64 slots
parents e3c56a2b bd179fd5
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
<testCase id="090101"> <testCase id="090101">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB USRP</desc> <desc>Initialize gNB USRP</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.106prb.usrpn300.phytest-dora.conf --phy-test -q -U 787200 -T 106 -t 23 -D 130175 -m 28 -M 106 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.106prb.usrpn300.phytest-dora.conf --phy-test -q -U 768 -T 106 -t 23 -D 127 -m 28 -M 106 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
<rt_stats_cfg>datalog_rt_stats.default.yaml</rt_stats_cfg> <rt_stats_cfg>datalog_rt_stats.default.yaml</rt_stats_cfg>
<air_interface>NR</air_interface> <air_interface>NR</air_interface>
<USRP_IPAddress>192.168.20.2</USRP_IPAddress> <USRP_IPAddress>192.168.20.2</USRP_IPAddress>
......
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
<testCase id="390101"> <testCase id="390101">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB USRP</desc> <desc>Initialize gNB USRP</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.273prb.usrpn300.phytest-dora.conf --phy-test -q -U 787200 -T 273 -t 23 -D 130175 -m 23 -M 273 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.273prb.usrpn300.phytest-dora.conf --phy-test -q -U 768 -T 273 -t 23 -D 127 -m 23 -M 273 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
<rt_stats_cfg>datalog_rt_stats.100.2x2.yaml</rt_stats_cfg> <rt_stats_cfg>datalog_rt_stats.100.2x2.yaml</rt_stats_cfg>
<air_interface>NR</air_interface> <air_interface>NR</air_interface>
<USRP_IPAddress>192.168.20.2</USRP_IPAddress> <USRP_IPAddress>192.168.20.2</USRP_IPAddress>
......
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
<testCase id="190101"> <testCase id="190101">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB USRP</desc> <desc>Initialize gNB USRP</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test -q -U 787200 -T 162 -t 23 -D 130175 -m 23 -M 162 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test -q -U 768 -T 162 -t 23 -D 127 -m 23 -M 162 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
<rt_stats_cfg>datalog_rt_stats.1x1.60.yaml</rt_stats_cfg> <rt_stats_cfg>datalog_rt_stats.1x1.60.yaml</rt_stats_cfg>
<air_interface>NR</air_interface> <air_interface>NR</air_interface>
<USRP_IPAddress>192.168.20.2</USRP_IPAddress> <USRP_IPAddress>192.168.20.2</USRP_IPAddress>
......
...@@ -45,7 +45,7 @@ ...@@ -45,7 +45,7 @@
<testCase id="290101"> <testCase id="290101">
<class>Initialize_eNB</class> <class>Initialize_eNB</class>
<desc>Initialize gNB USRP</desc> <desc>Initialize gNB USRP</desc>
<Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test --gNBs.[0].pdsch_AntennaPorts_XP 2 --RUs.[0].nb_tx 2 --RUs.[0].nb_rx 2 -q -U 787200 -T 162 -t 23 -D 130175 -m 23 -M 162 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args> <Initialize_eNB_args>-O ci-scripts/conf_files/gnb.band78.162prb.usrpn300.phytest-dora.conf --phy-test --gNBs.[0].pdsch_AntennaPorts_XP 2 --RUs.[0].nb_tx 2 --RUs.[0].nb_rx 2 -q -U 768 -T 162 -t 23 -D 127 -m 23 -M 162 -l 2 --usrp-tx-thread-config 1 --log_config.global_log_options level,nocolor,time</Initialize_eNB_args>
<rt_stats_cfg>datalog_rt_stats.60.2x2.yaml</rt_stats_cfg> <rt_stats_cfg>datalog_rt_stats.60.2x2.yaml</rt_stats_cfg>
<air_interface>NR</air_interface> <air_interface>NR</air_interface>
<USRP_IPAddress>192.168.20.2</USRP_IPAddress> <USRP_IPAddress>192.168.20.2</USRP_IPAddress>
......
...@@ -64,8 +64,8 @@ ...@@ -64,8 +64,8 @@
#define CONFIG_HLP_DLBW_PHYTEST "Set the number of PRBs used for DLSCH in PHYTEST mode\n" #define CONFIG_HLP_DLBW_PHYTEST "Set the number of PRBs used for DLSCH in PHYTEST mode\n"
#define CONFIG_HLP_ULBW_PHYTEST "Set the number of PRBs used for ULSCH in PHYTEST mode\n" #define CONFIG_HLP_ULBW_PHYTEST "Set the number of PRBs used for ULSCH in PHYTEST mode\n"
#define CONFIG_HLP_PRB_SA "Set the number of PRBs for SA\n" #define CONFIG_HLP_PRB_SA "Set the number of PRBs for SA\n"
#define CONFIG_HLP_DLBM_PHYTEST "Bitmap for DLSCH slots (slot 0 starts at LSB)\n" #define CONFIG_HLP_DLBM_PHYTEST "Bitmap for DLSCH slots in period (slot 0 starts at LSB)\n"
#define CONFIG_HLP_ULBM_PHYTEST "Bitmap for ULSCH slots (slot 0 starts at LSB)\n" #define CONFIG_HLP_ULBM_PHYTEST "Bitmap for ULSCH slots in period (slot 0 starts at LSB)\n"
#define CONFIG_HLP_SSC "Set the start subcarrier \n" #define CONFIG_HLP_SSC "Set the start subcarrier \n"
#define CONFIG_HLP_TDD "Set hardware to TDD mode (default: FDD). Used only with -U (otherwise set in config file).\n" #define CONFIG_HLP_TDD "Set hardware to TDD mode (default: FDD). Used only with -U (otherwise set in config file).\n"
#define CONFIG_HLP_UE "Set the lte softmodem as a UE\n" #define CONFIG_HLP_UE "Set the lte softmodem as a UE\n"
......
...@@ -41,27 +41,29 @@ ...@@ -41,27 +41,29 @@
// #define ENABLE_MAC_PAYLOAD_DEBUG 1 // #define ENABLE_MAC_PAYLOAD_DEBUG 1
/* This function checks whether the given Dl/UL slot is set /* This function checks whether the given Dl/UL slot is set
in the input bitmap, which is a mask indicating in which in the input bitmap (per period), which is a mask indicating in which
slot to transmit (among those available in the TDD configuration) */ slot to transmit (among those available in the TDD configuration) */
static bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot) static bool is_xlsch_in_slot(uint64_t bitmap, sub_frame_t slot)
{ {
return (bitmap >> (slot % 64)) & 0x01; AssertFatal(slot < 64, "Unable to handle periods with length larger than 64 slots in phy-test mode\n");
return (bitmap >> slot) & 0x01;
} }
uint32_t target_dl_mcs = 9; uint32_t target_dl_mcs = 9;
uint32_t target_dl_Nl = 1; uint32_t target_dl_Nl = 1;
uint32_t target_dl_bw = 50; uint32_t target_dl_bw = 50;
uint64_t dlsch_slot_bitmap = (1<<1); uint64_t dlsch_slot_bitmap = (1<<1);
/* schedules whole bandwidth for first user, all the time */ /* schedules whole bandwidth for first user, all the time */
void nr_preprocessor_phytest(module_id_t module_id, void nr_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot)
frame_t frame,
sub_frame_t slot)
{ {
gNB_MAC_INST *mac = RC.nrmac[module_id];
/* already mutex protected: held in gNB_dlsch_ulsch_scheduler() */ /* already mutex protected: held in gNB_dlsch_ulsch_scheduler() */
if (!is_xlsch_in_slot(dlsch_slot_bitmap, slot)) int slot_period = slot % mac->frame_structure.numb_slots_period;
if (!is_xlsch_in_slot(dlsch_slot_bitmap, slot_period))
return; return;
NR_UE_info_t *UE = RC.nrmac[module_id]->UE_info.list[0]; NR_UE_info_t *UE = mac->UE_info.list[0];
NR_ServingCellConfigCommon_t *scc = RC.nrmac[module_id]->common_channels[0].ServingCellConfigCommon; NR_ServingCellConfigCommon_t *scc = mac->common_channels[0].ServingCellConfigCommon;
NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl; NR_UE_sched_ctrl_t *sched_ctrl = &UE->UE_sched_ctrl;
NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP; NR_UE_DL_BWP_t *dl_bwp = &UE->current_DL_BWP;
const int CC_id = 0; const int CC_id = 0;
...@@ -72,7 +74,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -72,7 +74,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
return; return;
} }
const int tda = get_dl_tda(RC.nrmac[module_id], slot); const int tda = get_dl_tda(mac, slot);
NR_tda_info_t tda_info = get_dl_tda_info(dl_bwp, NR_tda_info_t tda_info = get_dl_tda_info(dl_bwp,
sched_ctrl->search_space->searchSpaceType->present, sched_ctrl->search_space->searchSpaceType->present,
tda, tda,
...@@ -98,7 +100,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -98,7 +100,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
int rbSize = 0; int rbSize = 0;
if (target_dl_bw>bwpSize) if (target_dl_bw>bwpSize)
target_dl_bw = bwpSize; target_dl_bw = bwpSize;
uint16_t *vrb_map = RC.nrmac[module_id]->common_channels[CC_id].vrb_map[beam]; uint16_t *vrb_map = mac->common_channels[CC_id].vrb_map[beam];
/* loop ensures that we allocate exactly target_dl_bw, or return */ /* loop ensures that we allocate exactly target_dl_bw, or return */
while (true) { while (true) {
/* advance to first free RB */ /* advance to first free RB */
...@@ -139,7 +141,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -139,7 +141,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
0); 0);
sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer; sched_ctrl->num_total_bytes += sched_ctrl->rlc_status[lcid].bytes_in_buffer;
int CCEIndex = get_cce_index(RC.nrmac[module_id], int CCEIndex = get_cce_index(mac,
CC_id, slot, UE->rnti, CC_id, slot, UE->rnti,
&sched_ctrl->aggregation_level, &sched_ctrl->aggregation_level,
beam, beam,
...@@ -147,10 +149,7 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -147,10 +149,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
sched_ctrl->coreset, sched_ctrl->coreset,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
false); false);
AssertFatal(CCEIndex >= 0, AssertFatal(CCEIndex >= 0, "Could not find CCE for UE %04x\n", UE->rnti);
"%s(): could not find CCE for UE %04x\n",
__func__,
UE->rnti);
NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch; NR_sched_pdsch_t *sched_pdsch = &sched_ctrl->sched_pdsch;
if (sched_pdsch->dl_harq_pid == -1) if (sched_pdsch->dl_harq_pid == -1)
...@@ -159,20 +158,16 @@ void nr_preprocessor_phytest(module_id_t module_id, ...@@ -159,20 +158,16 @@ void nr_preprocessor_phytest(module_id_t module_id,
int alloc = -1; int alloc = -1;
if (!get_FeedbackDisabled(UE->sc_info.downlinkHARQ_FeedbackDisabled_r17, sched_pdsch->dl_harq_pid)) { if (!get_FeedbackDisabled(UE->sc_info.downlinkHARQ_FeedbackDisabled_r17, sched_pdsch->dl_harq_pid)) {
int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, UE->current_UL_BWP.pucch_Config, CCEIndex); int r_pucch = nr_get_pucch_resource(sched_ctrl->coreset, UE->current_UL_BWP.pucch_Config, CCEIndex);
alloc = nr_acknack_scheduling(RC.nrmac[module_id], UE, frame, slot, 0, r_pucch, 0); alloc = nr_acknack_scheduling(mac, UE, frame, slot, 0, r_pucch, 0);
if (alloc < 0) { if (alloc < 0) {
LOG_D(MAC, LOG_D(NR_MAC, "Could not find PUCCH for UE %04x@%d.%d\n", rnti, frame, slot);
"Could not find PUCCH for UE %04x@%d.%d\n",
rnti,
frame,
slot);
return; return;
} }
} }
sched_ctrl->cce_index = CCEIndex; sched_ctrl->cce_index = CCEIndex;
fill_pdcch_vrb_map(RC.nrmac[module_id], fill_pdcch_vrb_map(mac,
CC_id, CC_id,
&sched_ctrl->sched_pdcch, &sched_ctrl->sched_pdcch,
CCEIndex, CCEIndex,
...@@ -270,7 +265,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_ ...@@ -270,7 +265,8 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
/* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE /* check if slot is UL, and that slot is 8 (assuming K2=6 because of UE
* limitations). Note that if K2 or the TDD configuration is changed, below * limitations). Note that if K2 or the TDD configuration is changed, below
* conditions might exclude each other and never be true */ * conditions might exclude each other and never be true */
if (!is_xlsch_in_slot(ulsch_slot_bitmap, sched_slot)) int slot_period = sched_slot % nr_mac->frame_structure.numb_slots_period;
if (!is_xlsch_in_slot(ulsch_slot_bitmap, slot_period))
return false; return false;
uint16_t rbStart = 0; uint16_t rbStart = 0;
......
...@@ -150,9 +150,7 @@ uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs); ...@@ -150,9 +150,7 @@ uint16_t nr_mac_compute_RIV(uint16_t N_RB_DL, uint16_t RBstart, uint16_t Lcrbs);
/* \brief preprocessor for phytest: schedules UE_id 0 with fixed MCS on all /* \brief preprocessor for phytest: schedules UE_id 0 with fixed MCS on all
* freq resources */ * freq resources */
void nr_preprocessor_phytest(module_id_t module_id, void nr_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot);
frame_t frame,
sub_frame_t slot);
/* \brief UL preprocessor for phytest: schedules UE_id 0 with fixed MCS on a /* \brief UL preprocessor for phytest: schedules UE_id 0 with fixed MCS on a
* fixed set of resources */ * fixed set of resources */
bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot); bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_t slot);
......
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