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Michael Black
OpenXG UE
Commits
80a8b139
Commit
80a8b139
authored
Nov 02, 2020
by
Shweta Shrivastava
Browse files
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Plain Diff
Fixes for a few UE failures due to invalid DCI received
parent
be8113e1
Changes
3
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Showing
3 changed files
with
66 additions
and
26 deletions
+66
-26
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
+10
-1
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
+24
-20
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
+32
-5
No files found.
openair1/PHY/NR_UE_TRANSPORT/nr_dlsch_demodulation.c
View file @
80a8b139
...
...
@@ -242,6 +242,10 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
dlsch0_harq
->
Qm
=
nr_get_Qm_dl
(
dlsch
[
0
]
->
harq_processes
[
harq_pid
]
->
mcs
,
dlsch
[
0
]
->
harq_processes
[
harq_pid
]
->
mcs_table
);
dlsch0_harq
->
R
=
nr_get_code_rate_dl
(
dlsch
[
0
]
->
harq_processes
[
harq_pid
]
->
mcs
,
dlsch
[
0
]
->
harq_processes
[
harq_pid
]
->
mcs_table
);
if
(
dlsch0_harq
->
Qm
==
0
||
dlsch0_harq
->
R
==
0
)
{
LOG_W
(
MAC
,
"Invalid code rate or Mod order, likely due to unexpected DL DCI.
\n
"
);
return
-
1
;
}
#ifdef DEBUG_HARQ
printf
(
"[DEMOD] MIMO mode = %d
\n
"
,
dlsch0_harq
->
mimo_mode
);
...
...
@@ -981,7 +985,12 @@ int nr_rx_pdsch(PHY_VARS_NR_UE *ue,
}
if
(
dlsch1_harq
)
{
switch
(
nr_get_Qm_dl
(
dlsch1_harq
->
mcs
,
dlsch1_harq
->
mcs_table
))
{
uint8_t
Qm
=
nr_get_Qm_dl
(
dlsch1_harq
->
mcs
,
dlsch1_harq
->
mcs_table
);
if
(
Qm
==
0
){
LOG_W
(
MAC
,
"Invalid code rate or Mod order, likely due to unexpected DL DCI.
\n
"
);
return
-
1
;
}
switch
(
Qm
)
{
case
2
:
if
(
rx_type
==
rx_standard
)
{
nr_dlsch_qpsk_llr
(
frame_parms
,
...
...
openair2/LAYER2/NR_MAC_COMMON/nr_mac_common.c
View file @
80a8b139
...
...
@@ -1616,7 +1616,7 @@ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx) {
case
0
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 0 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51311
[
Imcs
][
0
]);
break
;
...
...
@@ -1624,7 +1624,7 @@ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx) {
case
1
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 1 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_51312
[
Imcs
][
0
]);
break
;
...
...
@@ -1632,13 +1632,14 @@ uint8_t nr_get_Qm_dl(uint8_t Imcs, uint8_t table_idx) {
case
2
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 2 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51313
[
Imcs
][
0
]);
break
;
default:
AssertFatal
(
0
,
"Invalid MCS table index %d (expected in range [0,2])
\n
"
,
table_idx
);
LOG_E
(
MAC
,
"Invalid MCS table index %d (expected in range [0,2])
\n
"
,
table_idx
);
return
0
;
}
}
...
...
@@ -1647,7 +1648,7 @@ uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx) {
case
0
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 0 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51311
[
Imcs
][
1
]);
break
;
...
...
@@ -1655,7 +1656,7 @@ uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx) {
case
1
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 1 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_51312
[
Imcs
][
1
]);
break
;
...
...
@@ -1663,13 +1664,14 @@ uint32_t nr_get_code_rate_dl(uint8_t Imcs, uint8_t table_idx) {
case
2
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 2 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51313
[
Imcs
][
1
]);
break
;
default:
AssertFatal
(
0
,
"Invalid MCS table index %d (expected in range [0,2])
\n
"
,
table_idx
);
LOG_E
(
MAC
,
"Invalid MCS table index %d (expected in range [0,2])
\n
"
,
table_idx
);
return
0
;
}
}
...
...
@@ -1678,7 +1680,7 @@ uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx) {
case
0
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 0 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51311
[
Imcs
][
0
]);
break
;
...
...
@@ -1686,7 +1688,7 @@ uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx) {
case
1
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 1 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_51312
[
Imcs
][
0
]);
break
;
...
...
@@ -1694,7 +1696,7 @@ uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx) {
case
2
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 2 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51313
[
Imcs
][
0
]);
break
;
...
...
@@ -1702,7 +1704,7 @@ uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx) {
case
3
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 3 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_61411
[
Imcs
][
0
]);
break
;
...
...
@@ -1710,13 +1712,14 @@ uint8_t nr_get_Qm_ul(uint8_t Imcs, uint8_t table_idx) {
case
4
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 4 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_61412
[
Imcs
][
0
]);
break
;
default:
AssertFatal
(
0
,
"Invalid MCS table index %d (expected in range [0,4])
\n
"
,
table_idx
);
LOG_E
(
MAC
,
"Invalid MCS table index %d (expected in range [0,4])
\n
"
,
table_idx
);
return
0
;
}
}
...
...
@@ -1725,7 +1728,7 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) {
case
0
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 0 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51311
[
Imcs
][
1
]);
break
;
...
...
@@ -1733,7 +1736,7 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) {
case
1
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 1 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_51312
[
Imcs
][
1
]);
break
;
...
...
@@ -1741,7 +1744,7 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) {
case
2
:
if
(
Imcs
>
28
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 2 (expected range [0,28])
\n
"
,
Imcs
);
Imcs
=
28
;
return
0
;
}
return
(
Table_51313
[
Imcs
][
1
]);
break
;
...
...
@@ -1749,7 +1752,7 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) {
case
3
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 3 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_61411
[
Imcs
][
1
]);
break
;
...
...
@@ -1757,13 +1760,14 @@ uint32_t nr_get_code_rate_ul(uint8_t Imcs, uint8_t table_idx) {
case
4
:
if
(
Imcs
>
27
)
{
LOG_E
(
MAC
,
"Invalid MCS index %d for MCS table 4 (expected range [0,27])
\n
"
,
Imcs
);
Imcs
=
27
;
return
0
;
}
return
(
Table_61412
[
Imcs
][
1
]);
break
;
default:
AssertFatal
(
0
,
"Invalid MCS table index %d (expected in range [0,4])
\n
"
,
table_idx
);
LOG_E
(
MAC
,
"Invalid MCS table index %d (expected in range [0,4])
\n
"
,
table_idx
);
return
0
;
}
}
...
...
openair2/LAYER2/NR_MAC_UE/nr_ue_procedures.c
View file @
80a8b139
...
...
@@ -675,6 +675,7 @@ uint32_t get_ssb_frame(uint32_t test){
* indication value from RRC configuration.
*/
long
get_k2
(
NR_UE_MAC_INST_t
*
mac
,
uint8_t
time_domain_ind
)
{
long
k2
=
-
1
;
// Get K2 from RRC configuration
NR_PUSCH_Config_t
*
pusch_config
=
mac
->
ULbwp
[
0
]
->
bwp_Dedicated
->
pusch_Config
->
choice
.
setup
;
NR_PUSCH_TimeDomainResourceAllocationList_t
*
pusch_TimeDomainAllocationList
=
NULL
;
...
...
@@ -684,7 +685,14 @@ long get_k2(NR_UE_MAC_INST_t *mac, uint8_t time_domain_ind) {
else
if
(
mac
->
ULbwp
[
0
]
->
bwp_Common
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
)
{
pusch_TimeDomainAllocationList
=
mac
->
ULbwp
[
0
]
->
bwp_Common
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
;
}
long
k2
=
*
pusch_TimeDomainAllocationList
->
list
.
array
[
time_domain_ind
]
->
k2
;
if
(
pusch_TimeDomainAllocationList
)
{
if
(
time_domain_ind
>=
pusch_TimeDomainAllocationList
->
list
.
count
)
{
LOG_E
(
MAC
,
"time_domain_ind %d >= pusch->TimeDomainAllocationList->list.count %d
\n
"
,
time_domain_ind
,
pusch_TimeDomainAllocationList
->
list
.
count
);
return
-
1
;
}
k2
=
*
pusch_TimeDomainAllocationList
->
list
.
array
[
time_domain_ind
]
->
k2
;
}
LOG_D
(
MAC
,
"get_k2(): k2 is %ld
\n
"
,
k2
);
return
k2
;
...
...
@@ -892,8 +900,8 @@ NR_UE_L2_STATE_t nr_ue_scheduler(nr_downlink_indication_t *dl_info, nr_uplink_in
ulcfg_pdu
->
pusch_config_pdu
.
pusch_ptrs
.
ptrs_time_density
=
ptrs_time_density
;
ulcfg_pdu
->
pusch_config_pdu
.
pusch_ptrs
.
ptrs_freq_density
=
ptrs_freq_density
;
ulcfg_pdu
->
pusch_config_pdu
.
pusch_ptrs
.
ptrs_ports_list
=
&
ptrs_ports_list
;
ulcfg_pdu
->
pusch_config_pdu
.
target_code_rate
=
nr_get_code_rate_ul
(
ulcfg_pdu
->
pusch_config_pdu
.
mcs_index
,
ulcfg_pdu
->
pusch_config_pdu
.
mcs_table
);
ulcfg_pdu
->
pusch_config_pdu
.
qam_mod_order
=
nr_get_Qm_ul
(
ulcfg_pdu
->
pusch_config_pdu
.
mcs_index
,
ulcfg_pdu
->
pusch_config_pdu
.
mcs_table
);
//
ulcfg_pdu->pusch_config_pdu.target_code_rate = nr_get_code_rate_ul(ulcfg_pdu->pusch_config_pdu.mcs_index, ulcfg_pdu->pusch_config_pdu.mcs_table);
//
ulcfg_pdu->pusch_config_pdu.qam_mod_order = nr_get_Qm_ul(ulcfg_pdu->pusch_config_pdu.mcs_index, ulcfg_pdu->pusch_config_pdu.mcs_table);
if
(
1
<<
ulcfg_pdu
->
pusch_config_pdu
.
pusch_ptrs
.
ptrs_time_density
>=
ulcfg_pdu
->
pusch_config_pdu
.
nr_of_symbols
)
{
ulcfg_pdu
->
pusch_config_pdu
.
pdu_bit_map
&=
~
PUSCH_PDU_BITMAP_PUSCH_PTRS
;
// disable PUSCH PTRS
...
...
@@ -2509,13 +2517,19 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
mu
=
mac
->
ULbwp
[
0
]
->
bwp_Common
->
genericParameters
.
subcarrierSpacing
;
// Get slot offset K2 which will be used to calculate TX slot
k2
=
get_k2
(
mac
,
dci
->
time_domain_assignment
.
val
);
if
(
k2
<
0
)
// This can happen when a false DCI is received
return
-
1
;
// Calculate TX slot and frame
slot_tx
=
(
slot
+
k2
)
%
nr_slots_per_frame
[
mu
];
frame_tx
=
((
slot
+
k2
)
>
nr_slots_per_frame
[
mu
])
?
(
frame
+
1
)
%
1024
:
frame
;
// Get UL config request corresponding slot_tx
ul_config
=
get_ul_config_request
(
mac
,
slot_tx
);
AssertFatal
(
ul_config
!=
NULL
,
"nr_ue_process_dci(): ul_config is NULL
\n
"
);
//AssertFatal(ul_config != NULL, "nr_ue_process_dci(): ul_config is NULL\n");
if
(
!
ul_config
)
{
LOG_W
(
MAC
,
"nr_ue_process_dci(): ul_config request is NULL. Probably due to unexpected UL DCI in frame.slot %d.%d. Ignoring DCI!
\n
"
,
frame
,
slot
);
return
-
1
;
}
ul_config
->
ul_config_list
[
ul_config
->
number_pdus
].
pdu_type
=
FAPI_NR_UL_CONFIG_TYPE_PUSCH
;
ul_config
->
ul_config_list
[
ul_config
->
number_pdus
].
pusch_config_pdu
.
rnti
=
rnti
;
...
...
@@ -2598,13 +2612,19 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
mu
=
mac
->
ULbwp
[
0
]
->
bwp_Common
->
genericParameters
.
subcarrierSpacing
;
// Get slot offset K2 which will be used to calculate TX slot
k2
=
get_k2
(
mac
,
dci
->
time_domain_assignment
.
val
);
if
(
k2
<
0
)
// This can happen when a false DCI is received
return
-
1
;
// Calculate TX slot and frame
slot_tx
=
(
slot
+
k2
)
%
nr_slots_per_frame
[
mu
];
frame_tx
=
((
slot
+
k2
)
>
nr_slots_per_frame
[
mu
])
?
(
frame
+
1
)
%
1024
:
frame
;
// Get UL config request corresponding slot_tx
ul_config
=
get_ul_config_request
(
mac
,
slot_tx
);
AssertFatal
(
ul_config
!=
NULL
,
"nr_ue_process_dci(): ul_config is NULL
\n
"
);
//AssertFatal(ul_config != NULL, "nr_ue_process_dci(): ul_config is NULL\n");
if
(
!
ul_config
)
{
LOG_W
(
MAC
,
"nr_ue_process_dci(): ul_config request is NULL. Probably due to unexpected UL DCI in frame.slot %d.%d. Ignoring DCI!
\n
"
,
frame
,
slot
);
return
-
1
;
}
ul_config
->
ul_config_list
[
ul_config
->
number_pdus
].
pdu_type
=
FAPI_NR_UL_CONFIG_TYPE_PUSCH
;
ul_config
->
ul_config_list
[
ul_config
->
number_pdus
].
pusch_config_pdu
.
rnti
=
rnti
;
...
...
@@ -2642,6 +2662,13 @@ int8_t nr_ue_process_dci(module_id_t module_id, int cc_id, uint8_t gNB_index, fr
pusch_config_pdu_0_1
->
mcs_table
=
get_pusch_mcs_table
(
pusch_config
->
mcs_TableTransformPrecoder
,
1
,
dci_format
,
NR_RNTI_C
,
NR_SearchSpace__searchSpaceType_PR_ue_Specific
,
false
);
pusch_config_pdu_0_1
->
target_code_rate
=
nr_get_code_rate_ul
(
pusch_config_pdu_0_1
->
mcs_index
,
pusch_config_pdu_0_1
->
mcs_table
);
pusch_config_pdu_0_1
->
qam_mod_order
=
nr_get_Qm_ul
(
pusch_config_pdu_0_1
->
mcs_index
,
pusch_config_pdu_0_1
->
mcs_table
);
if
(
pusch_config_pdu_0_1
->
target_code_rate
==
0
||
pusch_config_pdu_0_1
->
qam_mod_order
==
0
)
{
LOG_W
(
MAC
,
"Invalid code rate or Mod order, likely due to unexpected UL DCI. Ignoring DCI!
\n
"
);
return
-
1
;
}
/* NDI */
pusch_config_pdu_0_1
->
pusch_data
.
new_data_indicator
=
dci
->
ndi
;
/* RV */
...
...
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