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Michael Black
OpenXG UE
Commits
815145da
Commit
815145da
authored
May 10, 2021
by
rmagueta
Browse files
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CCE-to-REG mapping extended for 2 or more DCI symbols at UE
parent
fe511729
Changes
2
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Showing
2 changed files
with
23 additions
and
17 deletions
+23
-17
openair1/PHY/NR_TRANSPORT/nr_dci.c
openair1/PHY/NR_TRANSPORT/nr_dci.c
+3
-3
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
+20
-14
No files found.
openair1/PHY/NR_TRANSPORT/nr_dci.c
View file @
815145da
...
...
@@ -181,7 +181,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
}
/*Mapping the encoded DCI along with the DMRS */
for
(
int
symbol
=
0
;
symbol
<
pdcch_pdu_rel15
->
DurationSymbols
;
symbol
++
)
{
for
(
int
symbol
_idx
=
0
;
symbol_idx
<
pdcch_pdu_rel15
->
DurationSymbols
;
symbol_idx
++
)
{
for
(
int
cce_count
=
0
;
cce_count
<
dci_pdu
->
AggregationLevel
;
cce_count
+=
pdcch_pdu_rel15
->
DurationSymbols
)
{
int8_t
cce_idx
=
reg_list_order
[
cce_count
];
...
...
@@ -193,7 +193,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
if
(
k
>=
frame_parms
.
ofdm_symbol_size
)
k
-=
frame_parms
.
ofdm_symbol_size
;
l
=
cset_start_symb
+
symbol
;
l
=
cset_start_symb
+
symbol
_idx
;
// dmrs index depends on reference point for k according to 38.211 7.4.1.3.2
if
(
pdcch_pdu_rel15
->
CoreSetType
==
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
)
...
...
@@ -238,7 +238,7 @@ void nr_generate_dci(PHY_VARS_gNB *gNB,
}
// m
}
// reg_in_cce_idx
}
// cce_count
}
// symbol
}
// symbol
_idx
LOG_D
(
PHY
,
"DCI: payloadSize = %d | payload = %llx
\n
"
,
...
...
openair1/PHY/NR_UE_TRANSPORT/dci_nr.c
View file @
815145da
...
...
@@ -132,7 +132,7 @@ void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
if
(
reg_bundle_size_L
!=
0
)
{
// interleaving will be done only if reg_bundle_size_L != 0
coreset_interleaved
=
1
;
coreset_C
=
(
uint32_t
)
(
(
coreset_nbr_rb
*
coreset_time_dur
)
/
(
coreset_interleaver_size_R
*
reg_bundle_size_L
));
coreset_C
=
(
uint32_t
)
(
coreset_nbr_rb
/
(
coreset_interleaver_size_R
*
reg_bundle_size_L
));
}
else
{
reg_bundle_size_L
=
6
;
}
...
...
@@ -140,7 +140,7 @@ void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
int
f_bundle_j_list
[
NR_MAX_PDCCH_AGG_LEVEL
]
=
{};
for
(
int
reg
=
0
;
reg
<
((
coreset_nbr_rb
*
coreset_time_dur
))
;
reg
++
)
{
for
(
int
reg
=
0
;
reg
<
coreset_nbr_rb
;
reg
++
)
{
if
((
reg
%
reg_bundle_size_L
)
==
0
)
{
if
(
r
==
coreset_interleaver_size_R
)
{
r
=
0
;
...
...
@@ -148,7 +148,7 @@ void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
}
bundle_j
=
(
c
*
coreset_interleaver_size_R
)
+
r
;
f_bundle_j
=
((
r
*
coreset_C
)
+
c
+
n_shift
)
%
(
(
coreset_nbr_rb
*
coreset_time_dur
)
/
reg_bundle_size_L
);
f_bundle_j
=
((
r
*
coreset_C
)
+
c
+
n_shift
)
%
(
coreset_nbr_rb
/
reg_bundle_size_L
);
if
(
coreset_interleaved
==
0
)
f_bundle_j
=
bundle_j
;
...
...
@@ -174,22 +174,28 @@ void nr_pdcch_demapping_deinterleaving(uint32_t *llr,
}
}
for
(
int
reg
=
0
;
reg
<
((
coreset_nbr_rb
*
coreset_time_dur
));
reg
++
)
{
int
rb
=
0
;
for
(
int
c_id
=
0
;
c_id
<
number_of_candidates
;
c_id
++
)
{
for
(
int
symbol_idx
=
0
;
symbol_idx
<
coreset_time_dur
;
symbol_idx
++
)
{
for
(
int
cce_count
=
CCE
[
c_id
/
coreset_time_dur
]
+
c_id
%
coreset_time_dur
;
cce_count
<
CCE
[
c_id
/
coreset_time_dur
]
+
c_id
%
coreset_time_dur
+
L
[
c_id
];
cce_count
+=
coreset_time_dur
)
{
for
(
int
reg_in_cce_idx
=
0
;
reg_in_cce_idx
<
NR_NB_REG_PER_CCE
;
reg_in_cce_idx
++
)
{
f_reg
=
(
f_bundle_j_list_ord
[
reg
/
6
]
*
reg_bundle_size_L
)
+
(
reg
%
reg_bundle_size_L
)
;
index_z
=
9
*
reg
;
index_llr
=
9
*
((
uint16_t
)
floor
(
f_reg
/
coreset_time_dur
)
+
((
f_reg
%
coreset_time_dur
)
*
(
coreset_nbr_rb
)))
;
f_reg
=
(
f_bundle_j_list_ord
[
cce_count
]
*
reg_bundle_size_L
)
+
reg_in_cce_idx
;
index_z
=
9
*
rb
;
index_llr
=
(
uint16_t
)
(
f_reg
+
symbol_idx
*
coreset_nbr_rb
)
*
9
;
for
(
int
i
=
0
;
i
<
9
;
i
++
)
{
z
[
index_z
+
i
]
=
llr
[
index_llr
+
i
];
for
(
int
i
=
0
;
i
<
9
;
i
++
)
{
z
[
index_z
+
i
]
=
llr
[
index_llr
+
i
];
#ifdef NR_PDCCH_DCI_DEBUG
LOG_D
(
PHY
,
"[reg=%d,bundle_j
=%d] z[%d]=(%d,%d) <->
\t
[f_reg=%d,fbundle_j=%d] llr[%d]=(%d,%d)
\n
"
,
reg
,
bundle_j
,(
index_z
+
i
),
*
(
int16_t
*
)
&
z
[
index_z
+
i
],
*
(
1
+
(
int16_t
*
)
&
z
[
index_z
+
i
]),
f_reg
,
f_bundle_j
,(
index_llr
+
i
),
*
(
int16_t
*
)
&
llr
[
index_llr
+
i
],
*
(
1
+
(
int16_t
*
)
&
llr
[
index_llr
+
i
]));
LOG_I
(
PHY
,
"[cce_count=%d,reg_in_cce_idx=%d,bundle_j=%d,symbol_idx=%d,candidate
=%d] z[%d]=(%d,%d) <->
\t
[f_reg=%d,fbundle_j=%d] llr[%d]=(%d,%d)
\n
"
,
cce_count
,
reg_in_cce_idx
,
bundle_j
,
symbol_idx
,
c_id
,(
index_z
+
i
),
*
(
int16_t
*
)
&
z
[
index_z
+
i
],
*
(
1
+
(
int16_t
*
)
&
z
[
index_z
+
i
]),
f_reg
,
f_bundle_j
,(
index_llr
+
i
),
*
(
int16_t
*
)
&
llr
[
index_llr
+
i
],
*
(
1
+
(
int16_t
*
)
&
llr
[
index_llr
+
i
]));
#endif
}
rb
++
;
}
}
}
if
((
reg
%
reg_bundle_size_L
)
==
0
)
r
++
;
}
}
...
...
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