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Michael Black
OpenXG UE
Commits
99ce74d4
Commit
99ce74d4
authored
Jul 27, 2018
by
Guy De Souza
Browse files
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Plain Diff
Nfapi struct corrections/ DCI interface/ Phytest scheduler type 1
parent
5ed3ba33
Changes
16
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16 changed files
with
295 additions
and
211 deletions
+295
-211
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h
+60
-32
openair1/PHY/INIT/nr_init.c
openair1/PHY/INIT/nr_init.c
+0
-1
openair1/PHY/NR_TRANSPORT/nr_dci.c
openair1/PHY/NR_TRANSPORT/nr_dci.c
+3
-3
openair1/PHY/NR_TRANSPORT/nr_dci.h
openair1/PHY/NR_TRANSPORT/nr_dci.h
+0
-47
openair1/PHY/defs_gNB.h
openair1/PHY/defs_gNB.h
+1
-0
openair1/PHY/defs_nr_common.h
openair1/PHY/defs_nr_common.h
+0
-21
openair1/SCHED_NR/fapi_nr_l1.c
openair1/SCHED_NR/fapi_nr_l1.c
+1
-1
openair1/SCHED_NR/phy_procedures_nr_common.c
openair1/SCHED_NR/phy_procedures_nr_common.c
+44
-52
openair1/SCHED_NR/sched_nr.h
openair1/SCHED_NR/sched_nr.h
+8
-10
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
+4
-33
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
+62
-0
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+101
-0
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+2
-2
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+3
-3
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+5
-5
No files found.
nfapi/open-nFAPI/nfapi/public_inc/nfapi_nr_interface.h
View file @
99ce74d4
...
...
@@ -277,6 +277,27 @@ typedef enum {
NFAPI_NR_SEARCH_SPACE_TYPE_UE_SPECIFIC
}
nfapi_nr_search_space_type_e
;
typedef
enum
{
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE1
=
0
,
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE2
,
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE3
}
nfapi_nr_ssb_and_cset_mux_pattern_type_e
;
typedef
enum
{
NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED
=
0
,
NFAPI_NR_CCE_REG_MAPPING_NON_INTERLEAVED
}
nfapi_nr_cce_reg_mapping_type_e
;
typedef
enum
{
NFAPI_NR_CSET_CONFIG_MIB_SIB1
=
0
,
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
}
nfapi_nr_coreset_config_type_e
;
typedef
enum
{
NFAPI_NR_CSET_SAME_AS_REG_BUNDLE
=
0
,
NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
}
nfapi_nr_coreset_precoder_granularity_type_e
;
// P7 Sub Structures
//formats 0_0 and 0_1
typedef
struct
{
...
...
@@ -314,7 +335,7 @@ uint8_t beta_offset_indicator; //0 or 2 bits
uint8_t
dmrs_sequence_initialization
;
//0 or 1 bit
uint8_t
ul_sch_indicator
;
//1 bit
}
nfapi_nr_ul_config_dci_pdu_rel15_t
;
}
nfapi_nr_ul_config_dci_
ul_
pdu_rel15_t
;
//#define NFAPI_NR_UL_CONFIG_REQUEST_DCI_UL_PDU_REL15_TAG 0x????
//formats 1_0, 1_1, 2_0, 2_1, 2_2 and 2_3
...
...
@@ -371,44 +392,48 @@ uint16_t *pre_emption_indications; //14 bit
uint8_t
block_number_count
;
uint8_t
*
block_numbers
;
}
nfapi_nr_dl_config_dci_pdu_rel15_t
;
}
nfapi_nr_dl_config_dci_
dl_
pdu_rel15_t
;
//#define NFAPI_NR_DL_CONFIG_REQUEST_DCI_DL_PDU_REL15_TAG 0x????
typedef
struct
{
nfapi_uint8_tlv
_t
coreset_id
;
nfapi_uint64_tlv
_t
frequency_domain_resources
;
nfapi_uint8_tlv
_t
duration
;
nfapi_uint8_tlv
_t
cce_reg_mapping_type
;
nfapi_uint8_tlv
_t
reg_bundle_size
;
nfapi_uint8_tlv
_t
interleaver_size
;
nfapi_uint8_tlv
_t
shift_index
;
nfapi_uint8_tlv
_t
precoder_granularity
;
nfapi_uint8_tlv
_t
tci_state_id
;
nfapi_uint8_tlv
_t
tci_present_in_dci
;
nfapi_uint16_tlv_t
pdcch_
dmrs_scrambling_id
;
uint8
_t
coreset_id
;
uint64
_t
frequency_domain_resources
;
uint8
_t
duration
;
uint8
_t
cce_reg_mapping_type
;
uint8
_t
reg_bundle_size
;
uint8
_t
interleaver_size
;
uint8
_t
shift_index
;
uint8
_t
precoder_granularity
;
uint8
_t
tci_state_id
;
uint8
_t
tci_present_in_dci
;
uint32_t
dmrs_scrambling_id
;
}
nfapi_nr_coreset_t
;
typedef
struct
{
nfapi_uint8_tlv
_t
search_space_id
;
nfapi_uint8_tlv
_t
coreset_id
;
nfapi_uint8_tlv
_t
search_space_type
;
nfapi_uint8_tlv
_t
duration
;
nfapi_uint8_tlv
_t
css_formats_0_0_and_1_0
;
nfapi_uint8_tlv
_t
css_format_2_0
;
nfapi_uint8_tlv
_t
css_format_2_1
;
nfapi_uint8_tlv
_t
css_format_2_2
;
nfapi_uint8_tlv
_t
css_format_2_3
;
nfapi_uint8_tlv
_t
uss_dci_formats
;
nfapi_uint8_tlv
_t
srs_monitoring_periodicity
;
nfapi_uint8_tlv
_t
slot_monitoring_periodicity
;
nfapi_uint8_tlv
_t
slot_monitoring_offset
;
nfapi_uint16_tlv
_t
monitoring_symbols_in_slot
;
nfapi_uint16_tlv
_t
number_of_candidates
[
NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS
];
uint8
_t
search_space_id
;
uint8
_t
coreset_id
;
uint8
_t
search_space_type
;
uint8
_t
duration
;
uint8
_t
css_formats_0_0_and_1_0
;
uint8
_t
css_format_2_0
;
uint8
_t
css_format_2_1
;
uint8
_t
css_format_2_2
;
uint8
_t
css_format_2_3
;
uint8
_t
uss_dci_formats
;
uint8
_t
srs_monitoring_periodicity
;
uint8
_t
slot_monitoring_periodicity
;
uint8
_t
slot_monitoring_offset
;
uint16
_t
monitoring_symbols_in_slot
;
uint16
_t
number_of_candidates
[
NFAPI_NR_MAX_NB_CCE_AGGREGATION_LEVELS
];
}
nfapi_nr_search_space_t
;
typedef
struct
{
nfapi_tl_t
tl
;
uint8_t
rnti
;
uint8_t
rnti_type
;
uint8_t
dci_format
;
uint8_t
aggregation_level
;
uint8_t
n_rb
;
uint8_t
n_symb
;
uint8_t
rb_offset
;
...
...
@@ -419,6 +444,7 @@ typedef struct {
uint8_t
first_slot
;
uint8_t
first_symbol
;
uint8_t
nb_ss_sets_per_slot
;
uint8_t
nb_slots
;
uint8_t
sfn_mod2
;
uint8_t
search_space_type
;
uint16_t
scrambling_id
;
...
...
@@ -462,14 +488,18 @@ typedef struct {
}
nfapi_nr_dl_config_ndlsch_pdu_rel15_t
;
typedef
struct
{
nfapi_nr_dl_config_dci_dl_pdu_rel15_t
dci_dl_pdu_rel15
;
nfapi_nr_dl_config_pdcch_parameters_rel15_t
pdcch_params_rel15
;
}
nfapi_nr_dl_config_dci_dl_pdu
;
typedef
struct
{
uint8_t
pdu_type
;
uint8_t
pdu_size
;
union
{
nfapi_nr_dl_config_dci_pdu_rel15_t
dci_dl_pdu_rel15
;
nfapi_nr_ul_config_dci_pdu_rel15_t
dci_ul_pdu_rel15
;
nfapi_nr_dl_config_dci_dl_pdu
dci_dl_pdu
;
nfapi_nr_dl_config_bch_pdu_rel15_t
bch_pdu_rel15
;
nfapi_nr_dl_config_dlsch_pdu_rel15_t
dlsch_pdu_rel15
;
nfapi_nr_dl_config_pch_pdu_rel15_t
pch_pdu_rel15
;
...
...
@@ -477,8 +507,6 @@ typedef struct {
nfapi_nr_dl_config_npdcch_pdu_rel15_t
npdcch_pdu_rel15
;
nfapi_nr_dl_config_ndlsch_pdu_rel15_t
ndlsch_pdu_rel15
;
};
nfapi_nr_dl_config_pdcch_parameters_rel15_t
pdcch_params_rel15
;
}
nfapi_nr_dl_config_request_pdu_t
;
typedef
struct
{
...
...
openair1/PHY/INIT/nr_init.c
View file @
99ce74d4
...
...
@@ -20,7 +20,6 @@
*/
#include "PHY/defs_gNB.h"
#include "SCHED/sched_eNB.h"
#include "PHY/phy_extern.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
#include "PHY/INIT/phy_init.h"
...
...
openair1/PHY/NR_TRANSPORT/nr_dci.c
View file @
99ce74d4
...
...
@@ -173,7 +173,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
/// DMRS QPSK modulation
/*There is a need to shift from which index the pregenerated DMRS sequence is used
* see 38211 r15.2.0 section 7.4.1.3.2: assumption is the reference point for k refers to the DMRS sequence*/
if
(
pdcch_params
.
config_type
==
nr_cset_config_pdcch_config
)
if
(
pdcch_params
.
config_type
==
NFAPI_NR_CSET_CONFIG_PDCCH_CONFIG
)
gold_pdcch_dmrs
+=
((
int
)
floor
(
frame_parms
.
ssb_start_subcarrier
/
NR_NB_SC_PER_RB
)
+
pdcch_params
.
rb_offset
)
*
3
/
32
;
for
(
int
i
=
0
;
i
<
NR_MAX_PDCCH_DMRS_LENGTH
>>
1
;
i
++
)
{
...
...
@@ -219,7 +219,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
if
(
cset_start_sc
>=
frame_parms
.
ofdm_symbol_size
)
cset_start_sc
-=
frame_parms
.
ofdm_symbol_size
;
if
(
pdcch_params
.
precoder_granularity
==
nr_cset_same_as_reg_bundle
)
{
if
(
pdcch_params
.
precoder_granularity
==
NFAPI_NR_CSET_SAME_AS_REG_BUNDLE
)
{
for
(
int
cce_idx
=
0
;
cce_idx
<
dci_alloc
.
L
;
cce_idx
++
){
cce
=
dci_alloc
.
cce_list
[
cce_idx
];
...
...
@@ -247,7 +247,7 @@ uint8_t nr_generate_dci_top(NR_gNB_PDCCH pdcch_vars,
}
}
else
{
//
nr_cset_all_contiguous_rbs
else
{
//
NFAPI_NR_CSET_ALL_CONTIGUOUS_RBS
}
}
...
...
openair1/PHY/NR_TRANSPORT/nr_dci.h
View file @
99ce74d4
...
...
@@ -25,53 +25,6 @@
#include "PHY/defs_gNB.h"
#include "PHY/NR_REFSIG/nr_refsig.h"
typedef
enum
{
nr_dci_format_0_0
=
0
,
nr_dci_format_0_1
,
nr_dci_format_2_0
,
nr_dci_format_2_1
,
nr_dci_format_2_2
,
nr_dci_format_2_3
,
nr_dci_format_1_0
,
nr_dci_format_1_1
,
}
nr_dci_format_e
;
typedef
enum
{
nr_rnti_type_SI_RNTI
=
0
,
nr_rnti_type_RA_RNTI
,
nr_rnti_type_C_RNTI
,
nr_rnti_type_TC_RNTI
,
nr_rnti_type_CS_RNTI
,
nr_rnti_type_P_RNTI
}
nr_rnti_type_e
;
typedef
struct
{
uint8_t
param_O
;
uint8_t
param_M
;
uint8_t
nb_ss_sets_per_slot
;
uint8_t
first_symbol_idx
;
}
nr_pdcch_ss_params_t
;
typedef
struct
{
uint8_t
n_rb
;
uint8_t
n_symb
;
uint8_t
rb_offset
;
nr_cce_reg_mapping_type_e
cr_mapping_type
;
nr_ssb_and_cset_mux_pattern_type_e
mux_pattern
;
nr_coreset_precoder_granularity_type_e
precoder_granularity
;
nr_coreset_config_type_e
config_type
;
}
nr_pdcch_coreset_params_t
;
typedef
struct
{
uint8_t
first_slot
;
uint8_t
nb_slots
;
uint8_t
sfn_mod2
;
uint32_t
dmrs_scrambling_id
;
nr_cce_t
cce_list
[
NR_MAX_PDCCH_AGG_LEVEL
];
nr_pdcch_ss_params_t
ss_params
;
nr_pdcch_coreset_params_t
coreset_params
;
}
nr_pdcch_vars_t
;
typedef
unsigned
__int128
uint128_t
;
uint8_t
nr_get_dci_size
(
nfapi_nr_dci_format_e
format
,
...
...
openair1/PHY/defs_gNB.h
View file @
99ce74d4
...
...
@@ -292,6 +292,7 @@ typedef struct PHY_VARS_gNB_s {
Sched_Rsp_t
Sched_INFO
;
NR_gNB_PDCCH
pdcch_vars
;
nfapi_nr_dl_config_pdcch_parameters_rel15_t
pdcch_type0_params
;
LTE_eNB_PHICH
phich_vars
[
2
];
NR_gNB_COMMON
common_vars
;
...
...
openair1/PHY/defs_nr_common.h
View file @
99ce74d4
...
...
@@ -112,27 +112,6 @@ typedef struct NR_BWP_PARMS {
uint16_t
ofdm_symbol_size
;
}
NR_BWP_PARMS
;
typedef
enum
{
nr_ssb_and_cset_mux_pattern_type_1
=
0
,
nr_ssb_and_cset_mux_pattern_type_2
,
nr_ssb_and_cset_mux_pattern_type_3
}
nr_ssb_and_cset_mux_pattern_type_e
;
typedef
enum
{
nr_cce_reg_mapping_interleaved
=
0
,
nr_cce_reg_mapping_non_interleaved
}
nr_cce_reg_mapping_type_e
;
typedef
enum
{
nr_cset_config_mib_sib1
=
0
,
nr_cset_config_pdcch_config
}
nr_coreset_config_type_e
;
typedef
enum
{
nr_cset_same_as_reg_bundle
=
0
,
nr_cset_all_contiguous_rbs
}
nr_coreset_precoder_granularity_type_e
;
typedef
struct
{
uint8_t
reg_idx
;
uint8_t
start_sc_idx
;
...
...
openair1/SCHED_NR/fapi_nr_l1.c
View file @
99ce74d4
...
...
@@ -61,7 +61,7 @@ void handle_nfapi_nr_dci_dl_pdu(PHY_VARS_gNB *gNB,
{
int
idx
=
subframe
&
1
;
NR_gNB_PDCCH
*
pdcch_vars
=
&
gNB
->
pdcch_vars
;
nfapi_nr_dl_config_dci_
pdu_rel15_t
*
pdu
=
&
dl_config_pdu
->
dci_dl_pdu_rel15
;
nfapi_nr_dl_config_dci_
dl_pdu_rel15_t
*
pdu
=
&
dl_config_pdu
->
dci_dl_pdu
.
dci_dl_pdu_rel15
;
LOG_D
(
PHY
,
"Frame %d, Subframe %d: DCI processing - populating pdcch_vars->dci_alloc[%d] proc:subframe_tx:%d idx:%d pdcch_vars->num_dci:%d
\n
"
,
frame
,
subframe
,
pdcch_vars
->
num_dci
,
proc
->
subframe_tx
,
idx
,
pdcch_vars
->
num_dci
);
...
...
openair1/SCHED_NR/phy_procedures_nr_common.c
View file @
99ce74d4
...
...
@@ -60,25 +60,29 @@ nr_subframe_t nr_subframe_select(nfapi_nr_config_request_t *cfg,unsigned char su
}
void
nr_get_pdcch_vars_from_mib
(
nr_pdcch_vars_t
*
pdcch_vars
,
nr_scs_e
scs_common
,
nr_scs_e
pdcch_scs
,
nr_frequency_range_e
freq_range
,
uint8_t
rmsi_pdcch_config
,
uint16_t
N_RB
)
void
nr_configure_css_dci_from_mib
(
nfapi_nr_dl_config_pdcch_parameters_rel15_t
*
pdcch_params
,
nr_scs_e
scs_common
,
nr_scs_e
pdcch_scs
,
nr_frequency_range_e
freq_range
,
uint8_t
rmsi_pdcch_config
,
uint8_t
ssb_idx
,
uint16_t
nb_slots_per_frame
,
uint16_t
N_RB
)
{
nr_pdcch_coreset_params_t
*
coreset_params
=
&
pdcch_vars
->
coreset_params
;
nr_pdcch_ss_params_t
*
ss_params
=
&
pdcch_vars
->
ss_params
;
uint8_t
O
,
M
;
uint8_t
ss_idx
=
rmsi_pdcch_config
&
0xf
;
uint8_t
cset_idx
=
(
rmsi_pdcch_config
>>
4
)
&
0xf
;
uint8_t
mu
;
/// Coreset params
switch
(
scs_common
)
{
case
kHz15
:
mu
=
0
;
break
;
case
kHz30
:
mu
=
1
;
if
(
N_RB
<
106
)
{
// Minimum 40Mhz bandwidth not satisfied
switch
(
pdcch_scs
)
{
...
...
@@ -86,10 +90,10 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
break
;
case
kHz30
:
coreset_params
->
mux_pattern
=
nr_ssb_and_cset_mux_pattern_type_
1
;
coreset
_params
->
n_rb
=
(
cset_idx
<
10
)
?
24
:
48
;
coreset
_params
->
n_symb
=
nr_coreset_nsymb_pdcch_type_0_b40Mhz
[
cset_idx
];
coreset
_params
->
rb_offset
=
nr_coreset_rb_offset_pdcch_type_0_b40Mhz
[
cset_idx
];
pdcch_params
->
mux_pattern
=
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE
1
;
pdcch
_params
->
n_rb
=
(
cset_idx
<
10
)
?
24
:
48
;
pdcch
_params
->
n_symb
=
nr_coreset_nsymb_pdcch_type_0_b40Mhz
[
cset_idx
];
pdcch
_params
->
rb_offset
=
nr_coreset_rb_offset_pdcch_type_0_b40Mhz
[
cset_idx
];
break
;
default:
...
...
@@ -104,10 +108,10 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
break
;
case
kHz30
:
coreset_params
->
mux_pattern
=
nr_ssb_and_cset_mux_pattern_type_
1
;
coreset
_params
->
n_rb
=
(
cset_idx
<
4
)
?
24
:
48
;
coreset
_params
->
n_symb
=
nr_coreset_nsymb_pdcch_type_0_b40Mhz
[
cset_idx
];
coreset
_params
->
rb_offset
=
nr_coreset_rb_offset_pdcch_type_0_b40Mhz
[
cset_idx
];
pdcch_params
->
mux_pattern
=
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE
1
;
pdcch
_params
->
n_rb
=
(
cset_idx
<
4
)
?
24
:
48
;
pdcch
_params
->
n_symb
=
nr_coreset_nsymb_pdcch_type_0_b40Mhz
[
cset_idx
];
pdcch
_params
->
rb_offset
=
nr_coreset_rb_offset_pdcch_type_0_b40Mhz
[
cset_idx
];
break
;
default:
...
...
@@ -116,9 +120,11 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
}
case
kHz60
:
mu
=
2
;
break
;
case
kHz120
:
mu
=
3
;
break
;
default:
...
...
@@ -127,60 +133,46 @@ void nr_get_pdcch_vars_from_mib(nr_pdcch_vars_t *pdcch_vars,
}
/// Search space params
switch
(
coreset
_params
->
mux_pattern
)
{
switch
(
pdcch
_params
->
mux_pattern
)
{
case
nr_ssb_and_cset_mux_pattern_type_
1
:
case
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE
1
:
if
(
freq_range
==
nr_FR1
)
{
ss_params
->
param_
O
=
nr_ss_param_O_type_0_mux1_FR1
[
ss_idx
];
ss
_params
->
nb_ss_sets_per_slot
=
nr_ss_sets_per_slot_type_0_FR1
[
ss_idx
];
ss_params
->
param_
M
=
nr_ss_param_M_type_0_mux1_FR1
[
ss_idx
];
ss_params
->
first_symbol_idx
=
(
ss_idx
<
8
)
?
(
(
ss_idx
&
1
)
?
coreset
_params
->
n_symb
:
0
)
:
nr_ss_first_symb_idx_type_0_mux1_FR1
[
ss_idx
-
8
];
O
=
nr_ss_param_O_type_0_mux1_FR1
[
ss_idx
];
pdcch
_params
->
nb_ss_sets_per_slot
=
nr_ss_sets_per_slot_type_0_FR1
[
ss_idx
];
M
=
nr_ss_param_M_type_0_mux1_FR1
[
ss_idx
];
pdcch_params
->
first_symbol
=
(
ss_idx
<
8
)
?
(
(
ss_idx
&
1
)
?
pdcch
_params
->
n_symb
:
0
)
:
nr_ss_first_symb_idx_type_0_mux1_FR1
[
ss_idx
-
8
];
}
else
{
AssertFatal
(
ss_idx
<
14
,
"Invalid search space index for multiplexing type 1 and FR2 %d
\n
"
,
ss_idx
);
ss_params
->
param_
O
=
nr_ss_param_O_type_0_mux1_FR2
[
ss_idx
];
ss
_params
->
nb_ss_sets_per_slot
=
nr_ss_sets_per_slot_type_0_FR2
[
ss_idx
];
ss_params
->
param_
M
=
nr_ss_param_M_type_0_mux1_FR2
[
ss_idx
];
ss_params
->
first_symbol_idx
=
(
ss_idx
<
12
)
?
(
(
ss_idx
&
1
)
?
7
:
0
)
:
0
;
O
=
nr_ss_param_O_type_0_mux1_FR2
[
ss_idx
];
pdcch
_params
->
nb_ss_sets_per_slot
=
nr_ss_sets_per_slot_type_0_FR2
[
ss_idx
];
M
=
nr_ss_param_M_type_0_mux1_FR2
[
ss_idx
];
pdcch_params
->
first_symbol
=
(
ss_idx
<
12
)
?
(
(
ss_idx
&
1
)
?
7
:
0
)
:
0
;
}
pdcch_params
->
nb_slots
=
2
;
pdcch_params
->
sfn_mod2
=
((
uint8_t
)(
floor
(
(
O
*
pow
(
2
,
mu
)
+
floor
(
ssb_idx
*
M
))
/
nb_slots_per_frame
))
&
1
)
?
1
:
0
;
pdcch_params
->
first_slot
=
(
uint8_t
)(
O
*
pow
(
2
,
mu
)
+
floor
(
ssb_idx
*
M
))
%
nb_slots_per_frame
;
break
;
case
nr_ssb_and_cset_mux_pattern_type_
2
:
case
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE
2
:
break
;
case
nr_ssb_and_cset_mux_pattern_type_
3
:
case
NFAPI_NR_SSB_AND_CSET_MUX_PATTERN_TYPE
3
:
break
;
default:
AssertFatal
(
1
==
0
,
"Invalid SSB and coreset multiplexing pattern %d
\n
"
,
coreset
_params
->
mux_pattern
);
AssertFatal
(
1
==
0
,
"Invalid SSB and coreset multiplexing pattern %d
\n
"
,
pdcch
_params
->
mux_pattern
);
}
pdcch_params
->
config_type
=
NFAPI_NR_CSET_CONFIG_MIB_SIB1
;
pdcch_params
->
cr_mapping_type
=
NFAPI_NR_CCE_REG_MAPPING_INTERLEAVED
;
pdcch_params
->
precoder_granularity
=
NFAPI_NR_CSET_SAME_AS_REG_BUNDLE
;
}
void
nr_get_pdcch_type_0_monitoring_period
(
nr_pdcch_vars_t
*
pdcch_vars
,
uint8_t
mu
,
uint8_t
nb_slots_per_frame
,
uint8_t
ssb_idx
)
{
uint8_t
O
=
pdcch_vars
->
ss_params
.
param_O
,
M
=
pdcch_vars
->
ss_params
.
param_M
;
if
(
pdcch_vars
->
coreset_params
.
mux_pattern
==
nr_ssb_and_cset_mux_pattern_type_1
)
{
pdcch_vars
->
nb_slots
=
2
;
pdcch_vars
->
sfn_mod2
=
((
uint8_t
)(
floor
(
(
O
*
pow
(
2
,
mu
)
+
floor
(
ssb_idx
*
M
))
/
nb_slots_per_frame
))
&
1
)
?
1
:
0
;
pdcch_vars
->
first_slot
=
(
uint8_t
)(
O
*
pow
(
2
,
mu
)
+
floor
(
ssb_idx
*
M
))
%
nb_slots_per_frame
;
}
else
{
//nr_ssb_and_cset_mux_pattern_type_2, nr_ssb_and_cset_mux_pattern_type_3
pdcch_vars
->
nb_slots
=
1
;
}
}
void
nr_get_pdcch_vars_from_config
(
nr_pdcch_vars_t
*
pdcch_vars
,
nfapi_nr_coreset_t
*
coreset
,
nfapi_nr_search_space_t
*
search_space
)
{
void
nr_configure_css_dci_from_pdcch_config
(
nfapi_nr_dl_config_pdcch_parameters_rel15_t
*
pdcch_params
,
nfapi_nr_coreset_t
*
coreset
,
nfapi_nr_search_space_t
*
search_space
)
{
nr_pdcch_coreset_params_t
cset_params
=
pdcch_vars
->
coreset_params
;
nr_pdcch_ss_params_t
ss_params
=
pdcch_vars
->
ss_params
;
}
openair1/SCHED_NR/sched_nr.h
View file @
99ce74d4
...
...
@@ -42,15 +42,13 @@ void nr_feptx_ofdm(RU_t *ru);
void
nr_feptx_ofdm_2thread
(
RU_t
*
ru
);
void
nr_feptx0
(
RU_t
*
ru
,
int
slot
);
void
nr_get_pdcch_vars_from_mib
(
nr_pdcch_vars_t
*
pdcch_vars
,
nr_scs_e
scs_common
,
nr_scs_e
pdcch_scs
,
nr_frequency_range_e
freq_range
,
uint8_t
rmsi_pdcch_config
,
uint16_t
N_RB
);
void
nr_get_pdcch_type_0_monitoring_period
(
nr_pdcch_vars_t
*
pdcch_vars
,
uint8_t
mu
,
uint8_t
nb_slots_per_frame
,
uint8_t
ssb_idx
);
void
nr_configure_css_dci_from_mib
(
nfapi_nr_dl_config_pdcch_parameters_rel15_t
*
pdcch_params
,
nr_scs_e
scs_common
,
nr_scs_e
pdcch_scs
,
nr_frequency_range_e
freq_range
,
uint8_t
rmsi_pdcch_config
,
uint8_t
ssb_idx
,
uint16_t
nb_slots_per_frame
,
uint16_t
N_RB
);
#endif
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler.c
View file @
99ce74d4
...
...
@@ -417,42 +417,13 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
schedule_nr_mib
(
module_idP
,
frameP
,
subframeP
);
}
/*
* Temporary DCI scheduling for PDCCH testing in the absence of phy-test mode and pending proper scheduling
* currently schedules PDCCH type 1 for RA-RNTI*/
/*
if (phy_test == 0){
// This schedules SI for legacy LTE and eMTC starting in subframeP
schedule_SI(module_idP, frameP, subframeP);
// This schedules Paging in subframeP
schedule_PCH(module_idP,frameP,subframeP);
// This schedules Random-Access for legacy LTE and eMTC starting in subframeP
schedule_RA(module_idP, frameP, subframeP);
// copy previously scheduled UL resources (ULSCH + HARQ)
copy_nr_ulreq(module_idP, frameP, subframeP);
// This schedules SRS in subframeP
schedule_nr_SRS(module_idP, frameP, subframeP);
// This schedules ULSCH in subframeP (dci0)
schedule_ulsch(module_idP, frameP, subframeP);
// This schedules UCI_SR in subframeP
schedule_nr_SR(module_idP, frameP, subframeP);
// This schedules UCI_CSI in subframeP
schedule_nr_CSI(module_idP, frameP, subframeP);
// This schedules DLSCH in subframeP
schedule_dlsch(module_idP, frameP, subframeP, mbsfn_status);
if
(
phy_test
==
0
)
{
}
else{
schedule_ulsch_phy_test(module_idP,frameP,subframeP);
schedule_ue_spec_phy_test(module_idP,frameP,subframeP,mbsfn_status);
else
{
void
nr_schedule_css_dlsch_phytest
(
module_idP
,
frameP
,
subframeP
);
}
*/
if
(
RC
.
flexran
[
module_idP
]
->
enabled
)
flexran_agent_send_update_stats
(
module_idP
);
/*
// Allocate CCEs for good after scheduling is done
for (CC_id = 0; CC_id < MAX_NUM_CCs; CC_id++)
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_RA.c
0 → 100644
View file @
99ce74d4
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.1 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file gNB_scheduler_RA.c
* \brief primitives used for random access
* \author
* \date
* \email:
* \version
*/
#include nr_mac_gNB.h
void
schedule_RA
(
module_id_t
module_idP
,
frame_t
frameP
,
sub_frame_t
subframeP
)
{
eNB_MAC_INST
*
mac
=
RC
.
mac
[
module_idP
];
COMMON_channels_t
*
cc
=
mac
->
common_channels
;
RA_t
*
ra
;
uint8_t
i
;
start_meas
(
&
mac
->
schedule_ra
);
for
(
CC_id
=
0
;
CC_id
<
MAX_NUM_CCs
;
CC_id
++
)
{
for
(
i
=
0
;
i
<
NB_RA_PROC_MAX
;
i
++
)
{
ra
=
(
RA_t
*
)
&
cc
[
CC_id
].
ra
[
i
];
//LOG_D(MAC,"RA[state:%d]\n",ra->state);
if
(
ra
->
state
==
MSG2
)
generate_Msg2
(
module_idP
,
CC_id
,
frameP
,
subframeP
,
ra
);
else
if
(
ra
->
state
==
MSG4
)
generate_Msg4
(
module_idP
,
CC_id
,
frameP
,
subframeP
,
ra
);
else
if
(
ra
->
state
==
WAITMSG4ACK
)
check_Msg4_retransmission
(
module_idP
,
CC_id
,
frameP
,
subframeP
,
ra
);
}
// for i=0 .. N_RA_PROC-1
}
// CC_id
stop_meas
(
&
mac
->
schedule_ra
);
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_bch.c
View file @
99ce74d4
...
...
@@ -30,7 +30,7 @@
*/
#include "assertions.h"
#include "LAYER2/NR_MAC_gNB/
mac
.h"
#include "LAYER2/NR_MAC_gNB/
nr_mac_gNB
.h"
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
#include "LAYER2/MAC/mac_extern.h"
#include "UTIL/LOG/log.h"
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
0 → 100644
View file @
99ce74d4
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/*! \file gNB_scheduler_phytest.c
* \brief gNB scheduling procedures in phy_test mode
* \author Guy De Souza
* \date 07/2018
* \email: desouza@eurecom.fr
* \version 1.0
* @ingroup _mac
*/
#include "nr_mac_gNB.h"
#include "PHY/SCHED/sched_nr.h"
extern
RAN_CONTEXT_t
RC
;
/*Scheduling of DLSCH with associated DCI in common search space
* current version has only a DCI for type 1 PDCCH for RA-RNTI*/
void
nr_schedule_css_dlsch_phytest
(
module_id_t
module_idP
,
frame_t
frameP
,
sub_frame_t
subframeP
)
{
uint8_t
CC_id
;
gNB_MAC_INST
*
gNB_mac
=
RC
.
mac
[
module_idP
];
NR_COMMON_channels_t
*
cc
=
gNB_mac
->
common_channels
;
nfapi_nr_dl_config_request_body_t
*
dl_req
;
nfapi_nr_dl_config_request_pdu_t
*
dl_config_pdu
;
for
(
CC_id
=
0
;
CC_id
<
MAX_NUM_CCs
;
CC_id
++
)
{
LOG_I
(
MAC
,
"Scheduling common search space DCI type 1 for CC_id %d
\n
"
,
CC_id
);
PHY_VARS_gNB_s
*
gNB
=
RC
.
gNB
[
module_idP
][
CC_id
];
nfapi_nr_config_request_t
*
config
=
gNB
->
gNB_config
;
dl_req
=
&
gNB_mac
->
DL_req
[
CC_id
].
dl_config_request_body
;
dl_config_pdu
=
&
dl_req
->
dl_config_pdu_list
[
dl_req
->
number_of_pdus
];
memset
((
void
*
)
dl_config_pdu
,
0
,
sizeof
(
nfapi_nr_dl_config_request_pdu_t
));
dl_config_pdu
->
pdu_type
=
NFAPI_NR_DL_CONFIG_DCI_DL_PDU_TYPE
;
dl_config_pdu
->
pdu_size
=
(
uint8_t
)(
2
+
sizeof
(
nfapi_nr_dl_config_dci_dl_pdu
));
nfapi_nr_dl_config_dci_dl_pdu_rel15_t
*
pdu_rel15
=
&
dl_config_pdu
->
dci_dl_pdu
.
dci_dl_pdu_rel15
;
nfapi_nr_dl_config_pdcch_parameters_rel15_t
*
params_rel15
=
&
dl_config_pdu
->
dci_dl_pdu
.
pdcch_params_rel15
;
nr_configure_css_dci_from_mib
(
&
gNB
->
pdcch_type0_params
,
kHz30
,
kHz30
,
NR_FR1
,
0
,
0
,
fp
->
slots_per_frame
,
cfg
->
rf_config
.
dl_channel_bandwidth
.
value
);
pdu_rel15
->
frequency_domain_resource_assignment
=
5
;
pdu_rel15
->
time_domain_resource_assignment
=
2
;
pdu_rel15
->
vrb_to_prb_mapping
=
0
;
pdu_rel15
->
tb_scaling
=
1
;
LOG_I
(
PHY
,
"DCI type 1 payload: freq_alloc %d, time_alloc %d, vrb to prb %d, tb_scaling %d
\n
"
,
pdu_rel15
->
frequency_domain_resource_assignment
,
pdu_rel15
->
time_domain_resource_assignment
,
pdu_rel15
->
vrb_to_prb_mapping
,
pdu_rel15
->
tb_scaling
);
params_rel15
->
rnti
=
0x03
;
params_rel15
->
rnti_type
=
NFAPI_NR_RNTI_RA
;
params_rel15
->
dci_format
=
NFAPI_NR_DL_DCI_FORMAT_1_0
;
params_rel15
->
aggregation_level
=
4
;
LOG_I
(
PHY
,
"DCI type 1 params: rmsi_pdcch_config, rnti %d, rnti_type %d, dci_format, L %d
\n
\
coreset params: mux_pattern %d, n_rb %d, n_symb %d, rb_offset %d
\n
\
ss params : nb_ss_sets_per_slot %d, first symb %d, nb_slots %d, sfn_mod2 %d, first slot %d
\n
"
,
0
,
params_rel15
->
rnti
,
params_rel15
->
rnti_type
,
params_rel15
->
dci_format
,
params_rel15
->
aggregation_level
,
params_rel15
->
mux_pattern
,
params_rel15
->
n_rb
,
params_rel15
->
n_symb
,
params_rel15
->
rb_offset
,
params_rel15
->
nb_ss_sets_per_slot
,
params_rel15
->
first_symbol
,
params_rel15
->
nb_slots
,
params_rel15
->
sfn_mod2
,
params_rel15
->
first_slot
);
}
}
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
99ce74d4
...
...
@@ -32,7 +32,7 @@
#include "assertions.h"
#include "LAYER2/MAC/mac.h"
#include "LAYER2/NR_MAC_gNB/
mac
.h"
#include "LAYER2/NR_MAC_gNB/
nr_mac_gNB
.h"
#include "LAYER2/MAC/mac_extern.h"
#include "LAYER2/NR_MAC_gNB/mac_proto.h"
...
...
@@ -119,4 +119,4 @@ int is_nr_UL_sf(NR_COMMON_channels_t * ccP, sub_frame_t subframeP){
subframeP
,
(
int
)
ccP
->
tdd_Config
->
subframeAssignment
);
break
;
}
}
\ No newline at end of file
}
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @
99ce74d4
...
...
@@ -2,8 +2,8 @@
#ifndef __LAYER2_NR_MAC_PROTO_H__
#define __LAYER2_NR_MAC_PROTO_H__
#include "
mac
.h"
#include "PHY/defs_
nr_common
.h"
#include "
nr_mac_gNB
.h"
#include "PHY/defs_
gNB
.h"
void
mac_top_init_gNB
(
void
);
...
...
@@ -30,4 +30,4 @@ void gNB_dlsch_ulsch_scheduler(module_id_t module_idP,
void
schedule_nr_mib
(
module_id_t
module_idP
,
frame_t
frameP
,
sub_frame_t
subframeP
);
#endif
/*__LAYER2_NR_MAC_PROTO_H__*/
\ No newline at end of file
#endif
/*__LAYER2_NR_MAC_PROTO_H__*/
openair2/LAYER2/NR_MAC_gNB/
mac
.h
→
openair2/LAYER2/NR_MAC_gNB/
nr_mac_gNB
.h
View file @
99ce74d4
...
...
@@ -34,8 +34,8 @@
/*@}*/
#ifndef __LAYER2_NR_MAC_
DEFS
_H__
#define __LAYER2_NR_MAC_
DEFS
_H__
#ifndef __LAYER2_NR_MAC_
GNB
_H__
#define __LAYER2_NR_MAC_
GNB
_H__
#include <stdio.h>
#include <stdlib.h>
...
...
@@ -52,13 +52,13 @@
#include "PHY/TOOLS/time_meas.h"
#include "PHY/defs_
common.h" // for PRACH_RESOURCES_t
#include "PHY/defs_
gNB.h"
#include "targets/ARCH/COMMON/common_lib.h"
#include "LAYER2/MAC/mac.h" // temporary
/*! \brief
e
NB common channels */
/*! \brief
g
NB common channels */
typedef
struct
{
int
physCellId
;
int
p_gNB
;
...
...
@@ -163,4 +163,4 @@ typedef struct gNB_MAC_INST_s {
time_stats_t
schedule_pch
;
}
gNB_MAC_INST
;
#endif
/*__LAYER2_NR_MAC_
DEFS
_H__ */
#endif
/*__LAYER2_NR_MAC_
GNB
_H__ */
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