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Michael Black
OpenXG-RAN
Commits
2780e004
Commit
2780e004
authored
Aug 18, 2021
by
francescomani
Browse files
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fix vrb map filling for csi-rs
parent
d606e73a
Changes
1
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Showing
1 changed file
with
17 additions
and
17 deletions
+17
-17
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+17
-17
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
2780e004
...
...
@@ -2120,20 +2120,20 @@ void nr_csirs_scheduling(int Mod_idP,
csirs_pdu_rel15
->
row
=
1
;
csirs_pdu_rel15
->
freq_domain
=
((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row1
.
buf
[
0
])
>>
4
)
&
0x0f
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row2
:
csirs_pdu_rel15
->
row
=
2
;
csirs_pdu_rel15
->
freq_domain
=
(((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row2
.
buf
[
1
]
>>
4
)
&
0x0f
)
|
((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row2
.
buf
[
0
]
<<
8
)
&
0xff0
));
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_row4
:
csirs_pdu_rel15
->
row
=
4
;
csirs_pdu_rel15
->
freq_domain
=
((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
row4
.
buf
[
0
])
>>
5
)
&
0x07
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__frequencyDomainAllocation_PR_other
:
csirs_pdu_rel15
->
freq_domain
=
((
resourceMapping
.
frequencyDomainAllocation
.
choice
.
other
.
buf
[
0
])
>>
2
)
&
0x3f
;
...
...
@@ -2144,18 +2144,18 @@ void nr_csirs_scheduling(int Mod_idP,
case
NR_CSI_RS_ResourceMapping__nrofPorts_p2
:
csirs_pdu_rel15
->
row
=
3
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p4
:
csirs_pdu_rel15
->
row
=
5
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p8
:
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
8
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
}
else
{
int
num_k
=
0
;
...
...
@@ -2164,12 +2164,12 @@ void nr_csirs_scheduling(int Mod_idP,
if
(
num_k
==
4
)
{
csirs_pdu_rel15
->
row
=
6
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
}
else
{
csirs_pdu_rel15
->
row
=
7
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
}
}
break
;
...
...
@@ -2177,12 +2177,12 @@ void nr_csirs_scheduling(int Mod_idP,
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
10
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
}
else
{
csirs_pdu_rel15
->
row
=
9
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
1
<<
csirs_pdu_rel15
->
symb_l0
);
}
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p16
:
...
...
@@ -2191,24 +2191,24 @@ void nr_csirs_scheduling(int Mod_idP,
else
csirs_pdu_rel15
->
row
=
11
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
1
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
2
<<
csirs_pdu_rel15
->
symb_l0
));
break
;
case
NR_CSI_RS_ResourceMapping__nrofPorts_p24
:
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
14
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
else
{
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm8_FD2_TD4
)
{
csirs_pdu_rel15
->
row
=
15
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
7
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
7
<<
csirs_pdu_rel15
->
symb_l0
);
}
else
{
csirs_pdu_rel15
->
row
=
13
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
}
break
;
...
...
@@ -2216,18 +2216,18 @@ void nr_csirs_scheduling(int Mod_idP,
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm4_FD2_TD2
)
{
csirs_pdu_rel15
->
row
=
17
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
else
{
if
(
resourceMapping
.
cdm_Type
==
NR_CSI_RS_ResourceMapping__cdm_Type_cdm8_FD2_TD4
)
{
csirs_pdu_rel15
->
row
=
18
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
(
7
<<
csirs_pdu_rel15
->
symb_l0
);
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
(
7
<<
csirs_pdu_rel15
->
symb_l0
);
}
else
{
csirs_pdu_rel15
->
row
=
16
;
for
(
int
rb
=
csirs_pdu_rel15
->
start_rb
;
rb
<
(
csirs_pdu_rel15
->
start_rb
+
csirs_pdu_rel15
->
nr_of_rbs
);
rb
++
)
vrb_map
[
rb
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
vrb_map
[
rb
+
csirs_pdu_rel15
->
bwp_start
]
|=
((
3
<<
csirs_pdu_rel15
->
symb_l0
)
|
(
3
<<
csirs_pdu_rel15
->
symb_l1
));
}
}
break
;
...
...
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