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Michael Black
OpenXG-RAN
Commits
d606e73a
Commit
d606e73a
authored
Aug 18, 2021
by
francescomani
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fix PRB allocation for phytest mode
parent
ba816f69
Changes
2
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2 changed files
with
12 additions
and
8 deletions
+12
-8
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+11
-7
No files found.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
d606e73a
...
...
@@ -743,7 +743,7 @@ void nr_fr1_dlsch_preprocessor(module_id_t module_id, frame_t frame, sub_frame_t
// calculate mask: init with "NOT" vrb_map:
// if any RB in vrb_map is blocked (1), the current RBG will be 0
rballoc_mask
[
i
-
BWPStart
]
=
!
vrb_map
[
i
];
n_rb_sched
+=
rballoc_mask
[
i
];
n_rb_sched
+=
rballoc_mask
[
i
-
BWPStart
];
}
/* Retrieve amount of data to send for this UE */
...
...
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @
d606e73a
...
...
@@ -283,6 +283,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
/* find largest unallocated chunk */
const
int
bwpSize
=
NRRIV2BW
(
sched_ctrl
->
active_bwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
const
int
BWPStart
=
NRRIV2PRBOFFSET
(
sched_ctrl
->
active_bwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
int
rbStart
=
0
;
int
rbSize
=
0
;
if
(
target_dl_bw
>
bwpSize
)
...
...
@@ -291,11 +292,11 @@ void nr_preprocessor_phytest(module_id_t module_id,
/* loop ensures that we allocate exactly target_dl_bw, or return */
while
(
true
)
{
/* advance to first free RB */
while
(
rbStart
<
bwpSize
&&
vrb_map
[
rbStart
])
while
(
rbStart
<
bwpSize
&&
vrb_map
[
rbStart
+
BWPStart
])
rbStart
++
;
rbSize
=
1
;
/* iterate until we are at target_dl_bw or no available RBs */
while
(
rbStart
+
rbSize
<
bwpSize
&&
!
vrb_map
[
rbStart
+
rbSize
]
&&
rbSize
<
target_dl_bw
)
while
(
rbStart
+
rbSize
<
bwpSize
&&
!
vrb_map
[
rbStart
+
rbSize
+
BWPStart
]
&&
rbSize
<
target_dl_bw
)
rbSize
++
;
/* found target_dl_bw? */
if
(
rbSize
==
target_dl_bw
)
...
...
@@ -392,7 +393,7 @@ void nr_preprocessor_phytest(module_id_t module_id,
/* mark the corresponding RBs as used */
for
(
int
rb
=
0
;
rb
<
sched_pdsch
->
rbSize
;
rb
++
)
vrb_map
[
rb
+
sched_pdsch
->
rbStart
]
=
1
;
vrb_map
[
rb
+
sched_pdsch
->
rbStart
+
BWPStart
]
=
1
;
if
((
frame
&
127
)
==
0
)
LOG_D
(
MAC
,
"phytest: %d.%d DL mcs %d, DL rbStart %d, DL rbSize %d
\n
"
,
frame
,
slot
,
sched_pdsch
->
mcs
,
rbStart
,
rbSize
);
}
...
...
@@ -454,8 +455,11 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
uint16_t
rbSize
;
const
int
bw
=
NRRIV2BW
(
sched_ctrl
->
active_ubwp
?
sched_ctrl
->
active_ubwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
:
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
sched_ctrl
->
active_ubwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
:
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
const
int
BWPStart
=
NRRIV2PRBOFFSET
(
sched_ctrl
->
active_ubwp
?
sched_ctrl
->
active_ubwp
->
bwp_Common
->
genericParameters
.
locationAndBandwidth
:
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
genericParameters
.
locationAndBandwidth
,
MAX_BWP_SIZE
);
if
(
target_ul_bw
>
bw
)
rbSize
=
bw
;
...
...
@@ -466,7 +470,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
&
RC
.
nrmac
[
module_id
]
->
common_channels
[
CC_id
].
vrb_map_UL
[
sched_slot
*
MAX_BWP_SIZE
];
const
uint16_t
symb
=
((
1
<<
ps
->
nrOfSymbols
)
-
1
)
<<
ps
->
startSymbolIndex
;
for
(
int
i
=
rbStart
;
i
<
rbStart
+
rbSize
;
++
i
)
{
if
((
vrb_map_UL
[
i
]
&
symb
)
!=
0
)
{
if
((
vrb_map_UL
[
i
+
BWPStart
]
&
symb
)
!=
0
)
{
LOG_E
(
MAC
,
"%s(): %4d.%2d RB %d is already reserved, cannot schedule UE
\n
"
,
__func__
,
...
...
@@ -528,6 +532,6 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
/* mark the corresponding RBs as used */
for
(
int
rb
=
rbStart
;
rb
<
rbStart
+
rbSize
;
rb
++
)
vrb_map_UL
[
rb
]
=
1
;
vrb_map_UL
[
rb
+
BWPStart
]
=
1
;
return
true
;
}
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