Add nrLDPC_cnProc_group_2pass_512() — a native 512-bit variant of the
two-pass min-sum CN processor — and update the BG1/BG2 wrappers to
dispatch to the widest available register set.

Kernel design:
- Uses AVX512BW mask-register comparisons (simde__mmask64) and
  predicated blend (simde_mm512_mask_blend_epi8) for single-cycle
  select instead of the vector-mask XOR trick used in the 256-bit path.
- Pass 1: simde_mm512_abs/xor/min_epu8/max_epu8 — same structure as
  256-bit kernel, 64 CNs per iteration.
- Pass 2: eq_mask = cmpeq_epi8_mask(|vk|, vmin1);
          out_mag = mask_blend_epi8(eq_mask, vmin1, vmin2);
          neg_mask = cmpgt_epi8_mask(zeros, other_xor);
          result = mask_blend_epi8(neg_mask, out_mag, -out_mag)

Wrapper dispatch (compile-time):
  __AVX512BW__: 512-bit, M = ceil(numCN*Z/64), off >>= 6
  __AVX2__:     256-bit, M = ceil(numCN*Z/32), off >>= 5
  else:         128-bit, M = ceil(numCN*Z/16), off >>= 4

All buffer strides (lut_numCnInCnGroups_{BG1_R13,BG2_R15}[grp] *
NR_LDPC_ZMAX) are divisible by 64, so the 512-bit stride is exact.

Compile-tested: -mavx512bw   → exit 0 (512-bit path)
  -mavx2       → exit 0 (256-bit path)
  -mno-avx2    → exit 0 (128-bit path, pre-existing Wpsabi warning)
Signed-off-by: Raymond Knopp <raymond.knopp@eurecom.fr>
Assisted-by: Claude:claude-sonnet-4.6