Commit 0b3d0986 authored by Robert Schmidt's avatar Robert Schmidt

Merge remote-tracking branch 'origin/fhi-f-release' into integration_2024_w49 (!3147)

Fronthaul xran library update to F release (2. and final step towards M-plane integration)

- xran library support -> both E and F releases
- RU delay profile removed -> not used in neither of the releases
- DU delay profile updated
- one-way delay measurements support is improved/fixed in the F release.
  However, not implemented here as it depends on the RU capabilities
parents ee1605b8 b7c3d593
......@@ -263,11 +263,6 @@ fhi_72 = {
ru_addr = ("98:ae:71:01:c5:eb", "98:ae:71:01:c5:eb");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (285, 429);
T2a_cp_ul = (285, 429);
T2a_up = (125, 428);
Ta3 = (130, 170);
T1a_cp_dl = (285, 470);
T1a_cp_ul = (285, 429);
T1a_up = (125, 350);
......
......@@ -271,11 +271,6 @@ fhi_72 = {
ru_addr = ("70:b3:d5:e1:5b:81", "70:b3:d5:e1:5b:81");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (259, 500);
T2a_cp_ul = (25, 500);
T2a_up = (134, 375);
Ta3 = (152, 160);
T1a_cp_dl = (419, 470);
T1a_cp_ul = (285, 336);
T1a_up = (294, 345);
......
......@@ -78,8 +78,10 @@ Tested libxran releases:
| Vendor |
|-----------------------------------------|
| `oran_e_maintenance_release_v1.0` |
| `oran_f_release_v1.0` |
**Note**: The libxran driver of OAI identifies the above version as "5.1.0" (E is fifth letter, then 1.0).
**Note**: The libxran driver of OAI identifies the above E release version as "5.1.0" (E is fifth letter, then 1.0), and the above F release as "6.1.0".
## Configure your server
......@@ -379,19 +381,22 @@ cd ~/openairinterface5g/
## Build ORAN Fronthaul Interface Library
Download ORAN FHI DU library and checkout the correct version.
Download ORAN FHI DU library, checkout the correct version, and apply the correct patch (available in `oai_folder/cmake_targets/tools/oran_fhi_integration_patches`).
### E release
```bash
git clone https://gerrit.o-ran-sc.org/r/o-du/phy.git ~/phy
cd ~/phy
git checkout oran_e_maintenance_release_v1.0
git apply ~/openairinterface5g/cmake_targets/tools/oran_fhi_integration_patches/E/oaioran_E.patch
```
Apply the patch (available in `oai_folder/cmake_targets/tools/oran_fhi_integration_patches/E`):
### F release
```bash
git clone https://gerrit.o-ran-sc.org/r/o-du/phy.git ~/phy
cd ~/phy
git apply ~/openairinterface5g/cmake_targets/tools/oran_fhi_integration_patches/E/oaioran_E.patch
git checkout oran_f_release_v1.0
git apply ~/openairinterface5g/cmake_targets/tools/oran_fhi_integration_patches/F/oaioran_F.patch
```
Compile the fronthaul interface library by calling `make` and the option
......@@ -404,7 +409,8 @@ environment variables `RTE_SDK` for the path to the source tree of DPDK, and
```bash
cd ~/phy/fhi_lib/lib
make clean
RTE_SDK=~/dpdk-stable-20.11.9/ XRAN_DIR=~/phy/fhi_lib make XRAN_LIB_SO=1
RTE_SDK=~/dpdk-stable-20.11.9/ XRAN_DIR=~/phy/fhi_lib make XRAN_LIB_SO=1 # E release
WIRELESS_SDK_TOOLCHAIN=gcc RTE_SDK=~/dpdk-stable-20.11.9/ XRAN_DIR=~/phy/fhi_lib make XRAN_LIB_SO=1 # F release
...
[AR] build/libxran.so
./build/libxran.so
......@@ -911,6 +917,7 @@ Edit the sample OAI gNB configuration file and check following parameters:
cannot preallocate memory on NUMA nodes other than 0; in this case, set
this to 0 (no pre-allocation) and so that DPDK will allocate it on-demand
on the right NUMA node.
* `owdm_enable`: used for eCPRI One-Way Delay Measurements; it depends if the RU supports it; if not set to 1 (enabled), default value is 0 (disabled)
* `fh_config`: parameters that need to match RU parameters
* timing parameters (starting with `T`) depend on the RU: `Tadv_cp_dl` is a
single number, the rest pairs of numbers `(x, y)` specifying minimum and
......@@ -928,7 +935,9 @@ Layer mapping (eAxC offsets) happens as follows:
- For PUSCH/PDSCH, the layers are mapped to `[0,1,...,Nrx-1]/[0,1,...,Ntx-1]` where `Nrx/Ntx` is the
respective RX/TX number of antennas.
- For PRACH, the layers are mapped to `[No,No+1,...No+Nrx-1]` where `No` is the
`fhi_72.fh_config.[0].prach_config.eAxC_offset`. Please be aware that the following equation must be fullfilled: `No >= max(Nrx,Ntx)`.
`fhi_72.fh_config.[0].prach_config.eAxC_offset`. xran assumes PRACH offset `No >= max(Nrx,Ntx)`.
However, we made a workaround that xran supports PRACH eAxC IDs same as PUSCH eAxC IDs. This is achieved with `is_prach` and `filter_id` parameters in the patch.
Please note that this approach only applies to the RUs that support this functionality, e.g. LITEON RU.
**Note**
......
......@@ -43,10 +43,10 @@ RUN wget http://fast.dpdk.org/rel/dpdk-20.11.9.tar.xz && \
## Build Fronthaul library
RUN git clone https://gerrit.o-ran-sc.org/r/o-du/phy.git /opt/phy && \
cd /opt/phy && \
git checkout oran_e_maintenance_release_v1.0 &&\
git apply /oai-ran/cmake_targets/tools/oran_fhi_integration_patches/E/oaioran_E.patch && \
git checkout oran_f_release_v1.0 &&\
git apply /oai-ran/cmake_targets/tools/oran_fhi_integration_patches/F/oaioran_F.patch && \
cd /opt/phy/fhi_lib/lib && \
RTE_SDK=/oai-ran/dpdk-stable-20.11.9/ XRAN_DIR=/opt/phy/fhi_lib make XRAN_LIB_SO=1
WIRELESS_SDK_TOOLCHAIN=gcc RTE_SDK=/oai-ran/dpdk-stable-20.11.9/ XRAN_DIR=/opt/phy/fhi_lib make XRAN_LIB_SO=1
FROM ran-base AS ran-build-fhi72
ARG E2AP_VERSION=E2AP_V3
......
......@@ -56,10 +56,10 @@ RUN wget http://fast.dpdk.org/rel/dpdk-20.11.9.tar.xz && \
## Build Fronthaul library
RUN git clone https://gerrit.o-ran-sc.org/r/o-du/phy.git /opt/phy && \
cd /opt/phy && \
git checkout oran_e_maintenance_release_v1.0 &&\
git apply /oai-ran/cmake_targets/tools/oran_fhi_integration_patches/E/oaioran_E.patch && \
git checkout oran_f_release_v1.0 &&\
git apply /oai-ran/cmake_targets/tools/oran_fhi_integration_patches/F/oaioran_F.patch && \
cd /opt/phy/fhi_lib/lib && \
RTE_SDK=/oai-ran/dpdk-stable-20.11.9/ XRAN_DIR=/opt/phy/fhi_lib make XRAN_LIB_SO=1
WIRELESS_SDK_TOOLCHAIN=gcc RTE_SDK=/oai-ran/dpdk-stable-20.11.9/ XRAN_DIR=/opt/phy/fhi_lib make XRAN_LIB_SO=1
FROM ran-base AS ran-build-fhi72
## Build and install OAI
......
......@@ -9,12 +9,6 @@ endif()
pkg_check_modules(dpdk REQUIRED libdpdk)
pkg_check_modules(numa REQUIRED numa)
find_package(xran 5.1.4 EXACT REQUIRED) # E release -> 5
# Ignore xran-specific warning: we don't care/can't change the following warning, so suppress
# alignment 1 of 'struct XYZ' is less than 2
add_compile_options(-Wno-packed-not-aligned)
add_library(oran_fhlib_5g MODULE
oran_isolate.c
oaioran.c
......@@ -22,6 +16,19 @@ add_library(oran_fhlib_5g MODULE
oran-init.c
)
find_package(xran REQUIRED)
if(xran_VERSION VERSION_EQUAL 5.1.4)
target_compile_definitions(oran_fhlib_5g PRIVATE E_RELEASE)
elseif(xran_VERSION VERSION_EQUAL 6.1.1)
target_compile_definitions(oran_fhlib_5g PRIVATE F_RELEASE)
else()
message(FATAL_ERROR "Found xran version ${xran_VERSION} but needed 5.1.4 (E release) or 6.1.1 (F release)")
endif()
# Ignore xran-specific warning: we don't care/can't change the following warning, so suppress
# alignment 1 of 'struct XYZ' is less than 2
add_compile_options(-Wno-packed-not-aligned)
set_target_properties(oran_fhlib_5g PROPERTIES COMPILE_FLAGS "-fvisibility=hidden -march=native")
target_link_libraries(oran_fhlib_5g PRIVATE xran::xran)
target_link_libraries(oran_fhlib_5g PRIVATE ${dpdk_LINK_LIBRARIES})
......
......@@ -90,7 +90,7 @@ void oai_xran_fh_rx_callback(void *pCallbackTag, xran_status_t status)
tti = xran_get_slot_idx_from_tti(rx_tti, &frame, &subframe, &slot, &second);
rx_sym = callback_tag->symbol;
rx_sym = callback_tag->symbol & 0xFF;
uint32_t ru_id = callback_tag->oXuId;
LOG_D(NR_PHY,
......@@ -101,7 +101,23 @@ void oai_xran_fh_rx_callback(void *pCallbackTag, xran_status_t status)
(unsigned long long)second,
rx_sym,
ru_id);
if (rx_sym == 7) {
if (rx_sym == 7) { // in F release this value is defined as XRAN_FULL_CB_SYM (full slot (offset + 7))
#ifdef F_RELEASE
int32_t nCellIdx = callback_tag->cellId;
int32_t ntti = (rx_tti + XRAN_N_FE_BUF_LEN - 1) % XRAN_N_FE_BUF_LEN;
for(uint32_t ant_id = 0; ant_id < fh_config->neAxc; ant_id++) {
struct xran_prb_map *pRbMap = (struct xran_prb_map *)xran_ctx->sFrontHaulRxPrbMapBbuIoBufCtrl[ntti][nCellIdx][ant_id].sBufferList.pBuffers->pData;
AssertFatal(pRbMap != NULL, "(%d:%d:%d)pRbMap == NULL. Aborting.\n", nCellIdx, ntti, ant_id);
for (uint32_t sym_id = 0; sym_id < XRAN_NUM_OF_SYMBOL_PER_SLOT; sym_id++) {
for (uint32_t idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++ ) {
struct xran_prb_elm *pRbElm = &pRbMap->prbMap[idxElm];
pRbElm->nSecDesc[sym_id] = 0; // number of section descriptors per symbol; M-plane info <supported-section-types>
}
}
}
#endif
if (first_call_set) {
if (!first_rx_set) {
LOG_I(NR_PHY, "first_rx is set (num_ports %d), first_read_set %d\n", num_ports, first_read_set);
......@@ -332,7 +348,11 @@ int xran_fh_rx_read_slot(ru_info_t *ru, int *frame, int *slot)
struct xran_prb_map *pPrbMap = (struct xran_prb_map *)pPrbMapData;
struct xran_prb_elm *pRbElm = &pPrbMap->prbMap[0];
#ifdef E_RELEASE
struct xran_section_desc *p_sec_desc = pRbElm->p_sec_desc[sym_idx][0];
#elif defined F_RELEASE
struct xran_section_desc *p_sec_desc = &pRbElm->sec_desc[sym_idx][0];
#endif
uint32_t one_rb_size =
(((pRbElm->iqWidth == 0) || (pRbElm->iqWidth == 16)) ? (N_SC_PER_PRB * 2 * 2) : (3 * pRbElm->iqWidth + 1));
if (fh_init->mtu < pRbElm->nRBSize * one_rb_size)
......@@ -486,9 +506,12 @@ int xran_fh_tx_send_slot(ru_info_t *ru, int frame, int slot, uint64_t timestamp)
for (idxElm = 0; idxElm < pRbMap->nPrbElm; idxElm++) {
struct xran_section_desc *p_sec_desc = NULL;
p_prbMapElm = &pRbMap->prbMap[idxElm];
p_sec_desc =
// assumes one fragment per symbol
p_prbMapElm->p_sec_desc[sym_id][0];
// assumes one fragment per symbol
#ifdef E_RELEASE
p_sec_desc = p_prbMapElm->p_sec_desc[sym_id][0];
#elif F_RELEASE
p_sec_desc = &p_prbMapElm->sec_desc[sym_id][0];
#endif
dst = xran_add_hdr_offset(dst, p_prbMapElm->compMethod);
......
This diff is collapsed.
......@@ -29,6 +29,7 @@
#include "oaioran.h"
#include "common/utils/assertions.h"
#include "common/utils/LOG/log.h"
#include "common_lib.h"
/* PRACH data samples are 32 bits wide (16bits for I/Q). Each packet contains
......@@ -140,10 +141,10 @@ static uint32_t oran_allocate_uplane_buffers(
{
xran_status_t status;
uint32_t pool;
// we need at least XRAN_N_FE_BUF_LEN * ant * XRAN_NUM_OF_SYMBOL_PER_SLOT
// buffers, but xran_bm_init() uses rte_pktmbuf_pool_create() which
// recommends to use a power of two for the buffers
uint32_t numBufs = next_power_2(XRAN_N_FE_BUF_LEN * ant * XRAN_NUM_OF_SYMBOL_PER_SLOT);
/* xran_bm_init() uses rte_pktmbuf_pool_create() which recommends to use a power of two for the buffers;
the E release sample app didn't take this into account, but we introduced it ourselves;
the F release sample app took this into account, so we can proudly say we assumed correctly */
uint32_t numBufs = next_power_2(XRAN_N_FE_BUF_LEN * ant * XRAN_NUM_OF_SYMBOL_PER_SLOT) - 1;
status = xran_bm_init(instHandle, &pool, numBufs, bufSize);
AssertFatal(XRAN_STATUS_SUCCESS == status, "Failed at xran_bm_init(), status %d\n", status);
printf("xran_bm_init() hInstance %p poolIdx %u elements %u size %u\n", instHandle, pool, numBufs, bufSize);
......@@ -217,26 +218,33 @@ static void oran_allocate_cplane_buffers(void *instHandle,
struct xran_flat_buffer buf[XRAN_MAX_ANTENNA_NR][XRAN_N_FE_BUF_LEN],
uint32_t ant,
uint32_t sect,
#ifdef F_RELEASE
uint32_t mtu,
const struct xran_fh_config *fh_config,
#endif
uint32_t size_of_prb_map,
const oran_cplane_prb_config *prb_conf)
oran_cplane_prb_config *prb_conf)
{
xran_status_t status;
uint32_t count1 = 0;
#ifdef E_RELEASE
uint32_t count2 = 0;
uint32_t poolSec;
uint32_t numBufsSec = next_power_2(XRAN_N_FE_BUF_LEN * ant * XRAN_NUM_OF_SYMBOL_PER_SLOT * sect * XRAN_MAX_FRAGMENT);
uint32_t bufSizeSec = sizeof(struct xran_section_desc);
status = xran_bm_init(instHandle, &poolSec, numBufsSec, bufSizeSec);
AssertFatal(XRAN_STATUS_SUCCESS == status, "Failed at xran_bm_init(), status %d\n", status);
printf("xran_bm_init() hInstance %p poolIdx %u elements %u size %u\n", instHandle, poolSec, numBufsSec, bufSizeSec);
#endif
uint32_t poolPrb;
uint32_t numBufsPrb = next_power_2(XRAN_N_FE_BUF_LEN * ant * XRAN_NUM_OF_SYMBOL_PER_SLOT);
uint32_t numBufsPrb = next_power_2(XRAN_N_FE_BUF_LEN * ant * XRAN_NUM_OF_SYMBOL_PER_SLOT) - 1;
uint32_t bufSizePrb = size_of_prb_map;
status = xran_bm_init(instHandle, &poolPrb, numBufsPrb, bufSizePrb);
AssertFatal(XRAN_STATUS_SUCCESS == status, "Failed at xran_bm_init(), status %d\n", status);
printf("xran_bm_init() hInstance %p poolIdx %u elements %u size %u\n", instHandle, poolPrb, numBufsPrb, bufSizePrb);
uint32_t count1 = 0;
uint32_t count2 = 0;
for (uint32_t a = 0; a < ant; a++) {
for (uint32_t j = 0; j < XRAN_N_FE_BUF_LEN; ++j) {
list[a][j].pBuffers = &buf[a][j];
......@@ -254,13 +262,15 @@ static void oran_allocate_cplane_buffers(void *instHandle,
fb->pData = ptr;
fb->pCtrl = mb;
// the original sample app code copies up to size_of_prb_map, but I think
// this is wrong because the way it is computed leads to a number larger
// than sizeof(map)
struct xran_prb_map *p_rb_map = (struct xran_prb_map *)ptr;
const struct xran_prb_map *src = &prb_conf->slotMap;
struct xran_prb_map *src = &prb_conf->slotMap;
if ((j % prb_conf->nTddPeriod) == prb_conf->mixed_slot_index)
src = &prb_conf->mixedSlotMap;
#ifdef E_RELEASE
/* as per E release sample app, the memory is copied up to size_of_prb_map
which translates to >= sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm)*5,
but we assume that RB allocation is done as 1 RE/UE so the total memory size is sizeof(struct xran_prb_map);
this is improved in F release */
struct xran_prb_map *p_rb_map = (struct xran_prb_map *)ptr;
memcpy(p_rb_map, src, sizeof(*src));
for (uint32_t elm_id = 0; elm_id < p_rb_map->nPrbElm; ++elm_id) {
......@@ -282,10 +292,19 @@ static void oran_allocate_cplane_buffers(void *instHandle,
}
}
}
#elif defined F_RELEASE
if (fh_config->RunSlotPrbMapBySymbolEnable) {
xran_init_PrbMap_by_symbol_from_cfg(src, ptr, mtu, fh_config->nDLRBs);
} else {
xran_init_PrbMap_from_cfg(src, ptr, mtu);
}
#endif
}
}
printf("xran_bm_allocate_buffer() hInstance %p poolIdx %u count %u\n", instHandle, poolPrb, count1);
#ifdef E_RELEASE
printf("xran_bm_allocate_buffer() hInstance %p poolIdx %u count %u\n", instHandle, poolSec, count2);
#endif
}
/* callback not actively used */
......@@ -298,6 +317,9 @@ static void oran_allocate_buffers(void *handle,
int xran_inst,
int num_sectors,
oran_port_instance_t *portInstances,
#ifdef F_RELEASE
uint32_t mtu,
#endif
const struct xran_fh_config *fh_config)
{
AssertFatal(num_sectors == 1, "only support one sector at the moment\n");
......@@ -305,7 +327,6 @@ static void oran_allocate_buffers(void *handle,
AssertFatal(handle != NULL, "no handle provided\n");
uint32_t xran_max_antenna_nr = RTE_MAX(fh_config->neAxc, fh_config->neAxcUl);
uint32_t xran_max_sections_per_slot = RTE_MAX(fh_config->max_sections_per_slot, XRAN_MIN_SECTIONS_PER_SLOT);
uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (xran_max_sections_per_slot - 1);
pi->buf_list = _mm_malloc(sizeof(*pi->buf_list), 256);
AssertFatal(pi->buf_list != NULL, "out of memory\n");
......@@ -331,11 +352,23 @@ static void oran_allocate_buffers(void *handle,
.slotMap = dlPm,
.mixedSlotMap = dlPmMixed,
};
#ifdef E_RELEASE
uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (xran_max_sections_per_slot - 1);
#elif defined F_RELEASE
uint32_t numPrbElm = xran_get_num_prb_elm(&dlPmMixed, mtu);
uint32_t size_of_prb_map = sizeof(struct xran_prb_map) + sizeof(struct xran_prb_elm) * (numPrbElm);
#endif
oran_allocate_cplane_buffers(pi->instanceHandle,
bl->srccp,
bl->bufs.tx_prbmap,
xran_max_antenna_nr,
xran_max_sections_per_slot,
#ifdef F_RELEASE
mtu,
fh_config,
#endif
size_of_prb_map,
&dlConf);
......@@ -357,6 +390,10 @@ static void oran_allocate_buffers(void *handle,
bl->bufs.rx_prbmap,
xran_max_antenna_nr,
xran_max_sections_per_slot,
#ifdef F_RELEASE
mtu,
fh_config,
#endif
size_of_prb_map,
&ulConf);
......@@ -422,7 +459,12 @@ int *oai_oran_initialize(struct xran_fh_init *xran_fh_init, struct xran_fh_confi
struct xran_cb_tag tag = {.cellId = sector, .oXuId = o_xu_id};
pi->prach_tag = tag;
pi->pusch_tag = tag;
#ifdef E_RELEASE
LOG_W(PHY, "Please be aware that E release support will be removed by the end of January 2025. Instead, F release will be mandatory.\n");
oran_allocate_buffers(gxran_handle, o_xu_id, 1, pi, &xran_fh_config[o_xu_id]);
#elif defined F_RELEASE
oran_allocate_buffers(gxran_handle, o_xu_id, 1, pi, xran_fh_init->mtu, &xran_fh_config[o_xu_id]);
#endif
if ((xret = xran_reg_physide_cb(gxran_handle, oai_physide_dl_tti_call_back, NULL, 10, XRAN_CB_TTI)) != XRAN_STATUS_SUCCESS) {
printf("xran_reg_physide_cb failed %d\n", xret);
......
......@@ -37,6 +37,7 @@
#define ORAN_CONFIG_NETHPERPORT "eth_lines"
#define ORAN_CONFIG_NETHSPEED "eth_speed"
#define ORAN_CONFIG_DPDK_MEM_SIZE "dpdk_mem_size"
#define ORAN_CONFIG_ECPRI_OWDM "owdm_enable"
// clang-format off
// TODO: PCI addr check
......@@ -52,16 +53,12 @@
{ORAN_CONFIG_NETHPERPORT, "number of links per port\n", 0, .uptr=NULL, .defuintval=1, TYPE_UINT, 0}, \
{ORAN_CONFIG_NETHSPEED, "ethernet speed link\n", 0, .uptr=NULL, .defuintval=10, TYPE_UINT, 0}, \
{ORAN_CONFIG_DPDK_MEM_SIZE, "DPDK huge page pre-allocation in MiB\n", 0, .uptr=NULL, .defuintval=8192, TYPE_UINT, 0}, \
{ORAN_CONFIG_ECPRI_OWDM, "eCPRI One-Way Delay Measurements\n", PARAMFLAG_BOOL, .uptr=NULL, .defuintval=0, TYPE_UINT, 0}, \
}
// clang-format on
#define CONFIG_STRING_ORAN_FH "fh_config"
#define ORAN_FH_CONFIG_TADV_CP_DL "Tadv_cp_dl"
#define ORAN_FH_CONFIG_T2A_CP_DL "T2a_cp_dl"
#define ORAN_FH_CONFIG_T2A_CP_UL "T2a_cp_ul"
#define ORAN_FH_CONFIG_T2A_UP "T2a_up"
#define ORAN_FH_CONFIG_TA3 "Ta3"
#define ORAN_FH_CONFIG_T1A_CP_DL "T1a_cp_dl"
#define ORAN_FH_CONFIG_T1A_CP_UL "T1a_cp_ul"
#define ORAN_FH_CONFIG_T1A_UP "T1a_up"
......@@ -73,11 +70,6 @@
// clang-format off
#define ORAN_FH_DESC { \
{ORAN_FH_CONFIG_TADV_CP_DL, "Tadv parameter of RU\n", PARAMFLAG_MANDATORY, .uptr=NULL, .defuintval=0, TYPE_UINT, 0}, \
{ORAN_FH_CONFIG_T2A_CP_DL, "T2a_cp_dl" ORAN_FH_HLP_CPLT, PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
{ORAN_FH_CONFIG_T2A_CP_UL, "T2a_cp_ul" ORAN_FH_HLP_CPLT, PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
{ORAN_FH_CONFIG_T2A_UP, "T2a_up" ORAN_FH_HLP_CPLT, PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
{ORAN_FH_CONFIG_TA3, "Ta3" ORAN_FH_HLP_CPLT, PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
{ORAN_FH_CONFIG_T1A_CP_DL, "T1a_cp_dl" ORAN_FH_HLP_CPLT, PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
{ORAN_FH_CONFIG_T1A_CP_UL, "T1a_cp_ul" ORAN_FH_HLP_CPLT, PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
{ORAN_FH_CONFIG_T1A_UP, "T1a_up" ORAN_FH_HLP_CPLT, PARAMFLAG_MANDATORY, .uptr=NULL, .defintarrayval=0, TYPE_UINTARRAY, 0}, \
......
......@@ -253,11 +253,6 @@ fhi_72 = {
ru_addr = ("8c:1f:64:d1:10:46","8c:1f:64:d1:10:46");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (259, 500);
T2a_cp_ul = (25, 500);
T2a_up = (134, 375);
Ta3 = (152, 160);
T1a_cp_dl = (419, 470);
T1a_cp_ul = (285, 336);
T1a_up = (294, 345);
......
......@@ -255,11 +255,6 @@ fhi_72 = {
fh_config = (
# RAN650 #1
{
Tadv_cp_dl = 125;
T2a_cp_dl = (259, 500);
T2a_cp_ul = (25, 500);
T2a_up = (134, 375);
Ta3 = (152, 160);
T1a_cp_dl = (419, 470);
T1a_cp_ul = (285, 336);
T1a_up = (294, 345);
......@@ -271,11 +266,6 @@ fhi_72 = {
},
# RAN650 #2
{
Tadv_cp_dl = 125;
T2a_cp_dl = (259, 500);
T2a_cp_ul = (25, 500);
T2a_up = (134, 375);
Ta3 = (152, 160);
T1a_cp_dl = (419, 470);
T1a_cp_ul = (285, 336);
T1a_up = (294, 345);
......
......@@ -269,11 +269,6 @@ fhi_72 = {
ru_addr = ("98:ae:71:01:c5:eb", "98:ae:71:01:c5:eb");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (285, 429);
T2a_cp_ul = (285, 429);
T2a_up = (125, 428);
Ta3 = (130, 170);
T1a_cp_dl = (285, 470);
T1a_cp_ul = (285, 429);
T1a_up = (125, 350);
......
......@@ -266,11 +266,6 @@ fhi_72 = {
ru_addr = ("98:ae:71:01:c5:eb", "98:ae:71:01:c5:eb");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (285, 429);
T2a_cp_ul = (285, 429);
T2a_up = (125, 428);
Ta3 = (130, 170);
T1a_cp_dl = (285, 470);
T1a_cp_ul = (285, 429);
T1a_up = (125, 350);
......
......@@ -268,11 +268,6 @@ fhi_72 = {
ru_addr = ("98:ae:71:01:c5:eb", "98:ae:71:01:c5:eb");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (285, 429);
T2a_cp_ul = (285, 429);
T2a_up = (125, 428);
Ta3 = (130, 170);
T1a_cp_dl = (285, 470);
T1a_cp_ul = (285, 429);
T1a_up = (125, 350);
......
......@@ -268,11 +268,6 @@ fhi_72 = {
ru_addr = ("70:b3:d5:e1:5b:81", "70:b3:d5:e1:5b:81");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (259, 500);
T2a_cp_ul = (25, 500);
T2a_up = (134, 375);
Ta3 = (152, 160);
T1a_cp_dl = (419, 470);
T1a_cp_ul = (285, 336);
T1a_up = (294, 345);
......
......@@ -270,11 +270,6 @@ fhi_72 = {
ru_addr = ("70:b3:d5:e1:5b:81", "70:b3:d5:e1:5b:81");
mtu = 9600;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (259, 500);
T2a_cp_ul = (25, 500);
T2a_up = (134, 375);
Ta3 = (152, 160);
T1a_cp_dl = (419, 470);
T1a_cp_ul = (285, 336);
T1a_up = (294, 345);
......
......@@ -266,11 +266,6 @@ fhi_72 = {
worker_cores = (2);
ru_addr = ("e8:c7:4f:1e:c7:11", "e8:c7:4f:1e:c7:11");
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (285, 429);
T2a_cp_ul = (285, 429);
T2a_up = (125, 428);
Ta3 = (130, 170);
T1a_cp_dl = (285, 429);
T1a_cp_ul = (285, 429);
T1a_up = (96, 196);
......
......@@ -252,11 +252,6 @@ fhi_72 = {
ru_addr = ("00:e0:0c:00:ae:06", "00:e0:0c:00:ae:06");
mtu = 9000;
fh_config = ({
Tadv_cp_dl = 125;
T2a_cp_dl = (285, 429);
T2a_cp_ul = (285, 429);
T2a_up = (125, 428);
Ta3 = (130, 170);
T1a_cp_dl = (285, 470);
T1a_cp_ul = (285, 429);
T1a_up = (125, 350);
......
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