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OpenXG
OpenXG-RAN
Commits
4ed939e4
Commit
4ed939e4
authored
Nov 22, 2024
by
Teodora
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Correct CI VVDN 4x4 100MHz config file
parent
6a810f15
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1
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19 additions
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32 deletions
+19
-32
ci-scripts/conf_files/gnb.sa.band77.273prb.fhi72.4x4-vvdn.conf
...ripts/conf_files/gnb.sa.band77.273prb.fhi72.4x4-vvdn.conf
+19
-32
No files found.
ci-scripts/conf_files/gnb.sa.band77.273prb.fhi72.4x4-vvdn.conf
View file @
4ed939e4
...
...
@@ -13,7 +13,6 @@ gNBs =
tracking_area_code
=
1
;
plmn_list
= ({
mcc
=
208
;
mnc
=
97
;
mnc_length
=
2
;
snssaiList
= ( {
sst
=
1
; }); });
//
nr_cellid
=
12345678
L
;
nr_cellid
=
1
;
//////////
Physical
parameters
:
...
...
@@ -23,7 +22,7 @@ gNBs =
maxMIMO_layers
=
2
;
pusch_AntennaPorts
=
4
;
do_CSIRS
=
1
;
do_SRS
=
0
;
do_SRS
=
0
;
pdcch_ConfigSIB1
= (
{
...
...
@@ -38,10 +37,11 @@ gNBs =
physCellId
=
0
;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3450.72 MHz (center frequency)
# center frequency = 3999.36 MHz
# selected SSB frequency = 3999.36 MHz
absoluteFrequencySSB
=
666624
;
dl_frequencyBand
=
77
;
#
this is 3401.58
MHz
#
frequency point A = 3950.22
MHz
dl_absoluteFrequencyPointA
=
663348
;
#scs-SpecificCarrierList
dl_offstToCarrier
=
0
;
...
...
@@ -186,8 +186,8 @@ MACRLCs = (
tr_n_preference
=
"local_RRC"
;
pusch_TargetSNRx10
=
180
;
pucch_TargetSNRx10
=
230
;
ul_bler_target_upper
=
.
35
;
ul_bler_target_lower
=
.
15
;
ul_bler_target_upper
=
.
35
;
ul_bler_target_lower
=
.
15
;
pusch_FailureThres
=
100
;
}
);
...
...
@@ -211,7 +211,7 @@ RUs = (
local_rf
=
"no"
;
nb_tx
=
4
;
nb_rx
=
4
;
att_tx
=
0
att_tx
=
0
;
att_rx
=
0
;
bands
= [
77
];
max_pdschReferenceSignalPower
= -
27
;
...
...
@@ -220,21 +220,11 @@ RUs = (
eNB_instances
= [
0
];
ru_thread_core
=
5
;
sl_ahead
=
5
;
clock_src
=
"internal"
;
tr_preference
=
"raw_if4p5"
;
# important: activate FHI7.2
do_precoding
=
0
;
# needs to match O-RU configuration
do_precoding
=
0
;
# needs to match O-RU configuration
}
);
rfsimulator
:
{
serveraddr
=
"server"
;
serverport
=
"4043"
;
options
= ();
#("saviq"); or/and "chanmod"
modelname
=
"AWGN"
;
IQfile
=
"/tmp/rfsimulator.iqs"
;
};
security
= {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
...
...
@@ -252,7 +242,8 @@ security = {
drb_integrity
=
"no"
;
};
log_config
: {
log_config
:
{
global_log_level
=
"info"
;
hw_log_level
=
"info"
;
phy_log_level
=
"info"
;
...
...
@@ -269,25 +260,21 @@ fhi_72 = {
system_core
=
0
;
io_core
=
1
;
worker_cores
= (
2
);
du_addr
= (
"76:76:64:6e:00:01"
,
"76:76:64:6e:00:01"
);
ru_addr
= (
"98:ae:71:01:c5:eb"
,
"98:ae:71:01:c5:eb"
);
mtu
=
9
216
;
# check if xran uses this properly
mtu
=
9
600
;
fh_config
= ({
Tadv_cp_dl
=
125
;
T2a_cp_dl
= (
285
,
429
);
# (min, max)
T2a_cp_ul
= (
285
,
429
);
# (min, max)
T2a_up
= (
125
,
428
);
# (min, max)
Ta3
= (
130
,
170
);
# (min, max)
T1a_cp_dl
= (
285
,
470
);
# (min, max)
T1a_cp_ul
= (
285
,
429
);
# (min, max)
T1a_up
= (
125
,
350
);
# (min, max)
Ta4
= (
110
,
180
);
# (min, max)
T2a_cp_dl
= (
285
,
429
);
T2a_cp_ul
= (
285
,
429
);
T2a_up
= (
125
,
428
);
Ta3
= (
130
,
170
);
T1a_cp_dl
= (
285
,
470
);
T1a_cp_ul
= (
285
,
429
);
T1a_up
= (
125
,
350
);
Ta4
= (
110
,
180
);
ru_config
= {
iq_width
=
9
;
iq_width_prach
=
9
;
};
prach_config
= {
eAxC_offset
=
4
;
};
});
};
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