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OpenXG-RAN
Commit caeedc04 authored by YanKuo's avatar YanKuo
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add OXGRF support

parent 102965a6
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Showing with 6619 additions and 11 deletions
cmake_targets/build_oai
View file @ caeedc04
......@@ -89,7 +89,7 @@ Options:
--UE-conf-nvram [configuration file]
Specify conf_nvram_path (default \"$conf_nvram_path\")
-w | --hardware
USRP, BLADERF, LMSSDR, IRIS, SIMU, AW2SORI, AERIAL, None (Default)
USRP, BLADERF, LMSSDR, IRIS, SIMU, AW2SORI, AERIAL, OXGRF, None (Default)
Adds this RF board support (in external packages installation and in compilation)
-t | --transport
Selects the transport protocol type, options: None, Ethernet, oran_fhlib_5g, oran_fhlib_5g_mplane, WLS
......@@ -246,7 +246,7 @@ function main() {
shift 2;;
-w | --hardware)
case "$2" in
"USRP" | "BLADERF" | "LMSSDR" | "IRIS")
"USRP" | "BLADERF" | "LMSSDR" | "IRIS" | "OXGRF")
HW="OAI_"$2
TARGET_LIST="$TARGET_LIST oai_${2,,}devif" # ,, makes lowercase
CMAKE_CMD="$CMAKE_CMD -DOAI_$2=ON"
......@@ -431,6 +431,10 @@ function main() {
flash_firmware_bladerf
fi
fi
if [ "$HW" == "OAI_OXGRF" ] ; then
echo_info "installing packages for OXGRF support"
#check_install_oxgrf_driver
fi
if [ "$HW" == "OAI_IRIS" ] ; then
echo_info "installing packages for IRIS support"
check_install_soapy
......
cmake_targets/tools/build_helper
View file @ caeedc04
......@@ -330,6 +330,34 @@ install_usrp_uhd_driver() {
fi
}
check_install_oxgrf_driver() {
#if modinfo riffa > /dev/null 2>&1
if modinfo xdma > /dev/null 2>&1
then
echo_success "OXGRF driver has loaded."
else
git clone https://github.com/v3best/riffa /tmp/riffa
if [ $? -ne 0 ]; then
echo_fatal "OXGRF driver download failed, please check your net connection."
else
cd /tmp/riffa/driver/linux
make && $SUDO make install
echo_success "OXGRF driver install success, please restart your PC later."
fi
git clone https://github.com/v3best/liboxgrf /tmp/liboxgrf
if [ $? -ne 0 ]; then
echo_fatal "OXGRF API download failed, please check your net connection."
else
cd /tmp/liboxgrf
mkdir build
cd build
cmake ../
make && $SUDO make install && $SUDO ldconfig
echo_success "OXGRF API install success, please restart your PC later."
fi
fi
}
install_bladerf_driver_from_source(){
echo_info "\nInstalling BladeRF driver from sources."
cd /tmp
......@@ -566,8 +594,9 @@ install_asn1c_from_source(){
$SUDO $INSTALLER -y install bison flex
$SUDO rm -rf /tmp/asn1c
# GIT_SSL_NO_VERIFY=true git clone https://gitlab.eurecom.fr/oai/asn1c.git /tmp/asn1c
git clone https://github.com/mouse07410/asn1c /tmp/asn1c
cd /tmp/asn1c
#git clone https://github.com/mouse07410/asn1c /tmp/asn1c
git clone https://gitee.com/chloeely/asn1c.git /tmp/asn1c
cd /tmp/asn1c
#git checkout vlm_master
# hotfix: current vlm_master (5fa129cf3161da9ff2d67341e6277e818c0f5d6a)
# breaks F1, NG, so use the one before.
......@@ -589,8 +618,9 @@ install_simde_from_source(){
echo_info "\nInstalling SIMDE from source without test cases (header files only)"
cd /tmp
$SUDO rm -rf /tmp/simde
git clone https://github.com/simd-everywhere/simde-no-tests.git /tmp/simde
cd /tmp/simde
# git clone https://github.com/simd-everywhere/simde-no-tests.git /tmp/simde
git clone https://gitee.com/chloeely/simde.git /tmp/simde
cd /tmp/simde
# we can specify a given version of SIMDE (sha-one or tag)
if [[ -v SIMDE_VERSION ]]; then
git checkout -f $SIMDE_VERSION
......@@ -604,6 +634,26 @@ install_simde_from_source(){
$SUDO \cp -rv ../simde /usr/include
}
install_oxgrf_from_source(){
echo_info "\nInstalling OXGRF from source without test cases (header files only)"
if [ ! -f /usr/local/include/oxgrf_api_ss.h ]; then
cp $OPENAIR_DIR/radio/OXGRF/oxgrf_api_ss.h /usr/local/include
$SUDO chmod +x /usr/local/include/oxgrf_api_ss.h
echo "oxgrf_api_ss.h installed successfully"
else
echo "oxgrf_api_ss.h is already existed"
fi
if [ ! -f /usr/local/include/liboxgrf_ss.so ]; then
cp $OPENAIR_DIR/radio/OXGRF/liboxgrf_ss.so /usr/local/lib
$SUDO chmod +x /usr/local/lib/liboxgrf_ss.so
$SUDO ldconfig /usr/local/lib
echo "liboxgrf_ss.so installed successfully"
else
echo "liboxgrf_ss.so is already existed"
fi
}
install_lttng() {
if [[ "$OS_DISTRO" != "ubuntu" ]]; then
echo_info "LTTng is supported only for ubuntu at the moment."
......
executables/lte-ru.c
View file @ caeedc04
......@@ -765,7 +765,7 @@ void tx_rf(RU_t *ru,
VCD_SIGNAL_DUMPER_DUMP_FUNCTION_BY_NAME(VCD_SIGNAL_DUMPER_FUNCTIONS_TRX_WRITE, 0);
// AssertFatal(txs == siglen+sf_extension,"TX : Timeout (sent %d/%d)\n",txs, siglen);
if (usrp_tx_thread == 0 && (txs != siglen + sf_extension)
if (usrp_tx_thread == 0 && oxgrf_tx_thread == 0 && (txs != siglen + sf_extension)
&& (late_control == STATE_BURST_NORMAL)) { /* add fail safe for late command */
late_control = STATE_BURST_TERMINATE;
LOG_E(PHY, "TX : Timeout (sent %d/%d) state =%d\n", txs, siglen, late_control);
......@@ -1588,7 +1588,7 @@ static void *ru_thread( void *param ) {
pthread_cond_signal(&proc->cond_FH1);
AssertFatal((ret=pthread_mutex_unlock(&proc->mutex_FH1))==0,"mutex_unlock returns %d\n",ret);
if(usrp_tx_thread == 1){
if(usrp_tx_thread == 1 || oxgrf_tx_thread == 1){
if (ru->start_write_thread){
if(ru->start_write_thread(ru) != 0){
LOG_E(HW,"Could not start tx write thread\n");
......
executables/lte-softmodem.h
View file @ caeedc04
......@@ -71,6 +71,7 @@
#define CONFIG_HLP_PRB "Set the PRB, valid values: 6, 25, 50, 100 \n"
#define CONFIG_HLP_DLSHIFT "dynamic shift for LLR compuation for TM3/4 (default 0)\n"
#define CONFIG_HLP_USRP_ARGS "set the arguments to identify USRP (same syntax as in UHD)\n"
#define CONFIG_HLP_OXGRF_ARGS "set the arguments to identify OXGRF\n"
#define CONFIG_HLP_DMAMAP "use DMA memory mapping\n"
#define CONFIG_HLP_TDD "Set hardware to TDD mode (default: FDD). Used only with -U (otherwise set in config file).\n"
......@@ -94,6 +95,7 @@
{"r" , CONFIG_HLP_PRB, 0, .u8ptr=&(frame_parms[0]->N_RB_DL), .defintval=25, TYPE_UINT8, 0}, \
{"dlsch-demod-shift", CONFIG_HLP_DLSHIFT, 0, .iptr=(int32_t *)&dlsch_demod_shift, .defintval=0, TYPE_INT, 0}, \
{"usrp-args", CONFIG_HLP_USRP_ARGS, 0, .strptr=&usrp_args, .defstrval="type=b200",TYPE_STRING, 0}, \
{"oxgrf-args", CONFIG_HLP_OXGRF_ARGS, 0, .strptr=&oxgrf_args, .defstrval="dev=pciex:0",TYPE_STRING, 0}, \
{"mmapped-dma", CONFIG_HLP_DMAMAP, PARAMFLAG_BOOL, .uptr=&mmapped_dma, .defintval=0, TYPE_INT, 0}, \
{"T" , CONFIG_HLP_TDD, PARAMFLAG_BOOL, .iptr=&tddflag, .defintval=0, TYPE_INT, 0}, \
{"ue-idx-standalone", NULL, 0, .u16ptr=&ue_idx_standalone, .defuintval=0xFFFF, TYPE_UINT16, 0}, \
......@@ -129,6 +131,7 @@ extern double cpuf;
extern int numerology;
extern int usrp_tx_thread;
extern int oxgrf_tx_thread;
// In lte-enb.c
extern void stop_eNB(int);
......
executables/lte-uesoftmodem.c
View file @ caeedc04
......@@ -144,6 +144,8 @@ int transmission_mode=1;
char *usrp_args=NULL;
char *usrp_clksrc=NULL;
char *oxgrf_args=NULL;
THREAD_STRUCT thread_struct;
/* struct for ethernet specific parameters given in eNB conf file */
eth_params_t *eth_params;
......@@ -406,6 +408,7 @@ static void init_openair0(LTE_DL_FRAME_PARMS *frame_parms, int rxgain)
}
if (usrp_args) openair0_cfg[card].sdr_addrs = usrp_args;
if (oxgrf_args) openair0_cfg[card].sdr_addrs = oxgrf_args;
}
}
......
executables/nr-ru.c
View file @ caeedc04
......@@ -1121,7 +1121,7 @@ void *ru_thread(void *param)
LOG_I(PHY, "RU %d RF started cpu_meas_enabled %d\n", ru->idx, cpu_meas_enabled);
// start trx write thread
if (usrp_tx_thread == 1) {
if (usrp_tx_thread == 1 || oxgrf_tx_thread == 1) {
if (ru->start_write_thread) {
if (ru->start_write_thread(ru) != 0) {
LOG_E(HW, "Could not start tx write thread\n");
......
executables/nr-softmodem-common.h
View file @ caeedc04
......@@ -84,12 +84,15 @@
#define CONFIG_HLP_NUMEROLOGY "adding numerology for 5G\n"
#define CONFIG_HLP_EMULATE_RF "Emulated RF enabled(disable by defult)\n"
#define CONFIG_HLP_OXGRF_THREAD "having extra thead for oxgrf tx\n"
#define CONFIG_HLP_USRP_THREAD "having extra thead for usrp tx\n"
#define CONFIG_HLP_DISABLNBIOT "disable nb-iot, even if defined in config\n"
#define CONFIG_HLP_USRP_ARGS "set the arguments to identify USRP (same syntax as in UHD)\n"
#define CONFIG_HLP_TX_SUBDEV "set the arguments to select tx_subdev (same syntax as in UHD)\n"
#define CONFIG_HLP_RX_SUBDEV "set the arguments to select rx_subdev (same syntax as in UHD)\n"
#define CONFIG_HLP_OXGRF_ARGS "set the arguments to identify OXGRF\n"
#define CONFIG_HLP_FLOG "Enable online log \n"
#define CONFIG_HLP_LOGL "Set the global log level, valid options: (4:trace, 3:debug, 2:info, 1:warn, (0:error))\n"
#define CONFIG_HLP_LOGV "Set the global log verbosity \n"
......@@ -134,5 +137,6 @@ extern double cpuf;
extern int numerology;
extern int usrp_tx_thread;
extern int oxgrf_tx_thread;
void wait_gNBs(void);
#endif
executables/nr-softmodem.h
View file @ caeedc04
......@@ -25,6 +25,7 @@
{"T" , CONFIG_HLP_ULBW_PHYTEST, 0, .uptr=&target_ul_bw, .defintval=0, TYPE_UINT, 0}, \
{"D" , CONFIG_HLP_DLBM_PHYTEST, 0, .u64ptr=&dlsch_slot_bitmap, .defintval=0, TYPE_UINT64, 0}, \
{"U" , CONFIG_HLP_ULBM_PHYTEST, 0, .u64ptr=&ulsch_slot_bitmap, .defintval=0, TYPE_UINT64, 0}, \
{"sdr-tx-thread-config", CONFIG_HLP_OXGRF_THREAD, 0, .iptr=&oxgrf_tx_thread, .defstrval=0, TYPE_INT, 0}, \
{"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, .iptr=&usrp_tx_thread, .defstrval=0, TYPE_INT, 0}, \
{"uecap_file", CONFIG_HLP_UECAP_FILE, 0, .strptr=&uecap_file, .defstrval="./uecap_ports1.xml", TYPE_STRING, 0}, \
}
......
executables/nr-ue.c
View file @ caeedc04
......@@ -763,7 +763,7 @@ void *UE_thread(void *arg)
UE->is_synchronized = 0;
int tmp2 = UE->rfdevice.trx_start_func(&UE->rfdevice);
AssertFatal(tmp2 == 0, "Could not start the device\n");
if (usrp_tx_thread == 1)
if (usrp_tx_thread == 1 || oxgrf_tx_thread == 1)
UE->rfdevice.trx_write_init(&UE->rfdevice);
InitSinLUT();
......
executables/nr-uesoftmodem.c
View file @ caeedc04
......@@ -279,6 +279,8 @@ void init_openair0(PHY_VARS_NR_UE *ue)
cfg->tx_subdev = get_nrUE_params()->tx_subdev;
if (get_nrUE_params()->rx_subdev)
cfg->rx_subdev = get_nrUE_params()->rx_subdev;
if (get_nrUE_params()->oxgrf_args)
cfg->sdr_addrs = get_nrUE_params()->oxgrf_args;
}
}
......
executables/nr-uesoftmodem.h
View file @ caeedc04
......@@ -46,6 +46,7 @@ extern uint16_t ue_id_g;
// clang-format off
#define CMDLINE_NRUEPARAMS_DESC { \
{"usrp-args", CONFIG_HLP_USRP_ARGS, 0, .strptr=&nrUE_params.usrp_args, .defstrval="type=b200", TYPE_STRING, 0}, \
{"oxgrf-args", CONFIG_HLP_OXGRF_ARGS, 0, .strptr=&nrUE_params.oxgrf_args, .defstrval="dev=pciex:0", TYPE_STRING, 0}, \
{"tx_subdev", CONFIG_HLP_TX_SUBDEV, 0, .strptr=&nrUE_params.tx_subdev, .defstrval=NULL, TYPE_STRING, 0}, \
{"rx_subdev", CONFIG_HLP_RX_SUBDEV, 0, .strptr=&nrUE_params.rx_subdev, .defstrval=NULL, TYPE_STRING, 0}, \
{"dlsch-parallel", CONFIG_HLP_DLSCH_PARA, 0, .u8ptr=NULL, .defintval=0, TYPE_UINT8, 0}, \
......@@ -113,6 +114,7 @@ typedef struct {
int cont_fo_comp;
int agc;
char *usrp_args;
char *oxgrf_args;
char *tx_subdev;
char *rx_subdev;
char *reconfig_file;
......
executables/softmodem-common.c
View file @ caeedc04
......@@ -44,6 +44,7 @@
char *parallel_config=NULL;
char *worker_config=NULL;
int usrp_tx_thread = 0;
int oxgrf_tx_thread = 0;
uint8_t nfapi_mode=0;
static struct timespec start;
......
executables/softmodem-common.h
View file @ caeedc04
......@@ -99,10 +99,12 @@ extern "C"
#define CONFIG_HLP_PARALLEL_CMD "three config for level of parallelism 'PARALLEL_SINGLE_THREAD', 'PARALLEL_RU_L1_SPLIT', or 'PARALLEL_RU_L1_TRX_SPLIT'\n"
#define CONFIG_HLP_WORKER_CMD "two option for worker 'WORKER_DISABLE' or 'WORKER_ENABLE'\n"
#define CONFIG_HLP_USRP_THREAD "having extra thead for usrp tx\n"
#define CONFIG_HLP_OXGRF_THREAD "having extra thead for oxgrf tx\n"
#define CONFIG_HLP_NOS1 "Disable s1 interface\n"
#define CONFIG_HLP_RFSIM "Run in rf simulator mode\n"
#define CONFIG_HLP_DISABLNBIOT "disable nb-iot, even if defined in config\n"
#define CONFIG_HLP_OXGRF_THREAD "having extra thead for oxgrf tx\n"
#define CONFIG_HLP_USRP_THREAD "having extra thead for usrp tx\n"
#define CONFIG_HLP_NFAPI "Change the nFAPI mode for NR 'MONOLITHIC', 'PNF', 'VNF', 'AERIAL','UE_STUB_PNF','UE_STUB_OFFNET','STANDALONE_PNF'\n"
#define CONFIG_HLP_CONTINUOUS_TX "perform continuous transmission, even in TDD mode (to work around USRP issues)\n"
......@@ -142,6 +144,7 @@ extern "C"
#define DEFAULT_RFCONFIG_FILE "/usr/local/etc/syriq/ue.band7.tm1.PRB100.NR40.dat";
extern int oxgrf_tx_thread;
extern int usrp_tx_thread;
// clang-format off
#define CMDLINE_PARAMS_DESC { \
......@@ -169,6 +172,7 @@ extern int usrp_tx_thread;
{"chest-time", CONFIG_HLP_CHESTTIME, 0, .iptr=&CHEST_TIME, .defintval=0, TYPE_INT, 0}, \
{"nsa", CONFIG_HLP_NSA, PARAMFLAG_BOOL, .iptr=&NSA, .defintval=0, TYPE_INT, 0}, \
{"node-number", NULL, 0, .u16ptr=&NODE_NUMBER, .defuintval=0, TYPE_UINT16, 0}, \
{"sdr-tx-thread-config", CONFIG_HLP_OXGRF_THREAD, 0, .iptr=&oxgrf_tx_thread, .defstrval=0, TYPE_INT, 0}, \
{"usrp-tx-thread-config", CONFIG_HLP_USRP_THREAD, 0, .iptr=&usrp_tx_thread, .defstrval=0, TYPE_INT, 0}, \
{"nfapi", CONFIG_HLP_NFAPI, 0, .strptr=NULL, .defstrval="MONOLITHIC", TYPE_STRING, 0}, \
{"non-stop", CONFIG_HLP_NONSTOP, PARAMFLAG_BOOL, .iptr=&NON_STOP, .defintval=0, TYPE_INT, 0}, \
......@@ -211,6 +215,7 @@ extern int usrp_tx_thread;
{ .s5 = { NULL } }, \
{ .s5 = { NULL } }, \
{ .s5 = { NULL } }, \
{ .s5 = { NULL } }, \
{ .s3a = { config_checkstr_assign_integer, \
{"MONOLITHIC", "PNF", "VNF", "AERIAL","UE_STUB_PNF","UE_STUB_OFFNET","STANDALONE_PNF"}, \
{NFAPI_MONOLITHIC, NFAPI_MODE_PNF, NFAPI_MODE_VNF, NFAPI_MODE_AERIAL,NFAPI_UE_STUB_PNF,NFAPI_UE_STUB_OFFNET,NFAPI_MODE_STANDALONE_PNF}, \
......@@ -346,6 +351,7 @@ char *get_softmodem_function(void);
void set_softmodem_sighandler(void);
extern uint64_t downlink_frequency[MAX_NUM_CCs][4];
extern int32_t uplink_frequency_offset[MAX_NUM_CCs][4];
extern int oxgrf_tx_thread;
extern int usrp_tx_thread;
extern int sf_ahead;
extern int oai_exit;
......
openair1/PHY/impl_defs_top.h
View file @ caeedc04
......@@ -43,6 +43,7 @@
* @defgroup _GENERIC_PHY_RF_INTERFACE_ Generic PHY - RF Interface
* @defgroup _USRP_PHY_RF_INTERFACE_ PHY - USRP RF Interface
* @defgroup _BLADERF_PHY_RF_INTERFACE_ PHY - BLADERF RF Interface
* @defgroup _OXGRF_PHY_RF_INTERFACE_ PHY - OXGRF RF Interface
* @defgroup _LMSSDR_PHY_RF_INTERFACE_ PHY - LMSSDR RF Interface
* @}
* @}
......
radio/CMakeLists.txt
View file @ caeedc04
......@@ -47,3 +47,8 @@ add_boolean_option(OAI_RF_EMULATOR ON "Activate OAI's RF emulator" OFF)
if(OAI_RF_EMULATOR)
add_subdirectory(emulator)
endif()
add_boolean_option(OAI_OXGRF OFF "Activate OAI's OXGRF driver" OFF)
if(OAI_OXGRF)
add_subdirectory(OXGRF)
endif()
radio/COMMON/common_lib.c
View file @ caeedc04
......@@ -45,7 +45,7 @@
#define MAX_GAP 100ULL
const char *const devtype_names[MAX_RF_DEV_TYPE] =
{"", "USRP B200", "USRP X300", "USRP N300", "USRP X400", "BLADERF", "LMSSDR", "IRIS", "No HW", "UEDv2", "RFSIMULATOR"};
{"", "USRP B200", "USRP X300", "USRP N300", "USRP X400", "BLADERF", "OXGRF", "LMSSDR", "IRIS", "No HW", "UEDv2", "RFSIMULATOR"};
const char *get_devname(int devtype) {
if (devtype < MAX_RF_DEV_TYPE && devtype !=MIN_RF_DEV_TYPE )
......
radio/COMMON/common_lib.h
View file @ caeedc04
......@@ -93,6 +93,8 @@ typedef enum {
USRP_X400_DEV,
/*!\brief device is BLADE RF*/
BLADERF_DEV,
/*!\brief device is OXGRF pcie*/
OXGRF_DEV,
/*!\brief device is LMSSDR (SoDeRa)*/
LMSSDR_DEV,
/*!\brief device is Iris */
......
radio/OXGRF/CMakeLists.txt 0 → 100644
View file @ caeedc04
find_library(oxgrf_ss NAMES oxgrf_ss)
add_library(oai_oxgrfdevif MODULE oxgrf_lib.c)
target_link_libraries(oai_oxgrfdevif PRIVATE oxgrf_ss)
target_link_libraries(oai_oxgrfdevif PRIVATE UTIL)
set_target_properties(oai_oxgrfdevif PROPERTIES LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
add_custom_command(TARGET oai_oxgrfdevif POST_BUILD
COMMAND ${CMAKE_COMMAND} -E create_symlink liboai_oxgrfdevif.so liboai_device.so
WORKING_DIRECTORY ${CMAKE_BINARY_DIR})
radio/OXGRF/oxgrf_api_ss.h 0 → 100755
View file @ caeedc04
/*
* oxgrf_api_ss.h
*
* Created on: 2016/5/9
* Author: Eric
*/
#ifndef __OXGRF_SS_API_H__
#define __OXGRF_SS_API_H__
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <stdbool.h>
#include "platform_types.h"
#if defined(__WINDOWS_) || defined(_WIN32)
#define DLLEXPORT __declspec(dllexport)
#define OXGRFCALL __cdecl
#else
#define DLLEXPORT
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef struct oxgrf_transport OXGRF_TRANSPORT;
typedef struct oxgrf_device_descriptor {
int32_t id;
int32_t status;
uint8_t nchips;
uint8_t nsubdev;
OXGRF_TRANSPORT *trans;
}OXGRF_DESCRIPTOR;
typedef enum {
TX1_CHANNEL = 1,
TX2_CHANNEL = 2,
TX3_CHANNEL = 3,
TX4_CHANNEL = 4,
TX5_CHANNEL = 5,
TX6_CHANNEL = 6,
TX7_CHANNEL = 7,
TX8_CHANNEL = 8,
}RF_TX_CHANNEL;
typedef enum {
RX1_CHANNEL = 1,
RX2_CHANNEL = 2,
RX3_CHANNEL = 3,
RX4_CHANNEL = 4,
RX5_CHANNEL = 5,
RX6_CHANNEL = 6,
RX7_CHANNEL = 7,
RX8_CHANNEL = 8,
}RF_RX_CHANNEL;
typedef enum rf_gain_ctrl_mode {
RF_GAIN_MGC,
RF_GAIN_FASTATTACK_AGC,
RF_GAIN_SLOWATTACK_AGC,
}RF_GAIN_CTRL_MODE;
typedef enum ref_select {
INTERNAL_REFERENCE = 0,
EXTERNAL_REFERENCE,
}REF_SELECT;
typedef enum vco_cal_select {
ADF4001 = 0,
AUXDAC1,
}VCO_CAL_SELECT;
/*/typedef enum duplex_select {
TDD = 0,
FDD,
}DUPLEX_SELECT;
*/
typedef frame_type_t DUPLEX_SELECT;
#define TO_OXGRF_OLD_VALUE(mode) ((mode) == TDD ? 0 : 1)
typedef enum trx_switch {
RX = 0,
TX,
}TRX_SWITCH;
typedef enum {
TX_CHANNEL_TIMEOUT = 29,
RX_CHANNEL_TIMEOUT = 30,
TX_CHANNEL_UNDERFLOW = 31,
RX_CHANNEL_OVERFLOW = 32,
TX_CHANNEL_COUNT = 33,
RX_CHANNEL_COUNT = 34,
}CHANNEL_EVENT;
typedef enum pps_enable {
PPS_INTERNAL_EN,
PPS_GPS_EN,
PPS_EXTERNAL_EN,
}PPSModeEnum;
typedef enum device_configuration {
SingleSubDevSingleRF = 0x1010,
SingleSubDevDualRF = 0x1020,
SingleSubDevQuadRF = 0x1040,
DualSubDevDualRF = 0x2011,
DualSubDevTriple1RF = 0x2012,
DualSubDevTriple2RF = 0x2021,
DualSubDevQuadRF = 0x2022,
DualSubDevOctoRF = 0x2044,
NULLSubDevNULLRF = 0,
}DEV_CFG;
typedef struct {
uint8_t receiver_mode;
uint8_t disciplining_mode;
uint16_t minor_alarms;
uint8_t gnss_decoding_status;
uint8_t disciplining_activity;
uint8_t pps_indication;
uint8_t pps_reference;
} GPS_STATUS;
typedef struct {
uint8_t second;
uint8_t minute;
uint8_t hour;
uint8_t day;
uint8_t month;
uint32_t year;
} TIME_24H;
/*********************************************************************************************************************************************************/
DLLEXPORT uint64_t oxgrf_ticksToTimeNs (const uint64_t ticks, const double rate);
DLLEXPORT uint64_t oxgrf_timeNsToTicks (const uint64_t timeNs, const double rate);
/*********************************************************************************************************************************************************/
DLLEXPORT OXGRF_DESCRIPTOR *oxgrf_open_device (const char *url);
DLLEXPORT int32_t oxgrf_close_device (OXGRF_DESCRIPTOR *oxgrf);
DLLEXPORT int32_t oxgrf_get_device_configuration (OXGRF_DESCRIPTOR* oxgrf, DEV_CFG* cfg);
DLLEXPORT int32_t oxgrf_get_firmware_version(OXGRF_DESCRIPTOR* oxgrf, uint32_t* version);
DLLEXPORT int32_t oxgrf_get_model_version(OXGRF_DESCRIPTOR* oxgrf, uint32_t* version);
/*********************************************************************************************************************************************************/
DLLEXPORT int32_t oxgrf_get_gps_status (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, GPS_STATUS *g_status);
DLLEXPORT int32_t oxgrf_get_utc (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, TIME_24H *time);
DLLEXPORT int32_t oxgrf_get_xyz (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, double *longtitude, double *latitude, double *altitude);
DLLEXPORT int32_t oxgrf_get_sampling_freq_range (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint32_t *sampling_freq_hz_max, uint32_t *sampling_freq_hz_min);
DLLEXPORT int32_t oxgrf_get_rx_gain_range (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint32_t *gain_db_max, uint32_t *gain_db_min);
DLLEXPORT int32_t oxgrf_get_tx_gain_range (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint32_t *gain_db_max, uint32_t *gain_db_min);
DLLEXPORT int32_t oxgrf_get_rx_freq_range (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint64_t *lo_freq_hz_max, uint64_t *lo_freq_hz_min);
DLLEXPORT int32_t oxgrf_get_tx_freq_range (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint64_t *lo_freq_hz_max, uint64_t *lo_freq_hz_min);
/*********************************************************************************************************************************************************/
/* Get current TX LO frequency. */
DLLEXPORT int32_t oxgrf_get_tx_lo_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint64_t *lo_freq_hz);
/* Get current TX sampling frequency. */
DLLEXPORT int32_t oxgrf_get_tx_sampling_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t *sampling_freq_hz);
/* Get the TX RF bandwidth. */
DLLEXPORT int32_t oxgrf_get_tx_rf_bandwidth (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t *bandwidth_hz);
/* Get current transmit attenuation for the selected channel. */
DLLEXPORT int32_t oxgrf_get_tx1_attenuation (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t *attenuation_mdb);
/* Get current transmit attenuation for the selected channel. */
DLLEXPORT int32_t oxgrf_get_tx2_attenuation (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t *attenuation_mdb);
/* Get current RX LO frequency. */
DLLEXPORT int32_t oxgrf_get_rx_lo_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint64_t *lo_freq_hz);
/* Get the RX RF bandwidth. */
DLLEXPORT int32_t oxgrf_get_rx_rf_bandwidth (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t *bandwidth_hz);
/* Get the gain control mode for the selected channel. */
DLLEXPORT int32_t oxgrf_get_rx1_gain_control_mode (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, RF_GAIN_CTRL_MODE *gc_mode);
/* Get the gain control mode for the selected channel. */
DLLEXPORT int32_t oxgrf_get_rx2_gain_control_mode (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, RF_GAIN_CTRL_MODE *gc_mode);
/* Get current receive RF gain for the selected channel. */
DLLEXPORT int32_t oxgrf_get_rx1_rf_gain (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, int32_t *gain_db);
/* Get current receive RF gain for the selected channel. */
DLLEXPORT int32_t oxgrf_get_rx2_rf_gain (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, int32_t *gain_db);
DLLEXPORT int32_t oxgrf_get_rx1_rssi (OXGRF_DESCRIPTOR* oxgrf, uint8_t rf_id, int32_t* rssi);
DLLEXPORT int32_t oxgrf_get_rx2_rssi (OXGRF_DESCRIPTOR* oxgrf, uint8_t rf_id, int32_t* rssi);
/*********************************************************************************************************************************************************/
/* Set the RX LO frequency. */
DLLEXPORT int32_t oxgrf_set_rx_lo_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint64_t lo_freq_hz);
/* Set the RX RF bandwidth. */
DLLEXPORT int32_t oxgrf_set_rx_rf_bandwidth (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t bandwidth_hz);
/* Set the RX sampling frequency. */
DLLEXPORT int32_t oxgrf_set_rx_sampling_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t sampling_freq_hz);
/* Set the gain control mode for the selected channel. */
DLLEXPORT int32_t oxgrf_set_rx1_gain_control_mode (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, RF_GAIN_CTRL_MODE gc_mode);
DLLEXPORT int32_t oxgrf_set_rx2_gain_control_mode (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, RF_GAIN_CTRL_MODE gc_mode);
/* Set the receive RF gain for the selected channel. */
DLLEXPORT int32_t oxgrf_set_rx1_rf_gain (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, int32_t gain_db);
/* Set the receive RF gain for the selected channel. */
DLLEXPORT int32_t oxgrf_set_rx2_rf_gain (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, int32_t gain_db);
DLLEXPORT int32_t oxgrf_set_rx_fir_en_dis (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint8_t enable);
/* Set the TX LO frequency. */
DLLEXPORT int32_t oxgrf_set_tx_lo_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint64_t lo_freq_hz);
/* Set the TX RF bandwidth. */
DLLEXPORT int32_t oxgrf_set_tx_rf_bandwidth (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t bandwidth_hz);
/* Set the TX sampling frequency. */
DLLEXPORT int32_t oxgrf_set_tx_sampling_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t sampling_freq_hz);
/* Set the transmit attenuation for the selected channel. */
DLLEXPORT int32_t oxgrf_set_tx1_attenuation (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t attenuation_mdb);
/* Set the transmit attenuation for the selected channel. */
DLLEXPORT int32_t oxgrf_set_tx2_attenuation (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t attenuation_mdb);
/* Set the transmit abs power for the selected channel. */
DLLEXPORT int32_t oxgrf_set_tx1_abs_power (OXGRF_DESCRIPTOR* oxgrf, uint8_t rf_id, int32_t abs_power);
/* Set the transmit abs power for the selected channel. */
DLLEXPORT int32_t oxgrf_set_tx2_abs_power (OXGRF_DESCRIPTOR* oxgrf, uint8_t rf_id, int32_t abs_power);
DLLEXPORT int32_t oxgrf_set_tx_fir_en_dis (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint8_t status);
/*********************************************************************************************************************************************************/
DLLEXPORT int32_t oxgrf_get_rfchip_reg (OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t reg, uint32_t *value);
DLLEXPORT int32_t oxgrf_set_rfchip_reg(OXGRF_DESCRIPTOR *oxgrf, uint8_t rf_id, uint32_t reg, uint32_t value);
/*********************************************************************************************************************************************************/
DLLEXPORT int32_t oxgrf_get_extend_cmd(OXGRF_DESCRIPTOR *oxgrf, uint8_t cmd_id, uint64_t *value, bool with_param);
DLLEXPORT int32_t oxgrf_set_extend_cmd(OXGRF_DESCRIPTOR *oxgrf, uint8_t cmd_id, uint64_t value);
/*********************************************************************************************************************************************************/
DLLEXPORT int32_t oxgrf_set_tx_lo_int_ext (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint8_t enable);
DLLEXPORT int32_t oxgrf_set_rx_lo_int_ext (OXGRF_DESCRIPTOR *oxgrf,uint8_t dev_id, uint8_t enable);
DLLEXPORT int32_t oxgrf_set_ext_lo_freq (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint64_t lo_freq_hz);
DLLEXPORT int32_t oxgrf_do_mcs (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint8_t enable);
DLLEXPORT int32_t oxgrf_set_ref_clock (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, REF_SELECT source);
DLLEXPORT int32_t oxgrf_set_vco_select (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, VCO_CAL_SELECT vco);
DLLEXPORT int32_t oxgrf_set_auxdac1 (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint32_t vol_mV);
DLLEXPORT int32_t oxgrf_set_duplex_select (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, DUPLEX_SELECT duplex);
DLLEXPORT int32_t oxgrf_set_rx_ant_enable (OXGRF_DESCRIPTOR* oxgrf, uint8_t dev_id, uint8_t enable);
DLLEXPORT int32_t oxgrf_tx_cyclic_enable (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint8_t enable);
DLLEXPORT int32_t oxgrf_set_trxsw_fpga_enable (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint8_t enable);
DLLEXPORT int32_t oxgrf_set_hwbuf_depth (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint32_t depth);
DLLEXPORT int32_t oxgrf_get_hwbuf_depth (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint32_t *depth);
DLLEXPORT int32_t oxgrf_set_pps_select (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, PPSModeEnum pps);
DLLEXPORT int32_t oxgrf_set_rxchannel_coef (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, RF_RX_CHANNEL channel, int16_t coef1, int16_t coef2);
DLLEXPORT int32_t oxgrf_enable_rxchannel_corr (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, RF_RX_CHANNEL channel, uint32_t enable);
DLLEXPORT int32_t oxgrf_set_txchannel_coef (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, RF_TX_CHANNEL channel, int16_t coef1, int16_t coef2);
DLLEXPORT int32_t oxgrf_enable_txchannel_corr (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, RF_TX_CHANNEL channel, uint32_t enable);
DLLEXPORT int32_t oxgrf_set_txchannel_ampcoef (OXGRF_DESCRIPTOR* oxgrf, uint8_t dev_id, RF_TX_CHANNEL channel, int16_t coef);
DLLEXPORT int32_t oxgrf_set_rxchannel_ampcoef (OXGRF_DESCRIPTOR* oxgrf, uint8_t dev_id, RF_RX_CHANNEL channel, int16_t coef);
/*********************************************************************************************************************************************************/
DLLEXPORT int32_t oxgrf_enable_timestamp (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint8_t enable);
DLLEXPORT int32_t oxgrf_read_timestamp (OXGRF_DESCRIPTOR *oxgrf, uint8_t dev_id, uint64_t *timestamp);
DLLEXPORT int32_t oxgrf_get_channel_event (OXGRF_DESCRIPTOR *oxgrf, CHANNEL_EVENT event, uint8_t channel, uint32_t *count);
/*********************************************************************************************************************************************************/
DLLEXPORT int32_t oxgrf_read_samples (OXGRF_DESCRIPTOR *oxgrf, void *buffer, uint32_t count, RF_RX_CHANNEL channel, uint64_t *timestamp);
DLLEXPORT int32_t oxgrf_read_samples_multiport (OXGRF_DESCRIPTOR *oxgrf, void **buffer, uint32_t count, uint8_t channel_mask, uint64_t *timestamp);
DLLEXPORT int32_t oxgrf_read_samples_multiport_Matlab (OXGRF_DESCRIPTOR *oxgrf, void *buffer, uint32_t count, uint8_t channel_mask, uint64_t *timestamp);
DLLEXPORT int32_t oxgrf_dump_samples_multiport (OXGRF_DESCRIPTOR *oxgrf, uint32_t count, uint8_t channel_mask, uint64_t* timestamp);
/* Since the data contains a 16-byte header, the size of the buffer should be greater than or equal to (count*4+16) Bytes*/
DLLEXPORT int32_t oxgrf_read_samples_zerocopy (OXGRF_DESCRIPTOR *oxgrf, void *buffer, uint32_t count, RF_RX_CHANNEL channel, uint64_t *timestamp);
DLLEXPORT int32_t oxgrf_write_samples (OXGRF_DESCRIPTOR *oxgrf, void *buffer, uint32_t count, RF_TX_CHANNEL channel, uint64_t timestamp);
DLLEXPORT int32_t oxgrf_write_samples2 (OXGRF_DESCRIPTOR *oxgrf, void *buffer, uint32_t count, RF_TX_CHANNEL channel, uint64_t timestamp, uint32_t flags);
DLLEXPORT int32_t oxgrf_write_samples_multiport (OXGRF_DESCRIPTOR *oxgrf, const void **buffer, uint32_t count, uint8_t channel_mask, uint64_t timestamp, uint32_t flags);
DLLEXPORT int32_t oxgrf_write_samples_multiport_Matlab (OXGRF_DESCRIPTOR *oxgrf, const void *buffer, uint32_t count, uint8_t channel_mask, uint64_t timestamp, uint32_t flags);
DLLEXPORT int32_t oxgrf_write_samples_zerocopy (OXGRF_DESCRIPTOR *oxgrf, void *buffer, uint32_t count, RF_TX_CHANNEL channel, uint64_t timestamp);
/*********************************************************************************************************************************************************/
DLLEXPORT void float_to_int16 (int16_t *dst, const float *src, int n, float mult);
DLLEXPORT void int16_to_float (float *dst, const int16_t *src, int len, float mult);
DLLEXPORT void int16_to_float_avx2(float *outputVector, const int16_t *inputVector, unsigned int num_points);
DLLEXPORT void float_to_int16_avx2(int16_t *outputVector, const float *inputVector, unsigned int num_points);
/*********************************************************************************************************************************************************/
#ifdef __cplusplus
}
#endif
#endif /* __OXGRF_SS_API_H__ */
radio/OXGRF/oxgrf_lib.c 0 → 100644
View file @ caeedc04
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/** oxgrf_lib.c
*
* Author: eric
* base on bladerf_lib.c
*/
#pragma GCC optimize(3, "Ofast", "inline", "fast-math", "unroll-loops")
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <inttypes.h>
#include "system.h"
#include <math.h>
#include "oxgrf_lib.h"
#include "rf_helper.h"
#include "common/utils/LOG/log.h"
/** @addtogroup _OXGRF_PHY_RF_INTERFACE_
* @{
*/
#include "openair1/PHY/sse_intrin.h"
#if defined (__AVX512BW__)
#include <simde/x86/avx512.h>
#endif
extern int oxgrf_tx_thread;
//! Number of OXGRF devices
int num_devices = 0;
static bool running = false;
#define BUFFER_SIZE (122880 * 100 * sizeof(int))
#define NCHAN_PER_DEV 4
static void *cache_buf[NCHAN_PER_DEV];
static void *iq_buf[NCHAN_PER_DEV];
static uint32_t remain = 0;
static uint32_t RX_MTU = 30720;
static uint8_t shift = 2;
static inline int channel_to_mask(int channel_count)
{
uint8_t ch_mask;
switch (channel_count) {
case 4:
ch_mask = 0xf;break;
case 3:
ch_mask = 0x7;break;
case 2:
ch_mask = 0x3;break;
case 1:
ch_mask = 0x1;break;
default:
ch_mask = 0x1;break;
}
return ch_mask;
}
static inline void rx_iq_shift(int16_t *dst, int16_t *src, ssize_t len, uint8_t shift)
{
int16_t *iq = src;
int16_t *iq_scale = dst;
#if defined(__x86_64__) || defined(__i386__)
#if defined(__AVX512BW__)
simde__m512i a, *b;
while (len >= 32) {
if ((((uintptr_t)iq) & 0x3F) == 0) {
a = *(simde__m512i *)&iq[0];
b = (simde__m512i *)&iq_scale[0];
*b = simde_mm512_srai_epi16(a, shift);
} else {
simde__m512i tmp = simde_mm512_loadu_si512((simde__m512i *)&iq[0]);
tmp = simde_mm512_srai_epi16(tmp, shift);
simde_mm512_storeu_si512((simde__m512i *)&iq_scale[0], tmp);
}
iq += 32;
iq_scale += 32;
len -= 32;
}
#else
simde__m256i a, *b;
while (len >= 16) {
if (((((uintptr_t)iq) & 0x1F) == 0)
&& ((((uintptr_t)iq_scale) & 0x1F) == 0)) {
a = *(simde__m256i *)&iq[0];
b = (simde__m256i *)&iq_scale[0];
*b = simde_mm256_srai_epi16(a, shift);
} else {
simde__m256i tmp = simde_mm256_loadu_si256((simde__m256i *)&iq[0]);
tmp = simde_mm256_srai_epi16(tmp, shift);
simde_mm256_storeu_si256((simde__m256i *)&iq_scale[0], tmp);
}
iq += 16;
iq_scale += 16;
len -= 16;
}
#endif
#elif defined(__arm__) || defined(__aarch64__)
int16x8_t a, *b;
while (len >= 8) {
a = *(int16x8_t *)&iq[0];
b = (int16x8_t *)&iq_scale[0];
*b = vshrq_n_s16(a, shift);
iq += 8;
iq_scale += 8;
len -= 8;
}
#endif
/* remaining data */
while (len != 0) {
iq_scale[0] = iq[0] >> shift;
iq++;
iq_scale++;
len--;
}
}
/*! \brief get current timestamp
*\param device the hardware to use
*\returns timestamp of OXGRF
*/
openair0_timestamp trx_get_timestamp(openair0_device *device)
{
return 0;
}
/*! \brief Start oxgrf
* \param device the hardware to use
* \returns 0 on success
*/
int trx_oxgrf_start(openair0_device *device)
{
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
oxgrf->rx_current_ts = 0;
LOG_I(HW, "[oxgrf] Start oxgrf ...\n");
running = true;
return 0;
}
/*! \brief Called to send samples to the oxgrf RF target
\param device pointer to the device structure specific to the RF hardware target
\param timestamp The timestamp at whicch the first sample MUST be sent
\param buff Buffer which holds the samples
\param nsamps number of samples to be sent
\param cc index of the component carrier
\param flags Ignored for the moment
\returns 0 on success
*/
static int trx_oxgrf_write(openair0_device *device,openair0_timestamp timestamp, void **buff, int nsamps, int cc, int flags)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t*)device->priv;
timestamp -= device->openair0_cfg->command_line_sample_advance + device->openair0_cfg->tx_sample_advance;
uint32_t trx_flags = 0;
radio_tx_burst_flag_t flags_burst = (radio_tx_burst_flag_t) (flags & 0xf);
int end;
openair0_thread_t *write_thread = &device->write_thread;
openair0_write_package_t *write_package = write_thread->write_package;
bool first_packet_state = false, last_packet_state = false;
if (flags_burst == TX_BURST_START) {
trx_flags = 0;
first_packet_state = true;
last_packet_state = false;
} else if (flags_burst == TX_BURST_END) {
trx_flags = 1;
first_packet_state = false;
last_packet_state = true;
} else if (flags_burst == TX_BURST_START_AND_END) {
trx_flags = 1;
first_packet_state = true;
last_packet_state = true;
} else if (flags_burst == TX_BURST_MIDDLE) {
trx_flags = 0;
first_packet_state = false;
last_packet_state = false;
} else if (flags_burst == 10) { // fail safe mode
first_packet_state = false;
last_packet_state = true;
}
if (oxgrf_tx_thread == 0) {
for(int i = 0; i < cc; i++) {
int len = nsamps * 2;
int16_t *iq = buff[i];
#if defined(__x86_64) || defined(__i386__)
#if defined(__AVX512BW__)
simde__m512i a, *b;
while (len >= 32) {
if ((((uintptr_t)iq) & 0x3F) == 0) {
a = *(simde__m512i *)&iq[0];
b = (simde__m512i *)&iq[0];
*b = simde_mm512_slli_epi16(a, 4);
} else {
simde__m512i tmp = simde_mm512_loadu_si512((simde__m512i *)&iq[0]);
tmp = simde_mm512_slli_epi16(tmp, 4);
simde_mm512_storeu_si512((simde__m512i *)&iq[0], tmp);
}
iq += 32;
len -= 32;
}
#else
simde__m256i a, *b;
while (len >= 16) {
if ((((uintptr_t)iq) & 0x1F) == 0) {
a = *(simde__m256i *)&iq[0];
b = (simde__m256i *)&iq[0];
*b = simde_mm256_slli_epi16(a, 4);
} else {
simde__m256i tmp = simde_mm256_loadu_si256((simde__m256i *)&iq[0]);
tmp = simde_mm256_slli_epi16(tmp, 4);
simde_mm256_storeu_si256((simde__m256i *)&iq[0], tmp);
}
iq += 16;
len -= 16;
}
#endif
#elif defined(__arm__) || defined(__aarch64__)
int16x8_t a, *b;
while (len >= 8) {
a = *(int16x8_t *)&iq[0];
b = (int16x8_t *)&iq[0];
*b = vshlq_n_s16(a, 4);
iq += 8;
len -= 8;
}
#endif
/* remaining data */
while (len != 0) {
iq[0] <<= 4;
iq++;
len--;
}
}
status = oxgrf_write_samples_multiport(oxgrf->dev, (const void **)buff, nsamps, channel_to_mask(cc), timestamp, trx_flags);
if (status < 0) {
oxgrf->num_tx_errors++;
LOG_E(HW, "[oxgrf] Failed to TX samples\n");
exit(-1);
}
//LOG_D(HW, "Provided TX timestamp: %u, nsamps: %u\n", ptimestamp, nsamps);
oxgrf->tx_current_ts = timestamp;
oxgrf->tx_nsamps += nsamps;
oxgrf->tx_count++;
return nsamps;
} else {
pthread_mutex_lock(&write_thread->mutex_write);
if (write_thread->count_write >= MAX_WRITE_THREAD_PACKAGE) {
LOG_W(HW,
"Buffer overflow, count_write = %d, start = %d end = %d, resetting write package\n",
write_thread->count_write,
write_thread->start,
write_thread->end);
write_thread->end = write_thread->start;
write_thread->count_write = 0;
}
end = write_thread->end;
write_package[end].timestamp = timestamp;
write_package[end].nsamps = nsamps;
write_package[end].cc = cc;
write_package[end].first_packet = first_packet_state;
write_package[end].last_packet = last_packet_state;
write_package[end].flags_gpio = trx_flags;
for (int i = 0; i < cc; i++)
write_package[end].buff[i] = buff[i];
write_thread->count_write++;
write_thread->end = (write_thread->end + 1) % MAX_WRITE_THREAD_PACKAGE;
LOG_D(HW, "Signaling TX TS %llu\n", (unsigned long long)timestamp);
pthread_cond_signal(&write_thread->cond_write);
pthread_mutex_unlock(&write_thread->mutex_write);
return 0;
}
}
void *trx_oxgrf_write_thread(void *arg)
{
int ret = 0;
openair0_device *device = (openair0_device *)arg;
openair0_thread_t *write_thread = &device->write_thread;
openair0_write_package_t *write_package = write_thread->write_package;
oxgrf_state_t *s;
int start;
openair0_timestamp timestamp;
void **buff;
int nsamps;
int cc;
int flags_gpio;
while(1) {
pthread_mutex_lock(&write_thread->mutex_write);
while (write_thread->count_write == 0) {
pthread_cond_wait(&write_thread->cond_write,&write_thread->mutex_write); // this unlocks mutex_rxtx while waiting and then locks it again
}
if (write_thread->write_thread_exit)
break;
s = (oxgrf_state_t *)device->priv;
start = write_thread->start;
timestamp = write_package[start].timestamp;
buff = write_package[start].buff;
nsamps = write_package[start].nsamps;
cc = write_package[start].cc;
flags_gpio = write_package[start].flags_gpio;
write_thread->start = (write_thread->start + 1)% MAX_WRITE_THREAD_PACKAGE;
write_thread->count_write--;
pthread_mutex_unlock(&write_thread->mutex_write);
for(int i = 0; i < cc; i++) {
int len = nsamps * 2;
int16_t *iq = buff[i];
#if defined(__x86_64) || defined(__i386__)
simde__m256i a, *b;
while (len >= 16) {
if ((((uintptr_t)iq) & 0x1F) == 0) {
a = *(simde__m256i *)&iq[0];
b = (simde__m256i *)&iq[0];
*b = simde_mm256_slli_epi16(a, 4);
} else {
simde__m256i tmp = simde_mm256_loadu_si256((simde__m256i *)&iq[0]);
tmp = simde_mm256_slli_epi16(tmp, 4);
simde_mm256_storeu_si256((simde__m256i *)&iq[0], tmp);
}
iq += 16;
len -= 16;
}
#elif defined(__arm__) || defined(__aarch64__)
int16x8_t a, *b;
while (len >= 8) {
a = *(int16x8_t *)&iq[0];
b = (int16x8_t *)&iq[0];
*b = vshlq_n_s16(a, 4);
iq += 8;
len -= 8;
}
#endif
/* remaining data */
while (len != 0) {
iq[0] <<= 4;
iq++;
len--;
}
}
ret = oxgrf_write_samples_multiport(s->dev, (const void **)buff, nsamps, channel_to_mask(cc), timestamp, flags_gpio);
if (ret < 0) {
s->num_tx_errors++;
LOG_E(HW, "[oxgrf] Failed to TX samples\n");
exit(-1);
}
//LOG_D(HW, "Provided TX timestamp: %u, nsamps: %u\n", ptimestamp, nsamps);
s->tx_current_ts = timestamp;
s->tx_nsamps += nsamps;
s->tx_count++;
}
return NULL;
}
int trx_oxgrf_write_init(openair0_device *device)
{
openair0_thread_t *write_thread = &device->write_thread;
printf("initializing tx write thread\n");
write_thread->start = 0;
write_thread->end = 0;
write_thread->count_write = 0;
write_thread->write_thread_exit = false;
printf("end of tx write thread\n");
pthread_mutex_init(&write_thread->mutex_write, NULL);
pthread_cond_init(&write_thread->cond_write, NULL);
threadCreate(&write_thread->pthread_write,
trx_oxgrf_write_thread,
(void *)device,
(char*)"trx_oxgrf_write_thread",
-1,
OAI_PRIORITY_RT_MAX);
return(0);
}
static void trx_oxgrf_write_reset(openair0_thread_t *wt)
{
pthread_mutex_lock(&wt->mutex_write);
wt->count_write = 1;
wt->write_thread_exit = true;
pthread_cond_signal(&wt->cond_write);
pthread_mutex_unlock(&wt->mutex_write);
void *retval = NULL;
pthread_join(wt->pthread_write, &retval);
LOG_I(HW, "stopped OXGRF write thread\n");
}
/*! \brief Receive samples from hardware.
* Read \ref nsamps samples from each channel to buffers. buff[0] is the array for
* the first channel. *ptimestamp is the time at which the first sample
* was received.
* \param device the hardware to use
* \param[out] ptimestamp the time at which the first sample was received.
* \param[out] buff An array of pointers to buffers for received samples. The buffers must be large enough to hold the number of samples \ref nsamps.
* \param nsamps Number of samples. One sample is 2 byte I + 2 byte Q => 4 byte.
* \param cc Index of component carrier
* \returns number of samples read
*/
static int trx_oxgrf_read(openair0_device *device, openair0_timestamp *ptimestamp, void **buff, int nsamps, int cc)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
uint64_t timestamp = 0UL;
retry:
if(remain == 0) {
int recv = 0;
timestamp = 0UL;
if(nsamps % RX_MTU) {
recv = (nsamps / RX_MTU + 1) * RX_MTU;
status = oxgrf_read_samples_multiport(oxgrf->dev, iq_buf, recv, channel_to_mask(cc), &timestamp);
if (status < 0) {
LOG_E(HW, "[oxgrf] Failed to read samples %d\n", nsamps);
oxgrf->num_rx_errors++;
exit(-1);
}
for(int i = 0; i < cc; i++)
rx_iq_shift((int16_t *)buff[i], (int16_t *)iq_buf[i], nsamps * 2, shift);
if(recv > nsamps) {
for(int i = 0; i < cc; i++)
memcpy(cache_buf[i], iq_buf[i] + nsamps * 4, (recv - nsamps) * 4);
remain = recv - nsamps;
}
} else {
recv = nsamps;
status = oxgrf_read_samples_multiport(oxgrf->dev, buff, recv, channel_to_mask(cc), &timestamp);
if (status < 0) {
LOG_E(HW, "[oxgrf] Failed to read samples %d\n", nsamps);
oxgrf->num_rx_errors++;
exit(-1);
}
}
*(uint64_t *)ptimestamp = timestamp;
oxgrf->rx_current_ts = timestamp + nsamps;
//LOG_D(HW, "case 0: Current RX timestamp %"PRIu64", hw ts %"PRIu64", nsamps %u, remain %u, recv: %u\n", *ptimestamp, timestamp, nsamps, remain, recv);
} else if(remain >= nsamps) {
for(int i = 0; i < cc; i++)
rx_iq_shift((int16_t *)buff[i], (int16_t *)cache_buf[i], nsamps * 2, shift);
remain -= nsamps;
if(remain > 0) {
for(int i = 0; i < cc; i++)
memmove(cache_buf[i], cache_buf[i] + nsamps * 4, remain * 4);
}
*(uint64_t *)ptimestamp = oxgrf->rx_current_ts;
oxgrf->rx_current_ts += nsamps;
//LOG_D(HW, "case 1: Current RX timestamp %"PRIu64", nsamps %u, remain %u\n", *ptimestamp, nsamps, remain);
} else {
int recv;
if(remain + RX_MTU >= nsamps)
recv = RX_MTU;
else
recv = (nsamps / RX_MTU + 1) * RX_MTU;
timestamp = 0UL;
void *tmp_ptr[4];
for(int i = 0; i < cc; i++) {
tmp_ptr[i] = cache_buf[i] + remain * 4;
}
status = oxgrf_read_samples_multiport(oxgrf->dev, tmp_ptr, recv, channel_to_mask(cc), &timestamp);
if (status < 0) {
LOG_E(HW, "[oxgrf] Failed to read samples %d\n", nsamps);
oxgrf->num_rx_errors++;
exit(-1);
}
if(timestamp != (oxgrf->rx_current_ts + remain)) {
int overflow = timestamp - (oxgrf->rx_current_ts + remain);
LOG_W(HW, "Rx overflow %u samples\n", overflow);
//remain += overflow;
remain = 0;
goto retry;
}
remain += recv;
for(int i = 0; i < cc; i++) {
rx_iq_shift((int16_t *)buff[i], (int16_t *)cache_buf[i], nsamps * 2, shift);
memmove(cache_buf[i], cache_buf[i] + nsamps * 4, (remain - nsamps) * 4);
}
remain -= nsamps;
*(uint64_t *)ptimestamp = oxgrf->rx_current_ts;
oxgrf->rx_current_ts += nsamps;
//LOG_D(HW, "case 2: Current RX timestamp %"PRIu64", hw ts %"PRIu64", nsamps %u, remain %u, recv: %u\n", *ptimestamp, timestamp, nsamps, remain, recv);
}
//LOG_D(HW, "Current RX timestamp %"PRIu64", nsamps %u\n", *ptimestamp, nsamps);
oxgrf->rx_nsamps += nsamps;
oxgrf->rx_count++;
//fixme:
//if(device->openair0_cfg->nr_band >= 257)
// *(uint64_t *)ptimestamp -= device->openair0_cfg->tx_sample_advance;
return nsamps;
}
/*! \brief Terminate operation of the oxgrf transceiver -- free all associated resources
* \param device the hardware to use
*/
void trx_oxgrf_end(openair0_device *device)
{
oxgrf_state_t *oxgrf = (oxgrf_state_t*)device->priv;
if(!running)
return;
running = false;
LOG_I(HW, ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
for(int i = 0; i < oxgrf->tx_num_channels; i++) {
uint32_t count = 0;
oxgrf_get_channel_event(oxgrf->dev, TX_CHANNEL_TIMEOUT, i+1, &count);
LOG_I(HW, "[oxgrf] TX%d Channel timeout: %u\n", i+1, count);
}
for(int i = 0; i < oxgrf->rx_num_channels; i++) {
uint32_t count = 0;
oxgrf_get_channel_event(oxgrf->dev, RX_CHANNEL_OVERFLOW, i+1, &count);
LOG_I(HW, "[oxgrf] RX%d Channel overflow: %u\n", i+1, count);
}
LOG_I(HW, "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
if (oxgrf_tx_thread != 0)
trx_oxgrf_write_reset(&device->write_thread);
oxgrf_close_device(oxgrf->dev);
return;
}
/*! \brief print the oxgrf statistics
* \param device the hardware to use
* \returns 0 on success
*/
int trx_oxgrf_get_stats(openair0_device* device)
{
return 0;
}
/*! \brief Reset the oxgrf statistics
* \param device the hardware to use
* \returns 0 on success
*/
int trx_oxgrf_reset_stats(openair0_device* device)
{
return 0;
}
/*! \brief Stop oxgrf
* \param card the hardware to use
* \returns 0 in success
*/
int trx_oxgrf_stop(openair0_device* device)
{
//oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
return 0;
}
/*! \brief Set frequencies (TX/RX)
* \param device the hardware to use
* \param openair0_cfg RF frontend parameters set by application
* \param dummy dummy variable not used
* \returns 0 in success
*/
int trx_oxgrf_set_freq(openair0_device* device, openair0_config_t *openair0_cfg)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
if(oxgrf->tx_lo_freq != openair0_cfg->tx_freq[0]) {
if ((status = oxgrf_set_tx_lo_freq(oxgrf->dev, 0, (uint64_t)(openair0_cfg->tx_freq[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX frequency\n");
} else {
LOG_I(HW, "[oxgrf] set TX frequency to %lu\n",(uint64_t)(openair0_cfg->tx_freq[0]));
oxgrf->tx_lo_freq = openair0_cfg->tx_freq[0];
}
}
if(oxgrf->rx_lo_freq != openair0_cfg->rx_freq[0]) {
if ((status = oxgrf_set_rx_lo_freq(oxgrf->dev, 0, (uint64_t)(openair0_cfg->rx_freq[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX frequency\n");
} else {
LOG_I(HW, "[oxgrf] set RX frequency to %lu\n",(uint64_t)(openair0_cfg->rx_freq[0]));
oxgrf->rx_lo_freq = openair0_cfg->rx_freq[0];
}
}
return 0;
}
/*! \brief calibration table for OXGRF */
rx_gain_calib_table_t calib_table_oxgrf[] = {
{3500000000.0, 72.0},
{2660000000.0, 72.0},
{2300000000.0, 72.0},
{1880000000.0, 72.0},
{816000000.0, 72.0},
{-1,0}
};
rx_gain_calib_table_t calib_table_none[] = {
{3500000000.0, 0.0},
{2660000000.0, 0.0},
{2300000000.0, 0.0},
{1880000000.0, 0.0},
{816000000.0, 0.0},
{-1,0}
};
/*! \brief set RX gain offset from calibration table
* \param openair0_cfg RF frontend parameters set by application
* \param chain_index RF chain ID
*/
void set_rx_gain_offset(openair0_config_t *openair0_cfg, int chain_index)
{
int i = 0;
// loop through calibration table to find best adjustment factor for RX frequency
double min_diff = 6e9, diff;
while (openair0_cfg->rx_gain_calib_table[i].freq > 0) {
diff = fabs(openair0_cfg->rx_freq[chain_index] - openair0_cfg->rx_gain_calib_table[i].freq);
printf("cal %d: freq %f, offset %f, diff %f\n",
i,
openair0_cfg->rx_gain_calib_table[i].freq,
openair0_cfg->rx_gain_calib_table[i].offset, diff);
if (min_diff > diff) {
min_diff = diff;
openair0_cfg->rx_gain_offset[chain_index] = openair0_cfg->rx_gain_calib_table[i].offset;
}
i++;
}
}
/*! \brief Set Gains (TX/RX)
* \param device the hardware to use
* \param openair0_cfg openair0 Config structure
* \returns 0 in success
*/
int trx_oxgrf_set_gains(openair0_device* device, openair0_config_t *openair0_cfg)
{
int ret = 0;
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
if (openair0_cfg->rx_gain[0] > 65+openair0_cfg->rx_gain_offset[0]) {
LOG_E(HW, "[oxgrf] Reduce RX Gain 0 by %f dB\n", openair0_cfg->rx_gain[0] - openair0_cfg->rx_gain_offset[0] - 65);
return -1;
}
if ((ret = oxgrf_set_rx1_rf_gain(oxgrf->dev, 0, (uint32_t)(openair0_cfg->rx_gain[0] - openair0_cfg->rx_gain_offset[0]))) < 0) {
LOG_I(HW, "[oxgrf] Failed to set RX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX1 gain to %u\n",(uint32_t)(openair0_cfg->rx_gain[0]));
if(oxgrf->rx_num_channels > 1) {
if ((ret = oxgrf_set_rx2_rf_gain(oxgrf->dev, 0, (uint32_t)(openair0_cfg->rx_gain[1] - openair0_cfg->rx_gain_offset[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX gain to %u\n",(uint32_t)(openair0_cfg->rx_gain[1]));
}
#if 0
if ((ret = oxgrf_set_tx1_attenuation(oxgrf->dev, 0, openair0_cfg->tx_gain[0] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX1 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[0]);
if(oxgrf->tx_num_channels > 1) {
if ((ret = oxgrf_set_tx2_attenuation(oxgrf->dev, 0, openair0_cfg->tx_gain[1] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX2 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[1]);
}
#endif
return ret;
}
/*! \brief Initialize Openair oxgrf target. It returns 0 if OK
* \param device the hardware to use
* \param openair0_cfg RF frontend parameters set by application
* \returns 0 on success
*/
int device_init(openair0_device *device, openair0_config_t *openair0_cfg)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t*)malloc(sizeof(oxgrf_state_t));
memset(oxgrf, 0, sizeof(oxgrf_state_t));
LOG_I(HW, "[oxgrf] openair0_cfg[0].sdr_addrs == '%s'\n", openair0_cfg[0].sdr_addrs);
LOG_I(HW, "[oxgrf] openair0_cfg[0].rx_num_channels == '%d'\n", openair0_cfg[0].rx_num_channels);
LOG_I(HW, "[oxgrf] openair0_cfg[0].tx_num_channels == '%d'\n", openair0_cfg[0].tx_num_channels);
//openair0_cfg->iq_txshift = 0;
//openair0_cfg->iq_rxrescale = 15;
oxgrf->sample_rate = (unsigned int)openair0_cfg->sample_rate;
LOG_I(HW, "[oxgrf] sampling_rate %d\n", oxgrf->sample_rate);
oxgrf->rx_num_channels = openair0_cfg[0].rx_num_channels;
oxgrf->tx_num_channels = openair0_cfg[0].tx_num_channels;
RX_MTU = openair0_cfg[0].sample_rate / 1000 / 2;
if(RX_MTU >= 61440)
RX_MTU = 61440;
else if(!(RX_MTU % 5760))
RX_MTU = 5760;
else
RX_MTU = 30720;
if(openair0_cfg[0].nr_band >= 257) {
switch (openair0_cfg[0].num_rb_dl) {
case 264:
RX_MTU = 61440;
break;
case 132:
RX_MTU = 30720;
break;
case 66:
RX_MTU = 15360;
break;
case 32:
default:
RX_MTU = 7680;
break;
}
}
bool rx_ant = true;
bool pa_status = false;
int auxdac1 = 0;
char args[64];
if (openair0_cfg[0].sdr_addrs == NULL) {
strcpy(args, "dev=pciex:0");
} else {
strcpy(args, openair0_cfg[0].sdr_addrs);
}
char dev_str[64];
const char dev_arg[] = "dev=";
char *dev_ptr = strstr(args, dev_arg);
if(dev_ptr) {
copy_subdev_string(dev_str, dev_ptr + strlen(dev_arg));
remove_substring(args, dev_arg);
remove_substring(args, dev_str);
LOG_I(HW, "[oxgrf] Using %s\n", dev_str);
}
const char auxdac1_arg[] = "auxdac1=";
char auxdac1_str[64] = {0};
char *auxdac1_ptr = strstr(args, auxdac1_arg);
if(auxdac1_ptr) {
copy_subdev_string(auxdac1_str, auxdac1_ptr + strlen(auxdac1_arg));
remove_substring(args, auxdac1_arg);
remove_substring(args, auxdac1_str);
auxdac1 = atoi(auxdac1_str);
LOG_I(HW, "[oxgrf] Setting auxdac1:%u\n", auxdac1);
}
const char pa_arg[] = "pa=";
char pa_str[64] = {0};
char *pa_ptr = strstr(args, pa_arg);
if(pa_ptr) {
copy_subdev_string(pa_str, pa_ptr + strlen(pa_arg));
remove_substring(args, pa_arg);
remove_substring(args, pa_str);
pa_status = !strcmp(pa_str, "enabled");
LOG_I(HW, "[oxgrf] PA Status:%s\n", pa_status?"Enabled":"Disabled");
}
const char ant_arg[] = "rx_ant=";
char ant_str[64] = {0};
char *ant_ptr = strstr(args, ant_arg);
if(ant_ptr) {
copy_subdev_string(ant_str, ant_ptr + strlen(ant_arg));
remove_substring(args, ant_arg);
remove_substring(args, ant_str);
rx_ant = strcmp(ant_str, "trx");
}
char dstring[128];
if(RX_MTU < 30720) {
sprintf(dstring, ",nsamples_recv_frame:%u", RX_MTU);
strcat(dev_str, dstring);
}
if ((oxgrf->dev = oxgrf_open_device(dev_str)) == NULL ) {
LOG_E(HW, "[oxgrf] Failed to open oxgrf\n");
free(oxgrf);
return -1;
}
uint32_t model = 0;
oxgrf_get_model_version(oxgrf->dev, &model);
model &= 0xffff;
if(model == 550) {
oxgrf->BoardType = Y550;
shift = 4;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 230) {
oxgrf->BoardType = Y230;
shift = 4;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 240) {
oxgrf->BoardType = Y240;
shift = 4;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 380) {
oxgrf->BoardType = Y380;
shift = 4;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 590) {
oxgrf->BoardType = Y590;
shift = 2;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 7400) {
oxgrf->BoardType = IQX7400;
shift = 2;
LOG_I(HW, "[oxgrf] device type: IQX%d\n", model);
} else if(model == 7402) {
oxgrf->BoardType = IQX7402;
shift = 2;
LOG_I(HW, "[oxgrf] device type: IQX%d(Split Mode)\n", model - 2);
} else if(model == 8400) {
oxgrf->BoardType = IQX8400;
shift = 2;
LOG_I(HW, "[oxgrf] device type: IQX%d\n", model);
} else if(model == 8800) {
oxgrf->BoardType = IQX8800;
shift = 2;
LOG_I(HW, "[oxgrf] device type: IQX%d\n", model);
} else if(model == 6000 || model == 7000 || model == 7100) {
oxgrf->BoardType = IQX7000;
shift = 2;
LOG_I(HW, "[oxgrf] device type: IQX%d\n", model);
} else {
oxgrf->BoardType = UNKNOWN;
shift = 0;
LOG_I(HW, "[oxgrf] device type: unknown\n");
}
if(oxgrf->BoardType == Y230) {
switch ((int)openair0_cfg->sample_rate) {
#if 0
case 61440000:
openair0_cfg->samples_per_packet = 30720;
openair0_cfg->tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
case 46080000:
openair0_cfg->samples_per_packet = 23040;
openair0_cfg->tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
#endif
case 30720000:
openair0_cfg[0].samples_per_packet = 15360;
openair0_cfg[0].tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 23040000:
openair0_cfg[0].samples_per_packet = 11520;
openair0_cfg[0].tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 15360000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 52;
openair0_cfg[0].tx_bw = 10e6;
openair0_cfg[0].rx_bw = 10e6;
break;
case 7680000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 34;
openair0_cfg[0].tx_bw = 5e6;
openair0_cfg[0].rx_bw = 5e6;
break;
case 3840000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 18;
openair0_cfg[0].tx_bw = 3e6;
openair0_cfg[0].rx_bw = 3e6;
break;
case 1920000:
openair0_cfg[0].samples_per_packet = 1920;
openair0_cfg[0].tx_sample_advance = 9;
openair0_cfg[0].tx_bw = 1.4e6;
openair0_cfg[0].rx_bw = 1.4e6;
break;
default:
LOG_I(HW, "[oxgrf] Error: unknown sampling rate %f\n", openair0_cfg->sample_rate);
free(oxgrf);
exit(-1);
break;
}
openair0_cfg[0].rx_gain_calib_table = calib_table_oxgrf;
set_rx_gain_offset(openair0_cfg, 0);
if(oxgrf->rx_num_channels > 1)
set_rx_gain_offset(openair0_cfg, 1);
}
if(oxgrf->BoardType == Y240) {
switch ((int)openair0_cfg->sample_rate) {
case 61440000:
openair0_cfg->samples_per_packet = 30720;
openair0_cfg->tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 50e6;
openair0_cfg[0].rx_bw = 50e6;
break;
case 46080000:
openair0_cfg->samples_per_packet = 23040;
openair0_cfg->tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
case 30720000:
openair0_cfg[0].samples_per_packet = 15360;
openair0_cfg[0].tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 23040000:
openair0_cfg[0].samples_per_packet = 11520;
openair0_cfg[0].tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 15360000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 52;
openair0_cfg[0].tx_bw = 10e6;
openair0_cfg[0].rx_bw = 10e6;
break;
case 7680000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 34;
openair0_cfg[0].tx_bw = 5e6;
openair0_cfg[0].rx_bw = 5e6;
break;
case 3840000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 18;
openair0_cfg[0].tx_bw = 3e6;
openair0_cfg[0].rx_bw = 3e6;
break;
case 1920000:
openair0_cfg[0].samples_per_packet = 1920;
openair0_cfg[0].tx_sample_advance = 9;
openair0_cfg[0].tx_bw = 1.4e6;
openair0_cfg[0].rx_bw = 1.4e6;
break;
default:
LOG_I(HW, "[oxgrf] Error: unknown sampling rate %f\n", openair0_cfg->sample_rate);
free(oxgrf);
exit(-1);
break;
}
openair0_cfg[0].rx_gain_calib_table = calib_table_none;
set_rx_gain_offset(openair0_cfg, 0);
if(oxgrf->rx_num_channels > 1)
set_rx_gain_offset(openair0_cfg, 1);
}
if(oxgrf->BoardType == Y380
|| oxgrf->BoardType == Y550
|| oxgrf->BoardType == Y590
|| oxgrf->BoardType == IQX7000
|| oxgrf->BoardType == IQX7402
|| oxgrf->BoardType == IQX7400) {
switch ((int)openair0_cfg->sample_rate) {
case 122880000:
openair0_cfg[0].samples_per_packet = 30720;
openair0_cfg[0].tx_sample_advance = 574;
openair0_cfg[0].tx_bw = 100e6;
openair0_cfg[0].rx_bw = 100e6;
break;
case 61440000:
openair0_cfg[0].samples_per_packet = 30720;
openair0_cfg[0].tx_sample_advance = 287;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
case 30720000:
openair0_cfg[0].samples_per_packet = 15360;
openair0_cfg[0].tx_sample_advance = 144;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 15360000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 72;
openair0_cfg[0].tx_bw = 10e6;
openair0_cfg[0].rx_bw = 10e6;
break;
case 7680000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 36;
openair0_cfg[0].tx_bw = 5e6;
openair0_cfg[0].rx_bw = 5e6;
break;
case 3840000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 18;
openair0_cfg[0].tx_bw = 3e6;
openair0_cfg[0].rx_bw = 3e6;
break;
case 1920000:
openair0_cfg[0].samples_per_packet = 1920;
openair0_cfg[0].tx_sample_advance = 10;
openair0_cfg[0].tx_bw = 1.4e6;
openair0_cfg[0].rx_bw = 1.4e6;
break;
default:
LOG_I(HW, "[oxgrf] Error: unknown sampling rate %f\n", openair0_cfg->sample_rate);
free(oxgrf);
exit(-1);
break;
}
//openair0_cfg[0].rx_gain_calib_table = calib_table_oxgrf;
openair0_cfg[0].rx_gain_calib_table = calib_table_none;
set_rx_gain_offset(openair0_cfg, 0);
if(oxgrf->rx_num_channels > 1)
set_rx_gain_offset(openair0_cfg, 1);
}
if(oxgrf->BoardType == IQX8800
|| oxgrf->BoardType == IQX8400
|| oxgrf->BoardType == Y750) {
switch ((int)openair0_cfg->sample_rate) {
case 245760000:
openair0_cfg[0].samples_per_packet = 61440;
openair0_cfg[0].tx_sample_advance = 111;
openair0_cfg[0].tx_bw = 200e6;
openair0_cfg[0].rx_bw = 200e6;
break;
case 122880000:
openair0_cfg[0].samples_per_packet = 30720;
openair0_cfg[0].tx_sample_advance = 111;
openair0_cfg[0].tx_bw = 100e6;
openair0_cfg[0].rx_bw = 100e6;
break;
case 61440000:
openair0_cfg[0].samples_per_packet = 30720;
openair0_cfg[0].tx_sample_advance = 172;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
case 30720000:
openair0_cfg[0].samples_per_packet = 15360;
openair0_cfg[0].tx_sample_advance = 169;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 15360000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 72;
openair0_cfg[0].tx_bw = 10e6;
openair0_cfg[0].rx_bw = 10e6;
break;
case 7680000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 36;
openair0_cfg[0].tx_bw = 5e6;
openair0_cfg[0].rx_bw = 5e6;
break;
case 3840000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 18;
openair0_cfg[0].tx_bw = 3e6;
openair0_cfg[0].rx_bw = 3e6;
break;
case 1920000:
openair0_cfg[0].samples_per_packet = 1920;
openair0_cfg[0].tx_sample_advance = 10;
openair0_cfg[0].tx_bw = 1.4e6;
openair0_cfg[0].rx_bw = 1.4e6;
break;
default:
LOG_I(HW, "[oxgrf] Error: unknown sampling rate %f\n", openair0_cfg->sample_rate);
free(oxgrf);
exit(-1);
break;
}
//openair0_cfg[0].rx_gain_calib_table = calib_table_oxgrf;
openair0_cfg[0].rx_gain_calib_table = calib_table_none;
set_rx_gain_offset(openair0_cfg, 0);
if(oxgrf->rx_num_channels > 1)
set_rx_gain_offset(openair0_cfg, 1);
}
LOG_I(HW, "[oxgrf] Initializing openair0_device\n");
switch (openair0_cfg[0].clock_source) {
case external:
LOG_I(HW, "[oxgrf] clock_source: external\n");
oxgrf_set_ref_clock (oxgrf->dev, 0, EXTERNAL_REFERENCE);
oxgrf_set_pps_select (oxgrf->dev, 0, PPS_EXTERNAL_EN);
break;
case gpsdo:
LOG_I(HW, "[oxgrf] clock_source: gpsdo\n");
break;
case internal:
default:
oxgrf_set_ref_clock (oxgrf->dev, 0, INTERNAL_REFERENCE);
oxgrf_set_pps_select (oxgrf->dev, 0, PPS_INTERNAL_EN);
//oxgrf_set_vco_select (oxgrf->dev, 0, AUXDAC1);
LOG_I(HW, "[oxgrf] clock_source: internal\n");
break;
}
oxgrf_set_auxdac1 (oxgrf->dev, 0, auxdac1);
if (pa_status) {
oxgrf_set_duplex_select (oxgrf->dev, 0, TO_OXGRF_OLD_VALUE(FDD));
oxgrf_set_trxsw_fpga_enable(oxgrf->dev, 0, 1);
oxgrf_set_rx_ant_enable (oxgrf->dev, 0, 0);
} else if (openair0_cfg->duplex_mode == duplex_mode_TDD && !rx_ant) {
oxgrf_set_duplex_select (oxgrf->dev, 0, TO_OXGRF_OLD_VALUE(TDD));
oxgrf_set_trxsw_fpga_enable(oxgrf->dev, 0, 1);
oxgrf_set_rx_ant_enable (oxgrf->dev, 0, 0);
} else {
oxgrf_set_duplex_select (oxgrf->dev, 0, TO_OXGRF_OLD_VALUE(FDD));
oxgrf_set_trxsw_fpga_enable(oxgrf->dev, 0, 0);
oxgrf_set_rx_ant_enable (oxgrf->dev, 0, 1);
}
LOG_I(HW, "[oxgrf] RX Ant:%s\n", rx_ant?"Enabled":"Disabled");
oxgrf_set_tx_fir_en_dis (oxgrf->dev, 0, 0);
oxgrf_set_rx_fir_en_dis (oxgrf->dev, 0, 0);
int max_idx = ((oxgrf->rx_num_channels > 2 || oxgrf->tx_num_channels > 2)? 1 : 0);
for(int chip_idx = 0; chip_idx <= max_idx; chip_idx++) {
// RX port Initialize
if ((status = oxgrf_set_rx_lo_freq(oxgrf->dev, chip_idx, (uint64_t)(openair0_cfg->rx_freq[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX frequency\n");
} else
LOG_I(HW, "[oxgrf] set RX frequency to %lu\n",(uint64_t)(openair0_cfg->rx_freq[0]));
if ((status = oxgrf_set_rx_sampling_freq(oxgrf->dev, chip_idx, (uint32_t)(openair0_cfg->sample_rate))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX sample rate\n");
} else
LOG_I(HW, "[oxgrf] set RX sample rate to %u\n", (uint32_t)(openair0_cfg->sample_rate));
if ((status = oxgrf_set_rx_rf_bandwidth(oxgrf->dev, chip_idx, (uint32_t)(openair0_cfg->rx_bw))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX bandwidth\n");
} else
LOG_I(HW, "[oxgrf] set RX bandwidth to %u\n",(uint32_t)(openair0_cfg->rx_bw));
if ((status = oxgrf_set_rx1_gain_control_mode(oxgrf->dev, chip_idx, 0)) < 0){
LOG_E(HW, "[oxgrf] Failed to set RX1 Gain Control Mode\n");
} else
LOG_I(HW, "[oxgrf] set RX1 Gain Control Mode MGC\n");
uint32_t rxgain = openair0_cfg->rx_gain[0] - openair0_cfg->rx_gain_offset[0];
if (openair0_cfg->rx_gain_offset[0] > 0) {
if (rxgain > 30)
rxgain = 60;
else
rxgain *= 2;
} else {
if (rxgain > 60)
rxgain = 60;
}
if ((status = oxgrf_set_rx1_rf_gain(oxgrf->dev, chip_idx, rxgain)) < 0) {
LOG_I(HW, "[oxgrf] Failed to set RX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX1 gain to %u\n", rxgain);
if ((status = oxgrf_set_rx2_gain_control_mode(oxgrf->dev, chip_idx, 0)) < 0){
LOG_E(HW, "[oxgrf] Failed to set RX2 Gain Control Mode\n");
} else
LOG_I(HW, "[oxgrf] set RX2 Gain Control Mode MGC\n");
if ((status = oxgrf_set_rx2_rf_gain(oxgrf->dev, chip_idx, rxgain)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX2 gain to %u\n", rxgain);
// TX port Initialize
if ((status = oxgrf_set_tx_lo_freq(oxgrf->dev, chip_idx, (uint64_t)openair0_cfg->tx_freq[0])) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX frequency\n");
} else
LOG_I(HW, "[oxgrf] set TX Frequency to %lu\n", (uint64_t)openair0_cfg->tx_freq[0]);
if ((status = oxgrf_set_tx_sampling_freq(oxgrf->dev, chip_idx, (uint32_t)openair0_cfg->sample_rate)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX sample rate\n");
} else
LOG_I(HW, "[oxgrf] set TX sampling rate to %u\n", (uint32_t)openair0_cfg->sample_rate);
if ((status = oxgrf_set_tx_rf_bandwidth(oxgrf->dev, chip_idx, (uint32_t)openair0_cfg->tx_bw)) <0) {
LOG_E(HW, "[oxgrf] Failed to set TX bandwidth\n");
} else
LOG_I(HW, "[oxgrf] set TX bandwidth to %u\n", (uint32_t)openair0_cfg->tx_bw);
if ((status = oxgrf_set_tx1_attenuation(oxgrf->dev, chip_idx, openair0_cfg->tx_gain[0] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX1 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[0]);
if ((status = oxgrf_set_tx2_attenuation(oxgrf->dev, chip_idx, openair0_cfg->tx_gain[1] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX2 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[1]);
}
uint32_t depth = oxgrf->sample_rate / 100 * sizeof(int) * oxgrf->rx_num_channels;
oxgrf_set_hwbuf_depth(oxgrf->dev, 0, depth);
oxgrf_enable_timestamp(oxgrf->dev, 0, 0);
sleep(2);
oxgrf_enable_timestamp(oxgrf->dev, 0, 1);
sleep(2);
for(int i = 0; i < NCHAN_PER_DEV; i++) {
int ret = posix_memalign((void **)&cache_buf[i], 4096, BUFFER_SIZE);
if(ret) {
LOG_I(HW, "Failed to alloc memory\n");
return -1;
}
ret = posix_memalign((void **)&iq_buf[i], 4096, BUFFER_SIZE);
if(ret) {
LOG_I(HW, "Failed to alloc memory\n");
return -1;
}
}
device->Mod_id = num_devices++;
device->type = OXGRF_DEV;
device->trx_start_func = trx_oxgrf_start;
device->trx_end_func = trx_oxgrf_end;
device->trx_read_func = trx_oxgrf_read;
device->trx_write_func = trx_oxgrf_write;
device->trx_get_stats_func = trx_oxgrf_get_stats;
device->trx_reset_stats_func = trx_oxgrf_reset_stats;
device->trx_stop_func = trx_oxgrf_stop;
device->trx_set_freq_func = trx_oxgrf_set_freq;
device->trx_set_gains_func = trx_oxgrf_set_gains;
device->trx_write_init = trx_oxgrf_write_init;
device->openair0_cfg = openair0_cfg;
device->priv = (void *)oxgrf;
return 0;
}
/*@}*/
radio/OXGRF/oxgrf_lib.h 0 → 100644
View file @ caeedc04
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/** oxgrf_lib.h
*
* Author: eric
* base on bladerf_lib.h
*/
#include "oxgrf_api_ss.h"
#include "common_lib.h"
/** @addtogroup _OXGRF_PHY_RF_INTERFACE_
* @{
*/
typedef enum {
Y230,
Y240,
Y380,
Y390,
Y550,
Y590,
Y750,
Y790,
IQX6000,
IQX7000,
IQX7100,
IQX7200,
IQX7400,
IQX7402, //split
IQX7600,
IQX8400,
IQX8800,
UNKNOWN = -1,
} OXGRFBoardType;
#if 0
typedef struct {
OXGRFBoardType Model;
struct {
uint64_t sample_rate;
uint64_t bandwidth;
int8_t tx_adv;
} tables[16];
} oxgrf_cfg_table;
oxgrf_cfg_table TABLE_IQX8x00 = { // for IQX8200 & IQX8400 & IQX8800
.Model = IQX8800,
.tables = {
{491520000, 400000000, 151},
{245760000, 200000000, 126},
{122880000, 100000000, 111},
{61440000, 40000000, 172},
{30720000, 20000000, 169},
{15360000, 10000000, 110},
{7680000, 5000000, 110},
{3840000, 3000000, 110},
{1920000, 1400000, 110},
},
};
oxgrf_cfg_table TABLE_IQX7x00 = { // for IQX7100 & IQX7400
.Model = IQX7400,
.tables = {
{122880000, 100000000, 573},
{61440000, 40000000, 286},
{30720000, 20000000, 143},
{15360000, 10000000, 73},
{7680000, 5000000, 36},
{3840000, 3000000, 17},
{1920000, 1400000, 9},
},
};
oxgrf_cfg_table TABLE_IQX7200 = { // for IQX7200
.Model = IQX7200,
.tables = {
{245760000, 200000000, 612},
{122880000, 100000000, 306},
{61440000, 40000000, 152},
{30720000, 20000000, 76},
{15360000, 10000000, 38},
{7680000, 5000000, 19},
{3840000, 3000000, 10},
{1920000, 1400000, 5},
},
};
oxgrf_cfg_table TABLE_Y590 = { // for Y590neo
.Model = Y590,
.tables = {
{245760000, 200000000, 502},
{122880000, 100000000, 251},
{61440000, 40000000, 125},
{30720000, 20000000, 63},
{15360000, 10000000, 32},
{7680000, 5000000, 16},
{3840000, 3000000, 8},
{1920000, 1400000, 4},
},
};
oxgrf_cfg_table TABLE_Y790 = { // for Y790s New/Old Version & Y750s
.Model = Y790,
.tables = {
{491520000, 400000000, 149},
{245760000, 200000000, 125},
{122880000, 100000000, 110},
{61440000, 40000000, 172},
{30720000, 20000000, 168},
},
};
oxgrf_cfg_table TABLE_Y780 = { // for Y780s New Version
.Model = Y780,
.tables = {
{245760000, 200000000, 359},
{122880000, 100000000, 179},
{61440000, 40000000, 88},
{30720000, 20000000, 43},
{15360000, 10000000, 22},
{7680000, 5000000, 11},
{3840000, 3000000, 6},
{1920000, 1400000, 3},
},
};
#endif
/*! \brief OXGRF specific data structure */
typedef struct {
//! opaque OXGRF device struct. An empty ("") or NULL device identifier will result in the first encountered device being opened (using the first discovered backend)
OXGRF_DESCRIPTOR *dev;
int16_t *rx_buffer;
int16_t *tx_buffer;
//! Sample rate
unsigned int sample_rate;
int rx_num_channels;
int tx_num_channels;
uint64_t tx_lo_freq;
uint64_t rx_lo_freq;
// --------------------------------
// Debug and output control
// --------------------------------
//! Number of underflows
int num_underflows;
//! Number of overflows
int num_overflows;
//! number of RX errors
int num_rx_errors;
//! Number of TX errors
int num_tx_errors;
//! timestamp of current TX
uint64_t tx_current_ts;
//! timestamp of current RX
uint64_t rx_current_ts;
//! number of TX samples
uint64_t tx_nsamps;
//! number of RX samples
uint64_t rx_nsamps;
//! number of TX count
uint64_t tx_count;
//! number of RX count
uint64_t rx_count;
//! timestamp of RX packet
openair0_timestamp rx_timestamp;
OXGRFBoardType BoardType;
} oxgrf_state_t;
/*! \brief get current timestamp
*\param device the hardware to use
*/
openair0_timestamp trx_get_timestamp(openair0_device *device);
/*@}*/
radio/OXGRF/oxgrf_lib_back.c 0 → 100644
View file @ caeedc04
/*
* Licensed to the OpenAirInterface (OAI) Software Alliance under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership.
* The OpenAirInterface Software Alliance licenses this file to You under
* the OAI Public License, Version 1.0 (the "License"); you may not use this file
* except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.openairinterface.org/?page_id=698
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*-------------------------------------------------------------------------------
* For more information about the OpenAirInterface (OAI) Software Alliance:
* contact@openairinterface.org
*/
/** oxgrf_lib.c
*
* Author: eric
* base on bladerf_lib.c
*/
#pragma GCC optimize(3, "Ofast", "inline", "fast-math", "unroll-loops")
#include <stdio.h>
#include <stdlib.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <inttypes.h>
#include <math.h>
#include "oxgrf_lib.h"
#include "rf_helper.h"
#include "common/utils/LOG/log.h"
#include "system.h"
/** @addtogroup _OXGRF_PHY_RF_INTERFACE_
* @{
*/
#include "openair1/PHY/sse_intrin.h"
#if defined (__AVX512BW__)
#include <simde/x86/avx512.h>
#endif
extern int oxgrf_tx_thread;
//! Number of OXGRF devices
int num_devices = 0;
static bool running = false;
#define BUFFER_SIZE (122880 * 100 * sizeof(int))
#define NCHAN_PER_DEV 4
static void *cache_buf[NCHAN_PER_DEV];
static void *iq_buf[NCHAN_PER_DEV];
static uint32_t remain = 0;
static uint32_t RX_MTU = 30720;
static uint8_t shift = 2;
static inline int channel_to_mask(int channel_count)
{
uint8_t ch_mask;
switch (channel_count) {
case 4:
ch_mask = 0xf;break;
case 3:
ch_mask = 0x7;break;
case 2:
ch_mask = 0x3;break;
case 1:
ch_mask = 0x1;break;
default:
ch_mask = 0x1;break;
}
return ch_mask;
}
static inline void rx_iq_shift(int16_t *dst, int16_t *src, ssize_t len, uint8_t shift)
{
int16_t *iq = src;
int16_t *iq_scale = dst;
#if defined(__x86_64__) || defined(__i386__)
#if defined(__AVX512BW__)
simde__m512i a, *b;
while (len >= 32) {
if ((((uintptr_t)iq) & 0x3F) == 0) {
a = *(simde__m512i *)&iq[0];
b = (simde__m512i *)&iq_scale[0];
*b = simde_mm512_srai_epi16(a, shift);
} else {
simde__m512i tmp = simde_mm512_loadu_si512((simde__m512i *)&iq[0]);
tmp = simde_mm512_srai_epi16(tmp, shift);
simde_mm512_storeu_si512((simde__m512i *)&iq_scale[0], tmp);
}
iq += 32;
iq_scale += 32;
len -= 32;
}
#else
simde__m256i a, *b;
while (len >= 16) {
if (((((uintptr_t)iq) & 0x1F) == 0)
&& ((((uintptr_t)iq_scale) & 0x1F) == 0)) {
a = *(simde__m256i *)&iq[0];
b = (simde__m256i *)&iq_scale[0];
*b = simde_mm256_srai_epi16(a, shift);
} else {
simde__m256i tmp = simde_mm256_loadu_si256((simde__m256i *)&iq[0]);
tmp = simde_mm256_srai_epi16(tmp, shift);
simde_mm256_storeu_si256((simde__m256i *)&iq_scale[0], tmp);
}
iq += 16;
iq_scale += 16;
len -= 16;
}
#endif
#elif defined(__arm__) || defined(__aarch64__)
int16x8_t a, *b;
while (len >= 8) {
a = *(int16x8_t *)&iq[0];
b = (int16x8_t *)&iq_scale[0];
*b = vshrq_n_s16(a, shift);
iq += 8;
iq_scale += 8;
len -= 8;
}
#endif
/* remaining data */
while (len != 0) {
iq_scale[0] = iq[0] >> shift;
iq++;
iq_scale++;
len--;
}
}
/*! \brief get current timestamp
*\param device the hardware to use
*\returns timestamp of OXGRF
*/
openair0_timestamp trx_get_timestamp(openair0_device *device)
{
return 0;
}
/*! \brief Start oxgrf
* \param device the hardware to use
* \returns 0 on success
*/
int trx_oxgrf_start(openair0_device *device)
{
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
oxgrf->rx_current_ts = 0;
LOG_I(HW, "[oxgrf] Start oxgrf ...\n");
running = true;
return 0;
}
/*! \brief Called to send samples to the oxgrf RF target
\param device pointer to the device structure specific to the RF hardware target
\param timestamp The timestamp at whicch the first sample MUST be sent
\param buff Buffer which holds the samples
\param nsamps number of samples to be sent
\param cc index of the component carrier
\param flags Ignored for the moment
\returns 0 on success
*/
static int trx_oxgrf_write(openair0_device *device,openair0_timestamp timestamp, void **buff, int nsamps, int cc, int flags)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t*)device->priv;
timestamp -= device->openair0_cfg->command_line_sample_advance + device->openair0_cfg->tx_sample_advance;
uint32_t trx_flags = 0;
radio_tx_burst_flag_t flags_burst = (radio_tx_burst_flag_t) (flags & 0xf);
int end;
openair0_thread_t *write_thread = &device->write_thread;
openair0_write_package_t *write_package = write_thread->write_package;
bool first_packet_state = false, last_packet_state = false;
if (flags_burst == TX_BURST_START) {
trx_flags = 0;
first_packet_state = true;
last_packet_state = false;
} else if (flags_burst == TX_BURST_END) {
trx_flags = 1;
first_packet_state = false;
last_packet_state = true;
} else if (flags_burst == TX_BURST_START_AND_END) {
trx_flags = 1;
first_packet_state = true;
last_packet_state = true;
} else if (flags_burst == TX_BURST_MIDDLE) {
trx_flags = 0;
first_packet_state = false;
last_packet_state = false;
} else if (flags_burst == 10) { // fail safe mode
first_packet_state = false;
last_packet_state = true;
}
if (oxgrf_tx_thread == 0) {
for(int i = 0; i < cc; i++) {
int len = nsamps * 2;
int16_t *iq = buff[i];
#if defined(__x86_64) || defined(__i386__)
#if defined(__AVX512BW__)
simde__m512i a, *b;
while (len >= 32) {
if ((((uintptr_t)iq) & 0x3F) == 0) {
a = *(simde__m512i *)&iq[0];
b = (simde__m512i *)&iq[0];
*b = simde_mm512_slli_epi16(a, 4);
} else {
simde__m512i tmp = simde_mm512_loadu_si512((simde__m512i *)&iq[0]);
tmp = simde_mm512_slli_epi16(tmp, 4);
simde_mm512_storeu_si512((simde__m512i *)&iq[0], tmp);
}
iq += 32;
len -= 32;
}
#else
simde__m256i a, *b;
while (len >= 16) {
if ((((uintptr_t)iq) & 0x1F) == 0) {
a = *(simde__m256i *)&iq[0];
b = (simde__m256i *)&iq[0];
*b = simde_mm256_slli_epi16(a, 4);
} else {
simde__m256i tmp = simde_mm256_loadu_si256((simde__m256i *)&iq[0]);
tmp = simde_mm256_slli_epi16(tmp, 4);
simde_mm256_storeu_si256((simde__m256i *)&iq[0], tmp);
}
iq += 16;
len -= 16;
}
#endif
#elif defined(__arm__) || defined(__aarch64__)
int16x8_t a, *b;
while (len >= 8) {
a = *(int16x8_t *)&iq[0];
b = (int16x8_t *)&iq[0];
*b = vshlq_n_s16(a, 4);
iq += 8;
len -= 8;
}
#endif
/* remaining data */
while (len != 0) {
iq[0] <<= 4;
iq++;
len--;
}
}
status = oxgrf_write_samples_multiport(oxgrf->dev, (const void **)buff, nsamps, channel_to_mask(cc), timestamp, trx_flags);
if (status < 0) {
oxgrf->num_tx_errors++;
LOG_E(HW, "[oxgrf] Failed to TX samples\n");
exit(-1);
}
//LOG_D(HW, "Provided TX timestamp: %u, nsamps: %u\n", ptimestamp, nsamps);
oxgrf->tx_current_ts = timestamp;
oxgrf->tx_nsamps += nsamps;
oxgrf->tx_count++;
return nsamps;
} else {
pthread_mutex_lock(&write_thread->mutex_write);
if (write_thread->count_write >= MAX_WRITE_THREAD_PACKAGE) {
LOG_W(HW,
"Buffer overflow, count_write = %d, start = %d end = %d, resetting write package\n",
write_thread->count_write,
write_thread->start,
write_thread->end);
write_thread->end = write_thread->start;
write_thread->count_write = 0;
}
end = write_thread->end;
write_package[end].timestamp = timestamp;
write_package[end].nsamps = nsamps;
write_package[end].cc = cc;
write_package[end].first_packet = first_packet_state;
write_package[end].last_packet = last_packet_state;
write_package[end].flags_gpio = trx_flags;
for (int i = 0; i < cc; i++)
write_package[end].buff[i] = buff[i];
write_thread->count_write++;
write_thread->end = (write_thread->end + 1) % MAX_WRITE_THREAD_PACKAGE;
LOG_D(HW, "Signaling TX TS %llu\n", (unsigned long long)timestamp);
pthread_cond_signal(&write_thread->cond_write);
pthread_mutex_unlock(&write_thread->mutex_write);
return 0;
}
}
void *trx_oxgrf_write_thread(void *arg)
{
int ret = 0;
openair0_device *device = (openair0_device *)arg;
openair0_thread_t *write_thread = &device->write_thread;
openair0_write_package_t *write_package = write_thread->write_package;
oxgrf_state_t *s;
int start;
openair0_timestamp timestamp;
void **buff;
int nsamps;
int cc;
int flags_gpio;
while(1) {
pthread_mutex_lock(&write_thread->mutex_write);
while (write_thread->count_write == 0) {
pthread_cond_wait(&write_thread->cond_write,&write_thread->mutex_write); // this unlocks mutex_rxtx while waiting and then locks it again
}
if (write_thread->write_thread_exit)
break;
s = (oxgrf_state_t *)device->priv;
start = write_thread->start;
timestamp = write_package[start].timestamp;
buff = write_package[start].buff;
nsamps = write_package[start].nsamps;
cc = write_package[start].cc;
flags_gpio = write_package[start].flags_gpio;
write_thread->start = (write_thread->start + 1)% MAX_WRITE_THREAD_PACKAGE;
write_thread->count_write--;
pthread_mutex_unlock(&write_thread->mutex_write);
for(int i = 0; i < cc; i++) {
int len = nsamps * 2;
int16_t *iq = buff[i];
#if defined(__x86_64) || defined(__i386__)
simde__m256i a, *b;
while (len >= 16) {
if ((((uintptr_t)iq) & 0x1F) == 0) {
a = *(simde__m256i *)&iq[0];
b = (simde__m256i *)&iq[0];
*b = simde_mm256_slli_epi16(a, 4);
} else {
simde__m256i tmp = simde_mm256_loadu_si256((simde__m256i *)&iq[0]);
tmp = simde_mm256_slli_epi16(tmp, 4);
simde_mm256_storeu_si256((simde__m256i *)&iq[0], tmp);
}
iq += 16;
len -= 16;
}
#elif defined(__arm__) || defined(__aarch64__)
int16x8_t a, *b;
while (len >= 8) {
a = *(int16x8_t *)&iq[0];
b = (int16x8_t *)&iq[0];
*b = vshlq_n_s16(a, 4);
iq += 8;
len -= 8;
}
#endif
/* remaining data */
while (len != 0) {
iq[0] <<= 4;
iq++;
len--;
}
}
ret = oxgrf_write_samples_multiport(s->dev, (const void **)buff, nsamps, channel_to_mask(cc), timestamp, flags_gpio);
if (ret < 0) {
s->num_tx_errors++;
LOG_E(HW, "[oxgrf] Failed to TX samples\n");
exit(-1);
}
//LOG_D(HW, "Provided TX timestamp: %u, nsamps: %u\n", ptimestamp, nsamps);
s->tx_current_ts = timestamp;
s->tx_nsamps += nsamps;
s->tx_count++;
}
return NULL;
}
int trx_oxgrf_write_init(openair0_device *device)
{
openair0_thread_t *write_thread = &device->write_thread;
printf("initializing tx write thread\n");
write_thread->start = 0;
write_thread->end = 0;
write_thread->count_write = 0;
write_thread->write_thread_exit = false;
printf("end of tx write thread\n");
pthread_mutex_init(&write_thread->mutex_write, NULL);
pthread_cond_init(&write_thread->cond_write, NULL);
threadCreate(&write_thread->pthread_write,
trx_oxgrf_write_thread,
(void *)device,
(char*)"trx_oxgrf_write_thread",
-1,
OAI_PRIORITY_RT_MAX);
return(0);
}
static void trx_oxgrf_write_reset(openair0_thread_t *wt)
{
pthread_mutex_lock(&wt->mutex_write);
wt->count_write = 1;
wt->write_thread_exit = true;
pthread_cond_signal(&wt->cond_write);
pthread_mutex_unlock(&wt->mutex_write);
void *retval = NULL;
pthread_join(wt->pthread_write, &retval);
LOG_I(HW, "stopped OXGRF write thread\n");
}
/*! \brief Receive samples from hardware.
* Read \ref nsamps samples from each channel to buffers. buff[0] is the array for
* the first channel. *ptimestamp is the time at which the first sample
* was received.
* \param device the hardware to use
* \param[out] ptimestamp the time at which the first sample was received.
* \param[out] buff An array of pointers to buffers for received samples. The buffers must be large enough to hold the number of samples \ref nsamps.
* \param nsamps Number of samples. One sample is 2 byte I + 2 byte Q => 4 byte.
* \param cc Index of component carrier
* \returns number of samples read
*/
static int trx_oxgrf_read(openair0_device *device, openair0_timestamp *ptimestamp, void **buff, int nsamps, int cc)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
uint64_t timestamp = 0UL;
retry:
if(remain == 0) {
int recv = 0;
timestamp = 0UL;
if(nsamps % RX_MTU) {
recv = (nsamps / RX_MTU + 1) * RX_MTU;
status = oxgrf_read_samples_multiport(oxgrf->dev, iq_buf, recv, channel_to_mask(cc), &timestamp);
if (status < 0) {
LOG_E(HW, "[oxgrf] Failed to read samples %d\n", nsamps);
oxgrf->num_rx_errors++;
exit(-1);
}
for(int i = 0; i < cc; i++)
rx_iq_shift((int16_t *)buff[i], (int16_t *)iq_buf[i], nsamps * 2, shift);
//memcpy(buff[i], iq_buf[i], nsamps * 4);
if(recv > nsamps) {
for(int i = 0; i < cc; i++)
memcpy(cache_buf[i], iq_buf[i] + nsamps * 4, (recv - nsamps) * 4);
remain = recv - nsamps;
}
} else {
recv = nsamps;
status = oxgrf_read_samples_multiport(oxgrf->dev, buff, recv, channel_to_mask(cc), &timestamp);
if (status < 0) {
LOG_E(HW, "[oxgrf] Failed to read samples %d\n", nsamps);
oxgrf->num_rx_errors++;
exit(-1);
}
}
*(uint64_t *)ptimestamp = timestamp;
oxgrf->rx_current_ts = timestamp + nsamps;
//LOG_D(HW, "case 0: Current RX timestamp %"PRIu64", hw ts %"PRIu64", nsamps %u, remain %u, recv: %u\n", *ptimestamp, timestamp, nsamps, remain, recv);
} else if(remain >= nsamps) {
for(int i = 0; i < cc; i++)
rx_iq_shift((int16_t *)buff[i], (int16_t *)cache_buf[i], nsamps * 2, shift);
//memcpy(buff[i], cache_buf[i], nsamps * 4);
remain -= nsamps;
if(remain > 0) {
for(int i = 0; i < cc; i++)
memmove(cache_buf[i], cache_buf[i] + nsamps * 4, remain * 4);
}
*(uint64_t *)ptimestamp = oxgrf->rx_current_ts;
oxgrf->rx_current_ts += nsamps;
//LOG_D(HW, "case 1: Current RX timestamp %"PRIu64", nsamps %u, remain %u\n", *ptimestamp, nsamps, remain);
} else {
int recv;
if(remain + RX_MTU >= nsamps)
recv = RX_MTU;
else
recv = (nsamps / RX_MTU + 1) * RX_MTU;
timestamp = 0UL;
#if 1
void *tmp_ptr[4];
for(int i = 0; i < cc; i++) {
tmp_ptr[i] = cache_buf[i] + remain * 4;
}
status = oxgrf_read_samples_multiport(oxgrf->dev, tmp_ptr, recv, channel_to_mask(cc), &timestamp);
if (status < 0) {
LOG_E(HW, "[oxgrf] Failed to read samples %d\n", nsamps);
oxgrf->num_rx_errors++;
exit(-1);
}
if(timestamp != (oxgrf->rx_current_ts + remain)) {
int overflow = timestamp - (oxgrf->rx_current_ts + remain);
LOG_W(HW, "Rx overflow %u samples\n", overflow);
//remain += overflow;
remain = 0;
goto retry;
}
remain += recv;
for(int i = 0; i < cc; i++) {
//memcpy(buff[i], cache_buf[i], nsamps * 4);
rx_iq_shift((int16_t *)buff[i], (int16_t *)cache_buf[i], nsamps * 2, shift);
memmove(cache_buf[i], cache_buf[i] + nsamps * 4, (remain - nsamps) * 4);
}
remain -= nsamps;
#else
status = oxgrf_read_samples_multiport(oxgrf->dev, iq_buf, recv, channel_to_mask(cc), &timestamp);
if (status < 0) {
LOG_E(HW, "[oxgrf] Failed to read samples %d\n", nsamps);
oxgrf->num_rx_errors++;
exit(-1);
}
if(timestamp != (oxgrf->rx_current_ts + remain)) {
int overflow = timestamp - (oxgrf->rx_current_ts + remain);
LOG_W(HW, "Rx overflow %u samples\n", overflow);
//remain += overflow;
remain = 0;
goto retry;
}
for(int i = 0; i < cc; i++)
memcpy(cache_buf[i] + remain * 4, iq_buf[i], recv * 4);
for(int i = 0; i < cc; i++)
memcpy(buff[i], cache_buf[i], nsamps * 4);
remain = recv + remain - nsamps;
for(int i = 0; i < cc; i++)
memmove(cache_buf[i], cache_buf[i] + nsamps * 4, remain * 4);
#endif
*(uint64_t *)ptimestamp = oxgrf->rx_current_ts;
oxgrf->rx_current_ts += nsamps;
//LOG_D(HW, "case 2: Current RX timestamp %"PRIu64", hw ts %"PRIu64", nsamps %u, remain %u, recv: %u\n", *ptimestamp, timestamp, nsamps, remain, recv);
}
#if 0
for (int i = 0; i < cc; i++) {
int len = nsamps * 2;
int16_t *iq = buff[i];
#if defined(__x86_64__) || defined(__i386__)
simde__m256i a, *b;
while (len >= 16) {
if ((((uintptr_t)iq) & 0x1F) == 0) {
a = *(simde__m256i *)&iq[0];
b = (simde__m256i *)&iq[0];
*b = simde_mm256_srai_epi16(a, shift);
} else {
simde__m256i tmp = simde_mm256_loadu_si256((simde__m256i *)&iq[0]);
tmp = simde_mm256_srai_epi16(tmp, shift);
simde_mm256_storeu_si256((simde__m256i *)&iq[0], tmp);
}
iq += 16;
len -= 16;
}
#elif defined(__arm__) || defined(__aarch64__)
int16x8_t a, *b;
while (len >= 8) {
a = *(int16x8_t *)&iq[0];
b = (int16x8_t *)&iq[0];
*b = vshrq_n_s16(a, shift);
iq += 8;
len -= 8;
}
#endif
/* remaining data */
while (len != 0) {
iq[0] >>= shift;
iq++;
len--;
}
}
#endif
//LOG_D(HW, "Current RX timestamp %"PRIu64", nsamps %u\n", *ptimestamp, nsamps);
oxgrf->rx_nsamps += nsamps;
oxgrf->rx_count++;
return nsamps;
}
/*! \brief Terminate operation of the oxgrf transceiver -- free all associated resources
* \param device the hardware to use
*/
void trx_oxgrf_end(openair0_device *device)
{
oxgrf_state_t *oxgrf = (oxgrf_state_t*)device->priv;
if(!running)
return;
running = false;
LOG_I(HW, ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
for(int i = 0; i < oxgrf->tx_num_channels; i++) {
uint32_t count = 0;
oxgrf_get_channel_event(oxgrf->dev, TX_CHANNEL_TIMEOUT, i+1, &count);
LOG_I(HW, "[oxgrf] TX%d Channel timeout: %u\n", i+1, count);
}
for(int i = 0; i < oxgrf->rx_num_channels; i++) {
uint32_t count = 0;
oxgrf_get_channel_event(oxgrf->dev, RX_CHANNEL_OVERFLOW, i+1, &count);
LOG_I(HW, "[oxgrf] RX%d Channel overflow: %u\n", i+1, count);
}
LOG_I(HW, "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
if (oxgrf_tx_thread != 0)
trx_oxgrf_write_reset(&device->write_thread);
oxgrf_close_device(oxgrf->dev);
return;
}
/*! \brief print the oxgrf statistics
* \param device the hardware to use
* \returns 0 on success
*/
int trx_oxgrf_get_stats(openair0_device* device)
{
return 0;
}
/*! \brief Reset the oxgrf statistics
* \param device the hardware to use
* \returns 0 on success
*/
int trx_oxgrf_reset_stats(openair0_device* device)
{
return 0;
}
/*! \brief Stop oxgrf
* \param card the hardware to use
* \returns 0 in success
*/
int trx_oxgrf_stop(openair0_device* device)
{
//oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
return 0;
}
/*! \brief Set frequencies (TX/RX)
* \param device the hardware to use
* \param openair0_cfg RF frontend parameters set by application
* \param dummy dummy variable not used
* \returns 0 in success
*/
int trx_oxgrf_set_freq(openair0_device* device, openair0_config_t *openair0_cfg)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
if(oxgrf->tx_lo_freq != openair0_cfg->tx_freq[0]) {
if ((status = oxgrf_set_tx_lo_freq(oxgrf->dev, 0, (uint64_t)(openair0_cfg->tx_freq[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX frequency\n");
} else {
LOG_I(HW, "[oxgrf] set TX frequency to %lu\n",(uint64_t)(openair0_cfg->tx_freq[0]));
oxgrf->tx_lo_freq = openair0_cfg->tx_freq[0];
}
}
if(oxgrf->rx_lo_freq != openair0_cfg->rx_freq[0]) {
if ((status = oxgrf_set_rx_lo_freq(oxgrf->dev, 0, (uint64_t)(openair0_cfg->rx_freq[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX frequency\n");
} else {
LOG_I(HW, "[oxgrf] set RX frequency to %lu\n",(uint64_t)(openair0_cfg->rx_freq[0]));
oxgrf->rx_lo_freq = openair0_cfg->rx_freq[0];
}
}
return 0;
}
/*! \brief calibration table for OXGRF */
rx_gain_calib_table_t calib_table_oxgrf[] = {
{3500000000.0, 72.0},
{2660000000.0, 72.0},
{2300000000.0, 72.0},
{1880000000.0, 72.0},
{816000000.0, 72.0},
{-1,0}
};
rx_gain_calib_table_t calib_table_none[] = {
{3500000000.0, 0.0},
{2660000000.0, 0.0},
{2300000000.0, 0.0},
{1880000000.0, 0.0},
{816000000.0, 0.0},
{-1,0}
};
/*! \brief set RX gain offset from calibration table
* \param openair0_cfg RF frontend parameters set by application
* \param chain_index RF chain ID
*/
void set_rx_gain_offset(openair0_config_t *openair0_cfg, int chain_index)
{
int i = 0;
// loop through calibration table to find best adjustment factor for RX frequency
double min_diff = 6e9, diff;
while (openair0_cfg->rx_gain_calib_table[i].freq > 0) {
diff = fabs(openair0_cfg->rx_freq[chain_index] - openair0_cfg->rx_gain_calib_table[i].freq);
printf("cal %d: freq %f, offset %f, diff %f\n",
i,
openair0_cfg->rx_gain_calib_table[i].freq,
openair0_cfg->rx_gain_calib_table[i].offset, diff);
if (min_diff > diff) {
min_diff = diff;
openair0_cfg->rx_gain_offset[chain_index] = openair0_cfg->rx_gain_calib_table[i].offset;
}
i++;
}
}
/*! \brief Set Gains (TX/RX)
* \param device the hardware to use
* \param openair0_cfg openair0 Config structure
* \returns 0 in success
*/
int trx_oxgrf_set_gains(openair0_device* device, openair0_config_t *openair0_cfg)
{
int ret = 0;
oxgrf_state_t *oxgrf = (oxgrf_state_t *)device->priv;
if (openair0_cfg->rx_gain[0] > 65+openair0_cfg->rx_gain_offset[0]) {
LOG_E(HW, "[oxgrf] Reduce RX Gain 0 by %f dB\n", openair0_cfg->rx_gain[0] - openair0_cfg->rx_gain_offset[0] - 65);
return -1;
}
if ((ret = oxgrf_set_rx1_rf_gain(oxgrf->dev, 0, (uint32_t)(openair0_cfg->rx_gain[0] - openair0_cfg->rx_gain_offset[0]))) < 0) {
LOG_I(HW, "[oxgrf] Failed to set RX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX1 gain to %u\n",(uint32_t)(openair0_cfg->rx_gain[0]));
if(oxgrf->rx_num_channels > 1) {
if ((ret = oxgrf_set_rx2_rf_gain(oxgrf->dev, 0, (uint32_t)(openair0_cfg->rx_gain[1] - openair0_cfg->rx_gain_offset[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX gain to %u\n",(uint32_t)(openair0_cfg->rx_gain[1]));
}
#if 0
if ((ret = oxgrf_set_tx1_attenuation(oxgrf->dev, 0, openair0_cfg->tx_gain[0] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX1 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[0]);
if(oxgrf->tx_num_channels > 1) {
if ((ret = oxgrf_set_tx2_attenuation(oxgrf->dev, 0, openair0_cfg->tx_gain[1] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX2 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[1]);
}
#endif
return ret;
}
/*! \brief Initialize Openair oxgrf target. It returns 0 if OK
* \param device the hardware to use
* \param openair0_cfg RF frontend parameters set by application
* \returns 0 on success
*/
int device_init(openair0_device *device, openair0_config_t *openair0_cfg)
{
int status;
oxgrf_state_t *oxgrf = (oxgrf_state_t*)malloc(sizeof(oxgrf_state_t));
memset(oxgrf, 0, sizeof(oxgrf_state_t));
LOG_I(HW, "[oxgrf] openair0_cfg[0].sdr_addrs == '%s'\n", openair0_cfg[0].sdr_addrs);
LOG_I(HW, "[oxgrf] openair0_cfg[0].rx_num_channels == '%d'\n", openair0_cfg[0].rx_num_channels);
LOG_I(HW, "[oxgrf] openair0_cfg[0].tx_num_channels == '%d'\n", openair0_cfg[0].tx_num_channels);
openair0_cfg->iq_txshift = 0;
openair0_cfg->iq_rxrescale = 15;
oxgrf->sample_rate = (unsigned int)openair0_cfg->sample_rate;
LOG_I(HW, "[oxgrf] sampling_rate %d\n", oxgrf->sample_rate);
oxgrf->rx_num_channels = openair0_cfg[0].rx_num_channels;
oxgrf->tx_num_channels = openair0_cfg[0].tx_num_channels;
RX_MTU = openair0_cfg[0].sample_rate / 1000 / 2;
if(RX_MTU >= 61440)
RX_MTU = 61440;
else if(!(RX_MTU % 5760))
RX_MTU = 5760;
else
RX_MTU = 7680;
if(openair0_cfg[0].nr_band >= 257) {
switch (openair0_cfg[0].num_rb_dl) {
case 264:
RX_MTU = 61440;
break;
case 132:
RX_MTU = 30720;
break;
case 66:
RX_MTU = 15360;
break;
case 32:
default:
RX_MTU = 7680;
break;
}
}
bool rx_ant = true;
bool pa_status = false;
int auxdac1 = 0;
char args[64];
if (openair0_cfg[0].sdr_addrs == NULL) {
strcpy(args, "dev=pciex:0");
} else {
strcpy(args, openair0_cfg[0].sdr_addrs);
}
char dev_str[64];
const char dev_arg[] = "dev=";
char *dev_ptr = strstr(args, dev_arg);
if(dev_ptr) {
copy_subdev_string(dev_str, dev_ptr + strlen(dev_arg));
remove_substring(args, dev_arg);
remove_substring(args, dev_str);
LOG_I(HW, "[oxgrf] Using %s\n", dev_str);
}
const char auxdac1_arg[] = "auxdac1=";
char auxdac1_str[64] = {0};
char *auxdac1_ptr = strstr(args, auxdac1_arg);
if(auxdac1_ptr) {
copy_subdev_string(auxdac1_str, auxdac1_ptr + strlen(auxdac1_arg));
remove_substring(args, auxdac1_arg);
remove_substring(args, auxdac1_str);
auxdac1 = atoi(auxdac1_str);
LOG_I(HW, "[oxgrf] Setting auxdac1:%u\n", auxdac1);
}
const char pa_arg[] = "pa=";
char pa_str[64] = {0};
char *pa_ptr = strstr(args, pa_arg);
if(pa_ptr) {
copy_subdev_string(pa_str, pa_ptr + strlen(pa_arg));
remove_substring(args, pa_arg);
remove_substring(args, pa_str);
pa_status = !strcmp(pa_str, "enabled");
LOG_I(HW, "[oxgrf] PA Status:%s\n", pa_status?"Enabled":"Disabled");
}
const char ant_arg[] = "rx_ant=";
char ant_str[64] = {0};
char *ant_ptr = strstr(args, ant_arg);
if(ant_ptr) {
copy_subdev_string(ant_str, ant_ptr + strlen(ant_arg));
remove_substring(args, ant_arg);
remove_substring(args, ant_str);
rx_ant = strcmp(ant_str, "trx");
}
char dstring[128];
if(RX_MTU < 30720) {
sprintf(dstring, ",nsamples_recv_frame:%u", RX_MTU);
strcat(dev_str, dstring);
}
if ((oxgrf->dev = oxgrf_open_device(dev_str)) == NULL ) {
LOG_E(HW, "[oxgrf] Failed to open oxgrf\n");
free(oxgrf);
return -1;
}
uint32_t model = 0;
oxgrf_get_model_version(oxgrf->dev, &model);
model &= 0xffff;
if(model == 550) {
oxgrf->BoardType = Y550;
shift = 4;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 230) {
oxgrf->BoardType = Y230;
shift = 4;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 380) {
oxgrf->BoardType = Y380;
shift = 4;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 590) {
oxgrf->BoardType = Y590;
shift = 2;
LOG_I(HW, "[oxgrf] device type: Y%d\n", model);
} else if(model == 7400) {
oxgrf->BoardType = IQX7400;
shift = 4;
LOG_I(HW, "[oxgrf] device type: IQX%d\n", model);
} else if(model == 7402) {
oxgrf->BoardType = IQX7402;
shift = 2;
LOG_I(HW, "[oxgrf] device type: IQX%d(Split Mode)\n", model - 2);
} else if(model == 6000 || model == 7000 || model == 7100) {
oxgrf->BoardType = IQX7000;
shift = 2;
LOG_I(HW, "[oxgrf] device type: IQX%d\n", model);
} else {
oxgrf->BoardType = UNKNOWN;
shift = 0;
LOG_I(HW, "[oxgrf] device type: unknown\n");
}
if(oxgrf->BoardType == Y230) {
switch ((int)openair0_cfg->sample_rate) {
#if 0
case 61440000:
openair0_cfg->samples_per_packet = 30720;
openair0_cfg->tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
case 46080000:
openair0_cfg->samples_per_packet = 23040;
openair0_cfg->tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
#endif
case 30720000:
openair0_cfg[0].samples_per_packet = 15360;
openair0_cfg[0].tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 23040000:
openair0_cfg[0].samples_per_packet = 11520;
openair0_cfg[0].tx_sample_advance = 80;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 15360000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 52;
openair0_cfg[0].tx_bw = 10e6;
openair0_cfg[0].rx_bw = 10e6;
break;
case 7680000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 34;
openair0_cfg[0].tx_bw = 5e6;
openair0_cfg[0].rx_bw = 5e6;
break;
case 3840000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 18;
openair0_cfg[0].tx_bw = 3e6;
openair0_cfg[0].rx_bw = 3e6;
break;
case 1920000:
openair0_cfg[0].samples_per_packet = 1920;
openair0_cfg[0].tx_sample_advance = 9;
openair0_cfg[0].tx_bw = 1.4e6;
openair0_cfg[0].rx_bw = 1.4e6;
break;
default:
LOG_I(HW, "[oxgrf] Error: unknown sampling rate %f\n", openair0_cfg->sample_rate);
free(oxgrf);
exit(-1);
break;
}
openair0_cfg[0].rx_gain_calib_table = calib_table_oxgrf;
set_rx_gain_offset(openair0_cfg, 0);
if(oxgrf->rx_num_channels > 1)
set_rx_gain_offset(openair0_cfg, 1);
}
if(oxgrf->BoardType == Y380
|| oxgrf->BoardType == Y550
|| oxgrf->BoardType == Y590
|| oxgrf->BoardType == IQX7000
|| oxgrf->BoardType == IQX7402
|| oxgrf->BoardType == IQX7400) {
switch ((int)openair0_cfg->sample_rate) {
case 122880000:
openair0_cfg[0].samples_per_packet = 30720;
openair0_cfg[0].tx_sample_advance = 574;
openair0_cfg[0].tx_bw = 100e6;
openair0_cfg[0].rx_bw = 100e6;
break;
case 61440000:
openair0_cfg[0].samples_per_packet = 30720;
openair0_cfg[0].tx_sample_advance = 287;
openair0_cfg[0].tx_bw = 40e6;
openair0_cfg[0].rx_bw = 40e6;
break;
case 30720000:
openair0_cfg[0].samples_per_packet = 15360;
openair0_cfg[0].tx_sample_advance = 144;
openair0_cfg[0].tx_bw = 20e6;
openair0_cfg[0].rx_bw = 20e6;
break;
case 15360000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 72;
openair0_cfg[0].tx_bw = 10e6;
openair0_cfg[0].rx_bw = 10e6;
break;
case 7680000:
openair0_cfg[0].samples_per_packet = 7680;
openair0_cfg[0].tx_sample_advance = 36;
openair0_cfg[0].tx_bw = 5e6;
openair0_cfg[0].rx_bw = 5e6;
break;
case 3840000:
openair0_cfg[0].samples_per_packet = 3840;
openair0_cfg[0].tx_sample_advance = 18;
openair0_cfg[0].tx_bw = 3e6;
openair0_cfg[0].rx_bw = 3e6;
break;
case 1920000:
openair0_cfg[0].samples_per_packet = 1920;
openair0_cfg[0].tx_sample_advance = 10;
openair0_cfg[0].tx_bw = 1.4e6;
openair0_cfg[0].rx_bw = 1.4e6;
break;
default:
LOG_I(HW, "[oxgrf] Error: unknown sampling rate %f\n", openair0_cfg->sample_rate);
free(oxgrf);
exit(-1);
break;
}
//openair0_cfg[0].rx_gain_calib_table = calib_table_oxgrf;
openair0_cfg[0].rx_gain_calib_table = calib_table_none;
set_rx_gain_offset(openair0_cfg, 0);
if(oxgrf->rx_num_channels > 1)
set_rx_gain_offset(openair0_cfg, 1);
}
LOG_I(HW, "[oxgrf] Initializing openair0_device\n");
switch (openair0_cfg[0].clock_source) {
case external:
LOG_I(HW, "[oxgrf] clock_source: external\n");
oxgrf_set_ref_clock (oxgrf->dev, 0, EXTERNAL_REFERENCE);
oxgrf_set_pps_select (oxgrf->dev, 0, PPS_EXTERNAL_EN);
break;
case gpsdo:
LOG_I(HW, "[oxgrf] clock_source: gpsdo\n");
break;
case internal:
default:
oxgrf_set_ref_clock (oxgrf->dev, 0, INTERNAL_REFERENCE);
oxgrf_set_pps_select (oxgrf->dev, 0, PPS_INTERNAL_EN);
//oxgrf_set_vco_select (oxgrf->dev, 0, AUXDAC1);
LOG_I(HW, "[oxgrf] clock_source: internal\n");
break;
}
oxgrf_set_auxdac1 (oxgrf->dev, 0, auxdac1);
if (pa_status) {
oxgrf_set_duplex_select (oxgrf->dev, 0, TO_OXGRF_OLD_VALUE(FDD));
oxgrf_set_trxsw_fpga_enable(oxgrf->dev, 0, 1);
oxgrf_set_rx_ant_enable (oxgrf->dev, 0, 0);
} else if (openair0_cfg->duplex_mode == duplex_mode_TDD && !rx_ant) {
oxgrf_set_duplex_select (oxgrf->dev, 0, TO_OXGRF_OLD_VALUE(TDD));
oxgrf_set_trxsw_fpga_enable(oxgrf->dev, 0, 1);
oxgrf_set_rx_ant_enable (oxgrf->dev, 0, 0);
} else {
oxgrf_set_duplex_select (oxgrf->dev, 0, TO_OXGRF_OLD_VALUE(FDD));
oxgrf_set_trxsw_fpga_enable(oxgrf->dev, 0, 0);
oxgrf_set_rx_ant_enable (oxgrf->dev, 0, 1);
}
LOG_I(HW, "[oxgrf] RX Ant:%s\n", rx_ant?"Enabled":"Disabled");
oxgrf_set_tx_fir_en_dis (oxgrf->dev, 0, 0);
oxgrf_set_rx_fir_en_dis (oxgrf->dev, 0, 0);
int max_idx = ((oxgrf->rx_num_channels > 2 || oxgrf->tx_num_channels > 2)? 1 : 0);
for(int chip_idx = 0; chip_idx <= max_idx; chip_idx++) {
// RX port Initialize
if ((status = oxgrf_set_rx_lo_freq(oxgrf->dev, chip_idx, (uint64_t)(openair0_cfg->rx_freq[0]))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX frequency\n");
} else
LOG_I(HW, "[oxgrf] set RX frequency to %lu\n",(uint64_t)(openair0_cfg->rx_freq[0]));
if ((status = oxgrf_set_rx_sampling_freq(oxgrf->dev, chip_idx, (uint32_t)(openair0_cfg->sample_rate))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX sample rate\n");
} else
LOG_I(HW, "[oxgrf] set RX sample rate to %u\n", (uint32_t)(openair0_cfg->sample_rate));
if ((status = oxgrf_set_rx_rf_bandwidth(oxgrf->dev, chip_idx, (uint32_t)(openair0_cfg->rx_bw))) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX bandwidth\n");
} else
LOG_I(HW, "[oxgrf] set RX bandwidth to %u\n",(uint32_t)(openair0_cfg->rx_bw));
if ((status = oxgrf_set_rx1_gain_control_mode(oxgrf->dev, chip_idx, 0)) < 0){
LOG_E(HW, "[oxgrf] Failed to set RX1 Gain Control Mode\n");
} else
LOG_I(HW, "[oxgrf] set RX1 Gain Control Mode MGC\n");
uint32_t rxgain = openair0_cfg->rx_gain[0] - openair0_cfg->rx_gain_offset[0];
if (openair0_cfg->rx_gain_offset[0] > 0) {
if (rxgain > 30)
rxgain = 60;
else
rxgain *= 2;
} else {
if (rxgain > 60)
rxgain = 60;
}
if ((status = oxgrf_set_rx1_rf_gain(oxgrf->dev, chip_idx, rxgain)) < 0) {
LOG_I(HW, "[oxgrf] Failed to set RX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX1 gain to %u\n", rxgain);
if ((status = oxgrf_set_rx2_gain_control_mode(oxgrf->dev, chip_idx, 0)) < 0){
LOG_E(HW, "[oxgrf] Failed to set RX2 Gain Control Mode\n");
} else
LOG_I(HW, "[oxgrf] set RX2 Gain Control Mode MGC\n");
if ((status = oxgrf_set_rx2_rf_gain(oxgrf->dev, chip_idx, rxgain)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set RX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set RX2 gain to %u\n", rxgain);
// TX port Initialize
if ((status = oxgrf_set_tx_lo_freq(oxgrf->dev, chip_idx, (uint64_t)openair0_cfg->tx_freq[0])) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX frequency\n");
} else
LOG_I(HW, "[oxgrf] set TX Frequency to %lu\n", (uint64_t)openair0_cfg->tx_freq[0]);
if ((status = oxgrf_set_tx_sampling_freq(oxgrf->dev, chip_idx, (uint32_t)openair0_cfg->sample_rate)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX sample rate\n");
} else
LOG_I(HW, "[oxgrf] set TX sampling rate to %u\n", (uint32_t)openair0_cfg->sample_rate);
if ((status = oxgrf_set_tx_rf_bandwidth(oxgrf->dev, chip_idx, (uint32_t)openair0_cfg->tx_bw)) <0) {
LOG_E(HW, "[oxgrf] Failed to set TX bandwidth\n");
} else
LOG_I(HW, "[oxgrf] set TX bandwidth to %u\n", (uint32_t)openair0_cfg->tx_bw);
if ((status = oxgrf_set_tx1_attenuation(oxgrf->dev, chip_idx, openair0_cfg->tx_gain[0] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX1 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX1 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[0]);
if ((status = oxgrf_set_tx2_attenuation(oxgrf->dev, chip_idx, openair0_cfg->tx_gain[1] * 1000)) < 0) {
LOG_E(HW, "[oxgrf] Failed to set TX2 gain\n");
} else
LOG_I(HW, "[oxgrf] set the TX2 gain to %d\n", 90 - (uint32_t)openair0_cfg->tx_gain[1]);
}
uint32_t depth = oxgrf->sample_rate / 100 * sizeof(int) * oxgrf->rx_num_channels;
oxgrf_set_hwbuf_depth(oxgrf->dev, 0, depth);
oxgrf_enable_timestamp(oxgrf->dev, 0, 0);
sleep(2);
oxgrf_enable_timestamp(oxgrf->dev, 0, 1);
sleep(2);
for(int i = 0; i < NCHAN_PER_DEV; i++) {
int ret = posix_memalign((void **)&cache_buf[i], 4096, BUFFER_SIZE);
if(ret) {
LOG_I(HW, "Failed to alloc memory\n");
return -1;
}
ret = posix_memalign((void **)&iq_buf[i], 4096, BUFFER_SIZE);
if(ret) {
LOG_I(HW, "Failed to alloc memory\n");
return -1;
}
}
device->Mod_id = num_devices++;
device->type = OXGRF_DEV;
device->trx_start_func = trx_oxgrf_start;
device->trx_end_func = trx_oxgrf_end;
device->trx_read_func = trx_oxgrf_read;
device->trx_write_func = trx_oxgrf_write;
device->trx_get_stats_func = trx_oxgrf_get_stats;
device->trx_reset_stats_func = trx_oxgrf_reset_stats;
device->trx_stop_func = trx_oxgrf_stop;
device->trx_set_freq_func = trx_oxgrf_set_freq;
device->trx_set_gains_func = trx_oxgrf_set_gains;
device->trx_write_init = trx_oxgrf_write_init;
device->openair0_cfg = openair0_cfg;
device->priv = (void *)oxgrf;
return 0;
}
/*@}*/
radio/OXGRF/rf_helper.h 0 → 100644
View file @ caeedc04
/*
* Copyright 2013-2020 Software Radio Systems Limited
*
* This file is part of srsLTE.
*
* srsLTE is free software: you can redistribute it and/or modify
* it under the terms of the GNU Affero General Public License as
* published by the Free Software Foundation, either version 3 of
* the License, or (at your option) any later version.
*
* srsLTE is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Affero General Public License for more details.
*
* A copy of the GNU Affero General Public License can be found in
* the LICENSE file in the top-level directory of this distribution
* and at http://www.gnu.org/licenses/.
*
*/
#ifndef OXGRF_RF_HELPER_H_
#define OXGRF_RF_HELPER_H_
// A bunch of helper functions to process device arguments
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define REMOVE_SUBSTRING_WITHCOMAS(S, TOREMOVE) \
remove_substring(S, TOREMOVE ","); \
remove_substring(S, TOREMOVE ", "); \
remove_substring(S, "," TOREMOVE); \
remove_substring(S, ", " TOREMOVE); \
remove_substring(S, TOREMOVE)
static inline void remove_substring(char* s, const char* toremove)
{
while ((s = strstr(s, toremove))) {
memmove(s, s + strlen(toremove), 1 + strlen(s + strlen(toremove)));
}
}
static inline void copy_subdev_string(char* dst, char* src)
{
int n = 0;
int len = (int)strlen(src);
/* Copy until end of string or comma */
while (n < len && src[n] != '\0' && src[n] != ',') {
dst[n] = src[n];
n++;
}
dst[n] = '\0';
}
#endif /* OXGRF_RF_HELPER_H_ */
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band38.tm1.100PRB.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_eNBs = ( "eNB_Eurecom_LTEBox");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
eNBs =
(
{
////////// Identification parameters:
eNB_ID = 0xe00;
cell_type = "CELL_MACRO_ENB";
eNB_name = "eNB_Eurecom_LTEBox";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ( { mcc = 001; mnc = 01; mnc_length = 2; } );
////////// Physical parameters:
component_carriers = (
{
node_function = "eNodeB_3GPP";
node_timing = "synch_to_ext_device";
node_synch_ref = 0;
frame_type = "TDD";
tdd_config = 1;
tdd_config_s = 0;
prefix_type = "NORMAL";
eutra_band = 38;
downlink_frequency = 2600000000L;
uplink_frequency_offset = 0;
Nid_cell = 0;
N_RB_DL = 100;
Nid_cell_mbsfn = 0;
nb_antenna_ports = 1;
nb_antennas_tx = 1;
nb_antennas_rx = 1;
tx_gain = 90;
rx_gain = 102;
prach_root = 0;
prach_config_index = 0;
prach_high_speed = "DISABLE";
prach_zero_correlation = 1;
prach_freq_offset = 2;
pucch_delta_shift = 1;
pucch_nRB_CQI = 1;
pucch_nCS_AN = 0;
pucch_n1_AN = 0;
pdsch_referenceSignalPower = -16;
pdsch_p_b = 0;
pusch_n_SB = 1;
pusch_enable64QAM = "DISABLE";
pusch_hoppingMode = "interSubFrame";
pusch_hoppingOffset = 0;
pusch_groupHoppingEnabled = "ENABLE";
pusch_groupAssignment = 0;
pusch_sequenceHoppingEnabled = "DISABLE";
pusch_nDMRS1 = 1;
phich_duration = "NORMAL";
phich_resource = "ONESIXTH";
srs_enable = "DISABLE";
/* srs_BandwidthConfig =;
srs_SubframeConfig =;
srs_ackNackST =;
srs_MaxUpPts =;*/
pusch_p0_Nominal = -90;
pusch_alpha = "AL1";
pucch_p0_Nominal = -108;
msg3_delta_Preamble = 6;
pucch_deltaF_Format1 = "deltaF2";
pucch_deltaF_Format1b = "deltaF3";
pucch_deltaF_Format2 = "deltaF0";
pucch_deltaF_Format2a = "deltaF0";
pucch_deltaF_Format2b = "deltaF0";
rach_numberOfRA_Preambles = 64;
rach_preamblesGroupAConfig = "DISABLE";
/*
rach_sizeOfRA_PreamblesGroupA = ;
rach_messageSizeGroupA = ;
rach_messagePowerOffsetGroupB = ;
*/
rach_powerRampingStep = 4;
rach_preambleInitialReceivedTargetPower = -108;
rach_preambleTransMax = 10;
rach_raResponseWindowSize = 10;
rach_macContentionResolutionTimer = 48;
rach_maxHARQ_Msg3Tx = 4;
pcch_default_PagingCycle = 128;
pcch_nB = "oneT";
bcch_modificationPeriodCoeff = 2;
ue_TimersAndConstants_t300 = 1000;
ue_TimersAndConstants_t301 = 1000;
ue_TimersAndConstants_t310 = 1000;
ue_TimersAndConstants_t311 = 10000;
ue_TimersAndConstants_n310 = 20;
ue_TimersAndConstants_n311 = 1;
ue_TransmissionMode = 1;
}
);
srb1_parameters :
{
# timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
timer_poll_retransmit = 80;
# timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
timer_reordering = 35;
# timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
timer_status_prohibit = 0;
# poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
poll_pdu = 4;
# poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
poll_byte = 99999;
# max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
max_retx_threshold = 4;
}
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// MME parameters:
mme_ip_address = ({ ipv4 = "127.0.1.100"; });
enable_measurement_reports = "no";
///X2
enable_x2 = "no";
t_reloc_prep = 1000; /* unit: millisecond */
tx2_reloc_overall = 2000; /* unit: millisecond */
t_dc_prep = 1000; /* unit: millisecond */
t_dc_overall = 2000; /* unit: millisecond */
NETWORK_INTERFACES :
{
ENB_IPV4_ADDRESS_FOR_S1_MME = "127.0.0.1/24";
ENB_IPV4_ADDRESS_FOR_S1U = "127.0.0.1/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152
ENB_IPV4_ADDRESS_FOR_X2C = "127.0.0.1/24";
ENB_PORT_FOR_X2C = 36422; # Spec 36422
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
puSch10xSnr = 200;
puCch10xSnr = 200;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 0
att_rx = 3;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 85;
eNB_instances = [0];
sdr_addrs = "dev=pciex:0,auxdac1=1620";
clock_src = "internal";
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
};
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band40.tm1.100PRB.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_eNBs = ( "eNB_Eurecom_LTEBox");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
eNBs =
(
{
////////// Identification parameters:
eNB_ID = 0xe00;
cell_type = "CELL_MACRO_ENB";
eNB_name = "eNB_Eurecom_LTEBox";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ( { mcc = 001; mnc = 01; mnc_length = 2; } );
////////// Physical parameters:
component_carriers = (
{
node_function = "eNodeB_3GPP";
node_timing = "synch_to_ext_device";
node_synch_ref = 0;
frame_type = "TDD";
tdd_config = 1;
tdd_config_s = 0;
prefix_type = "NORMAL";
eutra_band = 40;
downlink_frequency = 2350000000L;
uplink_frequency_offset = 0;
Nid_cell = 0;
N_RB_DL = 50;
Nid_cell_mbsfn = 0;
nb_antenna_ports = 1;
nb_antennas_tx = 1;
nb_antennas_rx = 1;
tx_gain = 90;
rx_gain = 102;
pbch_repetition = "FALSE";
prach_root = 0;
prach_config_index = 0;
prach_high_speed = "DISABLE";
prach_zero_correlation = 1;
prach_freq_offset = 2;
pucch_delta_shift = 1;
pucch_nRB_CQI = 1;
pucch_nCS_AN = 0;
pucch_n1_AN = 0;
pdsch_referenceSignalPower = -20;
pdsch_p_b = 0;
pusch_n_SB = 1;
pusch_enable64QAM = "DISABLE";
pusch_hoppingMode = "interSubFrame";
pusch_hoppingOffset = 0;
pusch_groupHoppingEnabled = "ENABLE";
pusch_groupAssignment = 0;
pusch_sequenceHoppingEnabled = "DISABLE";
pusch_nDMRS1 = 1;
phich_duration = "NORMAL";
phich_resource = "ONESIXTH";
srs_enable = "DISABLE";
/* srs_BandwidthConfig =;
srs_SubframeConfig =;
srs_ackNackST =;
srs_MaxUpPts =;*/
pusch_p0_Nominal = -104;
pusch_alpha = "AL1";
pucch_p0_Nominal = -96;
msg3_delta_Preamble = 6;
pucch_deltaF_Format1 = "deltaF2";
pucch_deltaF_Format1b = "deltaF3";
pucch_deltaF_Format2 = "deltaF0";
pucch_deltaF_Format2a = "deltaF0";
pucch_deltaF_Format2b = "deltaF0";
rach_numberOfRA_Preambles = 64;
rach_preamblesGroupAConfig = "DISABLE";
/*
rach_sizeOfRA_PreamblesGroupA = ;
rach_messageSizeGroupA = ;
rach_messagePowerOffsetGroupB = ;
*/
rach_powerRampingStep = 4;
rach_preambleInitialReceivedTargetPower = -108;
rach_preambleTransMax = 10;
rach_raResponseWindowSize = 10;
rach_macContentionResolutionTimer = 48;
rach_maxHARQ_Msg3Tx = 4;
pcch_default_PagingCycle = 128;
pcch_nB = "oneT";
bcch_modificationPeriodCoeff = 2;
ue_TimersAndConstants_t300 = 1000;
ue_TimersAndConstants_t301 = 1000;
ue_TimersAndConstants_t310 = 1000;
ue_TimersAndConstants_t311 = 10000;
ue_TimersAndConstants_n310 = 20;
ue_TimersAndConstants_n311 = 1;
ue_TransmissionMode = 1;
}
);
srb1_parameters :
{
# timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
timer_poll_retransmit = 80;
# timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
timer_reordering = 35;
# timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
timer_status_prohibit = 0;
# poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
poll_pdu = 4;
# poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
poll_byte = 99999;
# max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
max_retx_threshold = 4;
}
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// MME parameters:
mme_ip_address = ({ ipv4 = "127.0.1.100"; });
enable_measurement_reports = "no";
///X2
enable_x2 = "no";
t_reloc_prep = 1000; /* unit: millisecond */
tx2_reloc_overall = 2000; /* unit: millisecond */
t_dc_prep = 1000; /* unit: millisecond */
t_dc_overall = 2000; /* unit: millisecond */
NETWORK_INTERFACES :
{
ENB_IPV4_ADDRESS_FOR_S1_MME = "127.0.0.1/24";
ENB_IPV4_ADDRESS_FOR_S1U = "127.0.0.1/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152
ENB_IPV4_ADDRESS_FOR_X2C = "127.0.0.1/24";
ENB_PORT_FOR_X2C = 36422; # Spec 36422
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
puSch10xSnr = 200;
puCch10xSnr = 200;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 5
att_rx = 0;
bands = [40];
max_pdschReferenceSignalPower = -20;
max_rxgain = 82;
eNB_instances = [0];
sdr_addrs = "dev=pciex:0,auxdac1=1660";
clock_src = "internal";
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
};
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.100PRB.nsa.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_eNBs = ( "eNB_Eurecom_LTEBox");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
eNBs =
(
{
////////// Identification parameters:
eNB_ID = 0xe00;
cell_type = "CELL_MACRO_ENB";
eNB_name = "eNB_Eurecom_LTEBox";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ( { mcc = 001; mnc = 01; mnc_length = 2; } );
tr_s_preference = "local_mac"
////////// Physical parameters:
component_carriers = (
{
node_function = "eNodeB_3GPP";
node_timing = "synch_to_ext_device";
node_synch_ref = 0;
frame_type = "FDD";
tdd_config = 3;
tdd_config_s = 0;
prefix_type = "NORMAL";
eutra_band = 7;
downlink_frequency = 2680000000L;
uplink_frequency_offset = -120000000;
Nid_cell = 0;
N_RB_DL = 100;
Nid_cell_mbsfn = 0;
nb_antenna_ports = 1;
nb_antennas_tx = 1;
nb_antennas_rx = 1;
tx_gain = 89;
rx_gain = 102;
pbch_repetition = "FALSE";
prach_root = 0;
prach_config_index = 0;
prach_high_speed = "DISABLE";
prach_zero_correlation = 1;
prach_freq_offset = 2;
pucch_delta_shift = 1;
pucch_nRB_CQI = 1;
pucch_nCS_AN = 0;
pucch_n1_AN = 0;
pdsch_referenceSignalPower = -20;
pdsch_p_b = 0;
pusch_n_SB = 1;
pusch_enable64QAM = "DISABLE";
pusch_hoppingMode = "interSubFrame";
pusch_hoppingOffset = 0;
pusch_groupHoppingEnabled = "ENABLE";
pusch_groupAssignment = 0;
pusch_sequenceHoppingEnabled = "DISABLE";
pusch_nDMRS1 = 1;
phich_duration = "NORMAL";
phich_resource = "ONESIXTH";
srs_enable = "DISABLE";
/* srs_BandwidthConfig =;
srs_SubframeConfig =;
srs_ackNackST =;
srs_MaxUpPts =;*/
pusch_p0_Nominal = -96;
pusch_alpha = "AL1";
pucch_p0_Nominal = -104;
msg3_delta_Preamble = 6;
pucch_deltaF_Format1 = "deltaF2";
pucch_deltaF_Format1b = "deltaF3";
pucch_deltaF_Format2 = "deltaF0";
pucch_deltaF_Format2a = "deltaF0";
pucch_deltaF_Format2b = "deltaF0";
rach_numberOfRA_Preambles = 64;
rach_preamblesGroupAConfig = "DISABLE";
/*
rach_sizeOfRA_PreamblesGroupA = ;
rach_messageSizeGroupA = ;
rach_messagePowerOffsetGroupB = ;
*/
rach_powerRampingStep = 4;
rach_preambleInitialReceivedTargetPower = -94;
rach_preambleTransMax = 10;
rach_raResponseWindowSize = 10;
rach_macContentionResolutionTimer = 48;
rach_maxHARQ_Msg3Tx = 4;
pcch_default_PagingCycle = 128;
pcch_nB = "oneT";
bcch_modificationPeriodCoeff = 2;
ue_TimersAndConstants_t300 = 1000;
ue_TimersAndConstants_t301 = 1000;
ue_TimersAndConstants_t310 = 1000;
ue_TimersAndConstants_t311 = 10000;
ue_TimersAndConstants_n310 = 20;
ue_TimersAndConstants_n311 = 1;
ue_TransmissionMode = 1;
//Parameters for SIB18
rxPool_sc_CP_Len = "normal";
rxPool_sc_Period = "sf40";
rxPool_data_CP_Len = "normal";
rxPool_ResourceConfig_prb_Num = 20;
rxPool_ResourceConfig_prb_Start = 5;
rxPool_ResourceConfig_prb_End = 44;
rxPool_ResourceConfig_offsetIndicator_present = "prSmall";
rxPool_ResourceConfig_offsetIndicator_choice = 0;
rxPool_ResourceConfig_subframeBitmap_present = "prBs40";
rxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "00000000000000000000";
rxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
rxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
/* rxPool_dataHoppingConfig_hoppingParameter = 0;
rxPool_dataHoppingConfig_numSubbands = "ns1";
rxPool_dataHoppingConfig_rbOffset = 0;
rxPool_commTxResourceUC-ReqAllowed = "TRUE";
*/
// Parameters for SIB19
discRxPool_cp_Len = "normal"
discRxPool_discPeriod = "rf32"
discRxPool_numRetx = 1;
discRxPool_numRepetition = 2;
discRxPool_ResourceConfig_prb_Num = 5;
discRxPool_ResourceConfig_prb_Start = 3;
discRxPool_ResourceConfig_prb_End = 21;
discRxPool_ResourceConfig_offsetIndicator_present = "prSmall";
discRxPool_ResourceConfig_offsetIndicator_choice = 0;
discRxPool_ResourceConfig_subframeBitmap_present = "prBs40";
discRxPool_ResourceConfig_subframeBitmap_choice_bs_buf = "f0ffffffff";
discRxPool_ResourceConfig_subframeBitmap_choice_bs_size = 5;
discRxPool_ResourceConfig_subframeBitmap_choice_bs_bits_unused = 0;
}
);
srb1_parameters :
{
# timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
timer_poll_retransmit = 80;
# timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
timer_reordering = 35;
# timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
timer_status_prohibit = 0;
# poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
poll_pdu = 4;
# poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
poll_byte = 99999;
# max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
max_retx_threshold = 4;
}
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// MME parameters:
mme_ip_address = ({ ipv4 = "127.0.1.100"; });
enable_measurement_reports = "no";
///X2
enable_x2 = "yes";
t_reloc_prep = 1000; /* unit: millisecond */
tx2_reloc_overall = 2000; /* unit: millisecond */
t_dc_prep = 1000; /* unit: millisecond */
t_dc_overall = 2000; /* unit: millisecond */
NETWORK_INTERFACES :
{
ENB_IPV4_ADDRESS_FOR_S1_MME = "127.0.1.1/24";
ENB_IPV4_ADDRESS_FOR_S1U = "127.0.1.1/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152
ENB_IPV4_ADDRESS_FOR_X2C = "127.0.1.1/24";
ENB_PORT_FOR_X2C = 36422; # Spec 36422
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
phy_test_mode = 0;
puSch10xSnr = 200;
puCch10xSnr = 200;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 0
att_rx = 0;
bands = [7];
max_pdschReferenceSignalPower = -20;
max_rxgain = 83;
eNB_instances = [0];
sdr_addrs = "dev=pciex:0,auxdac1=1620";
clock_src = "internal";
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
/*
#example config for rfsimulator
rfsimulator :
{
serveraddr = "enb";
serverport = 4043;
options = ("saviq");
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
*/
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
};
targets/PROJECTS/GENERIC-LTE-EPC/CONF/enb.band7.tm1.100PRB.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_eNBs = ( "eNB_Eurecom_LTEBox");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
eNBs =
(
{
////////// Identification parameters:
eNB_ID = 0xe00;
cell_type = "CELL_MACRO_ENB";
eNB_name = "eNB_Eurecom_LTEBox";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ( { mcc = 001; mnc = 01; mnc_length = 2; } );
tr_s_preference = "local_mac"
////////// Physical parameters:
component_carriers = (
{
node_function = "eNodeB_3GPP";
node_timing = "synch_to_ext_device";
node_synch_ref = 0;
frame_type = "FDD";
tdd_config = 3;
tdd_config_s = 0;
prefix_type = "NORMAL";
eutra_band = 7;
downlink_frequency = 2680000000L;
uplink_frequency_offset = -120000000;
Nid_cell = 0;
N_RB_DL = 100;
Nid_cell_mbsfn = 0;
nb_antenna_ports = 1;
nb_antennas_tx = 1;
nb_antennas_rx = 1;
tx_gain = 90;
rx_gain = 102;
pbch_repetition = "FALSE";
prach_root = 0;
prach_config_index = 0;
prach_high_speed = "DISABLE";
prach_zero_correlation = 1;
prach_freq_offset = 2;
pucch_delta_shift = 1;
pucch_nRB_CQI = 1;
pucch_nCS_AN = 0;
pucch_n1_AN = 0;
pdsch_referenceSignalPower = -20;
pdsch_p_b = 0;
pusch_n_SB = 1;
pusch_enable64QAM = "DISABLE";
pusch_hoppingMode = "interSubFrame";
pusch_hoppingOffset = 0;
pusch_groupHoppingEnabled = "ENABLE";
pusch_groupAssignment = 0;
pusch_sequenceHoppingEnabled = "DISABLE";
pusch_nDMRS1 = 1;
phich_duration = "NORMAL";
phich_resource = "ONESIXTH";
srs_enable = "DISABLE";
/* srs_BandwidthConfig =;
srs_SubframeConfig =;
srs_ackNackST =;
srs_MaxUpPts =;*/
pusch_p0_Nominal = -76;
pusch_alpha = "AL1";
pucch_p0_Nominal = -96;
msg3_delta_Preamble = 6;
pucch_deltaF_Format1 = "deltaF2";
pucch_deltaF_Format1b = "deltaF3";
pucch_deltaF_Format2 = "deltaF0";
pucch_deltaF_Format2a = "deltaF0";
pucch_deltaF_Format2b = "deltaF0";
rach_numberOfRA_Preambles = 64;
rach_preamblesGroupAConfig = "DISABLE";
/*
rach_sizeOfRA_PreamblesGroupA = ;
rach_messageSizeGroupA = ;
rach_messagePowerOffsetGroupB = ;
*/
rach_powerRampingStep = 4;
rach_preambleInitialReceivedTargetPower = -90;
rach_preambleTransMax = 10;
rach_raResponseWindowSize = 10;
rach_macContentionResolutionTimer = 48;
rach_maxHARQ_Msg3Tx = 4;
pcch_default_PagingCycle = 128;
pcch_nB = "oneT";
bcch_modificationPeriodCoeff = 2;
ue_TimersAndConstants_t300 = 1000;
ue_TimersAndConstants_t301 = 1000;
ue_TimersAndConstants_t310 = 1000;
ue_TimersAndConstants_t311 = 10000;
ue_TimersAndConstants_n310 = 20;
ue_TimersAndConstants_n311 = 1;
ue_TransmissionMode = 1;
}
);
srb1_parameters :
{
# timer_poll_retransmit = (ms) [5, 10, 15, 20,... 250, 300, 350, ... 500]
timer_poll_retransmit = 80;
# timer_reordering = (ms) [0,5, ... 100, 110, 120, ... ,200]
timer_reordering = 35;
# timer_reordering = (ms) [0,5, ... 250, 300, 350, ... ,500]
timer_status_prohibit = 0;
# poll_pdu = [4, 8, 16, 32 , 64, 128, 256, infinity(>10000)]
poll_pdu = 4;
# poll_byte = (kB) [25,50,75,100,125,250,375,500,750,1000,1250,1500,2000,3000,infinity(>10000)]
poll_byte = 99999;
# max_retx_threshold = [1, 2, 3, 4 , 6, 8, 16, 32]
max_retx_threshold = 4;
}
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// MME parameters:
mme_ip_address = ({ ipv4 = "192.168.0.80"; });
enable_measurement_reports = "no";
///X2
enable_x2 = "no";
t_reloc_prep = 1000; /* unit: millisecond */
tx2_reloc_overall = 2000; /* unit: millisecond */
t_dc_prep = 1000; /* unit: millisecond */
t_dc_overall = 2000; /* unit: millisecond */
NETWORK_INTERFACES :
{
ENB_IPV4_ADDRESS_FOR_S1_MME = "192.168.0.201/24";
ENB_IPV4_ADDRESS_FOR_S1U = "192.168.0.201/24";
ENB_PORT_FOR_S1U = 2152; # Spec 2152
ENB_IPV4_ADDRESS_FOR_X2C = "192.168.0.201/24";
ENB_PORT_FOR_X2C = 36422; # Spec 36422
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
puSch10xSnr = 250;
puCch10xSnr = 250;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 0
att_rx = 0;
bands = [7];
max_pdschReferenceSignalPower = -20;
max_rxgain = 90;
eNB_instances = [0];
sdr_addrs = "dev=pciex:0,auxdac1=1660";
clock_src = "internal";
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
};
targets/PROJECTS/GENERIC-LTE-EPC/CONF/gnb.band78.tm1.106PRB.nsa.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-Eurecom-5GNRBox");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
cell_type = "CELL_MACRO_GNB";
gNB_name = "gNB-Eurecom-5GNRBox";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({mcc = 001; mnc = 01; mnc_length = 2;});
tr_s_preference = "local_mac"
////////// Physical parameters:
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3600 MHz + 84 PRBs@30kHz SCS (same as initial BWP)
absoluteFrequencySSB = 641272; //641032; #641968; 641968=start of ssb at 3600MHz + 82 RBs 641032=center of SSB at center of cell
dl_frequencyBand = 78;
# this is 3600 MHz
dl_absoluteFrequencyPointA = 640000;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=84,L=13 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 6368;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 0;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 6368;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 13;
preambleReceivedTargetPower = -100;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#0 = 839, 1 = 139
prach_RootSequenceIndex_PR = 1;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -90;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// MME parameters:
mme_ip_address = ({ ipv4 = "127.0.1.100"; });
///X2
enable_x2 = "yes";
t_reloc_prep = 1000; /* unit: millisecond */
tx2_reloc_overall = 2000; /* unit: millisecond */
t_dc_prep = 1000; /* unit: millisecond */
t_dc_overall = 2000; /* unit: millisecond */
target_enb_x2_ip_address = (
{ ipv4 = "127.0.1.1";
ipv6 = "192:168:30::17";
preference = "ipv4";
}
);
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "127.0.1.2/24";
GNB_IPV4_ADDRESS_FOR_NGU = "127.0.1.2/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
GNB_IPV4_ADDRESS_FOR_X2C = "127.0.1.2/24";
GNB_PORT_FOR_X2C = 36422; # Spec 36422
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 0
att_rx = 0;
bands = [7];
max_pdschReferenceSignalPower = -27;
max_rxgain = 102;
eNB_instances = [0];
sdr_addrs = "dev=pciex:1,auxdac1=1620";
clock_src = "external";
}
);
THREAD_STRUCT = (
{
#three config for level of parallelism "PARALLEL_SINGLE_THREAD", "PARALLEL_RU_L1_SPLIT", or "PARALLEL_RU_L1_TRX_SPLIT"
parallel_config = "PARALLEL_SINGLE_THREAD";
#two option for worker "WORKER_DISABLE" or "WORKER_ENABLE"
worker_config = "WORKER_ENABLE";
}
);
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb-cu.sa.f1.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "cu-oxgrf");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "cu-oxgrf";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
@include "neighbour-config-ho.conf"
nr_cellid = 12345678L;
tr_s_preference = "f1";
local_s_address = "127.0.0.3";
#local_s_address = "192.168.0.203";
remote_s_address = "0.0.0.0"; # multiple DUs
local_s_portd = 2152;
remote_s_portd = 2152;
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "127.0.1.100"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "127.0.1.1/24";
GNB_IPV4_ADDRESS_FOR_NGU = "127.0.1.1/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config : {
global_log_level = "info";
pdcp_log_level = "info";
rrc_log_level = "info";
f1ap_log_level = "info";
ngap_log_level = "info";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb-du.sa.band78.106prb.oxgrf.pci0.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "du-oxgrf");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_DU_ID = 0xe00;
gNB_name = "du-oxgrf";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
nr_cellid = 12345678L;
////////// Physical parameters:
min_rxtxtime = 4;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP)
absoluteFrequencySSB = 643200;
dl_frequencyBand = 78;
# this is 3600 MHz
dl_absoluteFrequencyPointA = 640016;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 13;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -90;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
}
);
MACRLCs = ({
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "f1";
local_n_address = "127.0.0.4";
remote_n_address = "127.0.0.3";
local_n_portd = 2152;
remote_n_portd = 2152;
pusch_FailureThres = 1000;
});
L1s = ({
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 200;
pucch0_dtx_threshold = 150;
ofdm_offset_divisor = 8; #set this to UINT_MAX for offset 0
});
RUs = ({
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 114;
eNB_instances = [0];
clock_src = "internal";
});
rfsimulator: {
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs"
}
log_config: {
global_log_level = "info";
hw_log_level = "info";
nr_phy_log_level = "info";
nr_mac_log_level = "info";
rlc_log_level = "info";
pdcp_log_level = "info";
rrc_log_level = "info";
f1ap_log_level = "info";
ngap_log_level = "debug";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.u3.132prb.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
sa = 1;
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 1;
pusch_AntennaPorts = 1;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 8;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# This is 27999.840 MHz (GSCN: 22473)
absoluteFrequencySSB = 2079163;
dl_frequencyBand = 257;
# This is 27952.560 MHz
dl_absoluteFrequencyPointA = 2077583;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 3;
dl_carrierBandwidth = 132;
#initialDownlinkBWP
#genericParameters
# This is RBstart = 0, L = 32: (275 * (L - 1)) + RBstart
initialDLBWPlocationAndBandwidth = 36025;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 3;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 0;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 257;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 3;
ul_carrierBandwidth = 132;
pMax = 10;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 36025;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 3;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 59;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -110;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 3;
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant = -84;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -96;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 3;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 3;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 3;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "127.0.0.5"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "127.0.1.100/24";
GNB_IPV4_ADDRESS_FOR_NGU = "127.0.1.100/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 300;
#pucch_TargetSNRx10 = 200;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes";
nb_tx = 1;
nb_rx = 1;
att_tx = 0;
att_rx = 0;
#sl_ahead = 12;
bands = [257];
max_pdschReferenceSignalPower = -27;
max_rxgain = 60;
eNB_instances = [0];
#if_freq = 3649380000L;
if_freq = 3500080000L;
clock_src = "internal";
sdr_addrs = "dev=pciex:0,auxdac1=1660";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="info";
f1ap_log_level ="info";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.u3.32prb.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
sa = 1;
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 1;
pusch_AntennaPorts = 1;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 6;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# This is 27510.240 MHz + 16 * 12 * 120e3 MHz = 27533.280 MHz (GSCN: 22446)
absoluteFrequencySSB = 2071387;
dl_frequencyBand = 257;
# This is 27510.240 MHz
dl_absoluteFrequencyPointA = 2071003;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 3;
dl_carrierBandwidth = 32;
#initialDownlinkBWP
#genericParameters
# This is RBstart = 0, L = 32: (275 * (L - 1)) + RBstart
initialDLBWPlocationAndBandwidth = 8525;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 3;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 0;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 257;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 3;
ul_carrierBandwidth = 32;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 8525;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 3;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 59;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 3;
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 3;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 3;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 3;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -10; #IQX7400
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "192.168.0.80"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "192.168.0.201/24";
GNB_IPV4_ADDRESS_FOR_NGU = "192.168.0.201/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 150;
#pucch_TargetSNRx10 = 200;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes";
nb_tx = 1;
nb_rx = 1;
att_tx = 0;
att_rx = 0;
#sl_ahead = 12;
bands = [257];
max_pdschReferenceSignalPower = -10;
max_rxgain = 102;
eNB_instances = [0];
if_freq = 3000280000L;
clock_src = "internal";
sdr_addrs = "dev=pciex:0,auxdac1=1660";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="info";
f1ap_log_level ="info";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band257.u3.66prb.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
sa = 1;
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 1;
pusch_AntennaPorts = 1;
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 8;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# This is 27999.840 MHz (GSCN: 22473)
absoluteFrequencySSB = 2079163;
dl_frequencyBand = 257;
# This is 27952.560 MHz
dl_absoluteFrequencyPointA = 2078375;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 3;
dl_carrierBandwidth = 66;
#initialDownlinkBWP
#genericParameters
# This is RBstart = 0, L = 32: (275 * (L - 1)) + RBstart
initialDLBWPlocationAndBandwidth = 17875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 3;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 0;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 257;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 3;
ul_carrierBandwidth = 66;
pMax = 10;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 17875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 3;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 59;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -110;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 3;
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant = -84;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -96;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 3;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 3;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 1;
nrofDownlinkSlots = 3;
nrofDownlinkSymbols = 10;
nrofUplinkSlots = 1;
nrofUplinkSymbols = 2;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "127.0.0.5"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "127.0.1.100/24";
GNB_IPV4_ADDRESS_FOR_NGU = "127.0.1.100/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 300;
#pucch_TargetSNRx10 = 200;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
#pucch0_dtx_threshold = 120;
}
);
RUs = (
{
local_rf = "yes";
nb_tx = 1;
nb_rx = 1;
att_tx = 0;
att_rx = 0;
#sl_ahead = 12;
bands = [257];
max_pdschReferenceSignalPower = -27;
max_rxgain = 60;
eNB_instances = [0];
#if_freq = 3649380000L;
if_freq = 3500080000L;
clock_src = "internal";
sdr_addrs = "dev=pciex:0,auxdac1=1660";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="info";
f1ap_log_level ="info";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band41.fr1.52PRB.oxgrf.y230.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
nr_cellid = 12345678L;
////////// Physical parameters:
do_CSIRS = 1;
do_SRS = 1;
min_rxtxtime = 6;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 2574.270 MHz + 53 PRBs@30kHz SCS (same as initial BWP)
absoluteFrequencySSB = 518670;
dl_frequencyBand = 41;
# this is 3600 MHz
dl_absoluteFrequencyPointA = 517734;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 0;
dl_carrierBandwidth = 52;
#initialDownlinkBWP
#genericParameters
# this is RBstart=0,L=106 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 14025; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 0;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 6;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 41;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 0;
ul_carrierBandwidth = 52;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 14025;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 0;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 13;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 15;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 0,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -90;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 0;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 0;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 7;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "192.168.0.80"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "192.168.0.201/24";
GNB_IPV4_ADDRESS_FOR_NGU = "192.168.0.201/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
pusch_TargetSNRx10 = 250;
pucch_TargetSNRx10 = 300;
pusch_FailureThres = 1000;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
pusch_proc_threads = 8;
prach_dtx_threshold = 120;
pucch0_dtx_threshold = 150;
ofdm_offset_divisor = 8; #set this to UINT_MAX for offset 0
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 0;
att_rx = 0;
bands = [41];
max_pdschReferenceSignalPower = -27;
max_rxgain = 102;
eNB_instances = [0];
sdr_addrs = "dev=usb3:0,auxdac1=1960";
clock_src = "internal";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
global_log_verbosity ="medium";
hw_log_level ="info";
hw_log_verbosity ="medium";
phy_log_level ="info";
phy_log_verbosity ="medium";
mac_log_level ="info";
mac_log_verbosity ="high";
rlc_log_level ="info";
rlc_log_verbosity ="medium";
pdcp_log_level ="info";
pdcp_log_verbosity ="medium";
rrc_log_level ="info";
rrc_log_verbosity ="medium";
ngap_log_level ="debug";
ngap_log_verbosity ="medium";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.2x2.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.60 MHz + 53*12*30e-3 MHz = 3319.68
absoluteFrequencySSB = 621312; # 641280
dl_frequencyBand = 78;
# this is 3300.60 MHz
dl_absoluteFrequencyPointA = 620040; # 640008
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "192.168.70.132"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "192.168.70.129/24";
GNB_IPV4_ADDRESS_FOR_NGU = "192.168.70.129/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
pusch_TargetSNRx10 = 150;
pucch_TargetSNRx10 = 200;
pusch_FailureThres = 1000;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
pucch0_dtx_threshold = 100;
ofdm_offset_divisor = 8; #set this to UINT_MAX for offset 0
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2
nb_rx = 2
att_tx = 0
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 102;
eNB_instances = [0];
clock_src = "internal";
sdr_addrs = "dev=pciex:0,auxdac1=1630";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="debug";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.106PRB.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }) });
nr_cellid = 12345678L;
////////// Physical parameters:
do_CSIRS = 1;
do_SRS = 1;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3600 MHz + 43 PRBs@30kHz SCS (same as initial BWP)
absoluteFrequencySSB = 641280;
dl_frequencyBand = 78;
# this is 3600 MHz
dl_absoluteFrequencyPointA = 640008;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 106;
#initialDownlinkBWP
#genericParameters
# this is RBstart=27,L=48 (275*(L-1))+RBstart
initialDLBWPlocationAndBandwidth = 28875; # 6366 12925 12956 28875 12952
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 106;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 28875;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 13;
preambleReceivedTargetPower = -96;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant =-90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -90;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "192.168.70.132"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "192.168.70.129/24";
GNB_IPV4_ADDRESS_FOR_NGU = "192.168.70.129/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
pusch_TargetSNRx10 = 150;
pucch_TargetSNRx10 = 200;
pusch_FailureThres = 1000;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
pucch0_dtx_threshold = 100;
ofdm_offset_divisor = 8; #set this to UINT_MAX for offset 0
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1
nb_rx = 1
att_tx = 0;
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 102;
eNB_instances = [0];
sdr_addrs = "dev=pciex:0,auxdac1=1660";
clock_src = "internal";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="debug";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.273PRB.2x2.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 1;
plmn_list = ({ mcc = 001; mnc = 01; mnc_length = 2; snssaiList = ({ sst = 1; }); });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 2;
pusch_AntennaPorts = 2;
do_CSIRS = 1;
do_SRS = 1;
ul_prbblacklist = "135,136,137,138"
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3648 MHz (5G NR GSCN: 7949)
absoluteFrequencySSB = 643200;
dl_frequencyBand = 78;
# this is 3600.24 MHz
dl_absoluteFrequencyPointA = 640016;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 273;
#initialDownlinkBWP
#genericParameters
initialDLBWPlocationAndBandwidth = 1099;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 273;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 1099;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -90;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant = -90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "192.168.0.80"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "192.168.0.201/24";
GNB_IPV4_ADDRESS_FOR_NGU = "192.168.0.201/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 300;
#pucch_TargetSNRx10 = 200;
pusch_FailureThres = 1000;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
pucch0_dtx_threshold = 80;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 2;
nb_rx = 2;
att_tx = 0;
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 60;
eNB_instances = [0];
#clock_src = "internal";
sdr_addrs = "dev=pciex:0,auxdac1=1630";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="debug";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/gnb.sa.band78.fr1.273PRB.oxgrf.conf 0 → 100644
View file @ caeedc04
Active_gNBs = ( "gNB-OAI");
# Asn1_verbosity, choice in: none, info, annoying
Asn1_verbosity = "none";
gNBs =
(
{
////////// Identification parameters:
gNB_ID = 0xe00;
gNB_name = "gNB-OAI";
// Tracking area code, 0x0000 and 0xfffe are reserved values
tracking_area_code = 100;
plmn_list = ({ mcc = 466; mnc = 92; mnc_length = 2; snssaiList = ({ sst = 1; }); });
nr_cellid = 12345678L;
////////// Physical parameters:
pdsch_AntennaPorts_XP = 1;
pusch_AntennaPorts = 1;
do_CSIRS = 1;
do_SRS = 0;
ul_prbblacklist = "135,136,137,138"
min_rxtxtime = 6;
servingCellConfigCommon = (
{
#spCellConfigCommon
physCellId = 0;
# downlinkConfigCommon
#frequencyInfoDL
# this is 3300.24 + 134*12*30e3 = 3348.48 MHz (5G NR GSCN: 7741)
absoluteFrequencySSB = 643200;
dl_frequencyBand = 78;
# this is 3300.24 MHz
dl_absoluteFrequencyPointA = 640016;
#scs-SpecificCarrierList
dl_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
dl_subcarrierSpacing = 1;
dl_carrierBandwidth = 273;
#initialDownlinkBWP
#genericParameters
initialDLBWPlocationAndBandwidth = 1099;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialDLBWPsubcarrierSpacing = 1;
#pdcch-ConfigCommon
initialDLBWPcontrolResourceSetZero = 12;
initialDLBWPsearchSpaceZero = 0;
#uplinkConfigCommon
#frequencyInfoUL
ul_frequencyBand = 78;
#scs-SpecificCarrierList
ul_offstToCarrier = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
ul_subcarrierSpacing = 1;
ul_carrierBandwidth = 273;
pMax = 20;
#initialUplinkBWP
#genericParameters
initialULBWPlocationAndBandwidth = 1099;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
initialULBWPsubcarrierSpacing = 1;
#rach-ConfigCommon
#rach-ConfigGeneric
prach_ConfigurationIndex = 98;
#prach_msg1_FDM
#0 = one, 1=two, 2=four, 3=eight
prach_msg1_FDM = 0;
prach_msg1_FrequencyStart = 0;
zeroCorrelationZoneConfig = 12;
preambleReceivedTargetPower = -90;
#preamblTransMax (0...10) = (3,4,5,6,7,8,10,20,50,100,200)
preambleTransMax = 6;
#powerRampingStep
# 0=dB0,1=dB2,2=dB4,3=dB6
powerRampingStep = 1;
#ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR
#1=oneeighth,2=onefourth,3=half,4=one,5=two,6=four,7=eight,8=sixteen
ssb_perRACH_OccasionAndCB_PreamblesPerSSB_PR = 4;
#one (0..15) 4,8,12,16,...60,64
ssb_perRACH_OccasionAndCB_PreamblesPerSSB = 14;
#ra_ContentionResolutionTimer
#(0..7) 8,16,24,32,40,48,56,64
ra_ContentionResolutionTimer = 7;
rsrp_ThresholdSSB = 19;
#prach-RootSequenceIndex_PR
#1 = 839, 2 = 139
prach_RootSequenceIndex_PR = 2;
prach_RootSequenceIndex = 1;
# SCS for msg1, can only be 15 for 30 kHz < 6 GHz, takes precendence over the one derived from prach-ConfigIndex
#
msg1_SubcarrierSpacing = 1,
# restrictedSetConfig
# 0=unrestricted, 1=restricted type A, 2=restricted type B
restrictedSetConfig = 0,
msg3_DeltaPreamble = 1;
p0_NominalWithGrant = -90;
# pucch-ConfigCommon setup :
# pucchGroupHopping
# 0 = neither, 1= group hopping, 2=sequence hopping
pucchGroupHopping = 0;
hoppingId = 40;
p0_nominal = -70;
ssb_PositionsInBurst_Bitmap = 1;
# ssb_periodicityServingCell
# 0 = ms5, 1=ms10, 2=ms20, 3=ms40, 4=ms80, 5=ms160, 6=spare2, 7=spare1
ssb_periodicityServingCell = 2;
# dmrs_TypeA_position
# 0 = pos2, 1 = pos3
dmrs_TypeA_Position = 0;
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
subcarrierSpacing = 1;
#tdd-UL-DL-ConfigurationCommon
# subcarrierSpacing
# 0=kHz15, 1=kHz30, 2=kHz60, 3=kHz120
referenceSubcarrierSpacing = 1;
# pattern1
# dl_UL_TransmissionPeriodicity
# 0=ms0p5, 1=ms0p625, 2=ms1, 3=ms1p25, 4=ms2, 5=ms2p5, 6=ms5, 7=ms10
dl_UL_TransmissionPeriodicity = 6;
nrofDownlinkSlots = 7;
nrofDownlinkSymbols = 6;
nrofUplinkSlots = 2;
nrofUplinkSymbols = 4;
ssPBCH_BlockPower = -25;
}
);
# ------- SCTP definitions
SCTP :
{
# Number of streams to use in input/output
SCTP_INSTREAMS = 2;
SCTP_OUTSTREAMS = 2;
};
////////// AMF parameters:
amf_ip_address = ({ ipv4 = "172.11.200.14"; });
NETWORK_INTERFACES :
{
GNB_IPV4_ADDRESS_FOR_NG_AMF = "172.11.200.1/24";
GNB_IPV4_ADDRESS_FOR_NGU = "172.11.200.1/24";
GNB_PORT_FOR_S1U = 2152; # Spec 2152
};
}
);
MACRLCs = (
{
num_cc = 1;
tr_s_preference = "local_L1";
tr_n_preference = "local_RRC";
#pusch_TargetSNRx10 = 300;
#pucch_TargetSNRx10 = 200;
pusch_FailureThres = 1000;
}
);
L1s = (
{
num_cc = 1;
tr_n_preference = "local_mac";
prach_dtx_threshold = 120;
pucch0_dtx_threshold = 80;
}
);
RUs = (
{
local_rf = "yes"
nb_tx = 1;
nb_rx = 1;
att_tx = 0;
att_rx = 0;
bands = [78];
max_pdschReferenceSignalPower = -27;
max_rxgain = 60;
eNB_instances = [0];
#clock_src = "internal";
sdr_addrs = "dev=pciex:0,auxdac1=1488";
}
);
rfsimulator :
{
serveraddr = "server";
serverport = 4043;
options = (); #("saviq"); or/and "chanmod"
modelname = "AWGN";
IQfile = "/tmp/rfsimulator.iqs";
};
security = {
# preferred ciphering algorithms
# the first one of the list that an UE supports in chosen
# valid values: nea0, nea1, nea2, nea3
ciphering_algorithms = ( "nea0" );
# preferred integrity algorithms
# the first one of the list that an UE supports in chosen
# valid values: nia0, nia1, nia2, nia3
integrity_algorithms = ( "nia2", "nia0" );
# setting 'drb_ciphering' to "no" disables ciphering for DRBs, no matter
# what 'ciphering_algorithms' configures; same thing for 'drb_integrity'
drb_ciphering = "yes";
drb_integrity = "no";
};
log_config :
{
global_log_level ="info";
hw_log_level ="info";
phy_log_level ="info";
mac_log_level ="info";
rlc_log_level ="info";
pdcp_log_level ="info";
rrc_log_level ="info";
ngap_log_level ="debug";
f1ap_log_level ="debug";
};
targets/PROJECTS/GENERIC-NR-5GC/CONF/neighbour-config-ho.conf 0 → 100644
View file @ caeedc04
neighbour_list = (
{
nr_cellid = 12345678;
neighbour_cell_configuration = (
{
gNB_ID = 0xe01;
nr_cellid = 11111111;
physical_cellId = 1;
absoluteFrequencySSB = 643200;
subcarrierSpacing = 1; #30 KHz
band = 78;
plmn = { mcc = 001; mnc = 01; mnc_length = 2};
tracking_area_code = 1;
}
)
},
{
nr_cellid = 11111111;
neighbour_cell_configuration = (
{
gNB_ID = 0xe00;
nr_cellid = 12345678;
physical_cellId = 0;
absoluteFrequencySSB = 643200;
subcarrierSpacing = 1; #30 KHz
band = 78;
plmn = { mcc = 001; mnc = 01; mnc_length = 2};
tracking_area_code = 1;
}
)
}
);
nr_measurement_configuration = {
Periodical = {
enable = 1;
includeBeamMeasurements = 1;
maxNrofRS_IndexesToReport = 4;
};
A2 = {
enable = 1;
threshold = 110;
timeToTrigger = 1;
};
A3 = ({
cell_id = -1; #Default
offset = 10;
hysteresis = 0;
timeToTrigger = 1
}, {
physCellId = 0;
offset = 5;
hysteresis = 1;
timeToTrigger = 2
}, {
physCellId = 1;
offset = 5;
hysteresis = 1;
timeToTrigger = 2
})
};
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