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OpenXG
OpenXG-RAN
Commits
d3f90a90
Commit
d3f90a90
authored
3 years ago
by
francescomani
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removing calculate_preferred_ul_tda
parent
276b2d5e
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v2.2.0
v2.1.0
v2.0.0
flexran-eol
ARC_1.3
No related merge requests found
Changes
8
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8 changed files
with
45 additions
and
172 deletions
+45
-172
openair2/LAYER2/NR_MAC_gNB/config.c
openair2/LAYER2/NR_MAC_gNB/config.c
+1
-11
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
+1
-2
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
+1
-1
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
+2
-3
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
+14
-127
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
+1
-1
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
+0
-4
openair2/RRC/NR/nr_rrc_config.c
openair2/RRC/NR/nr_rrc_config.c
+25
-23
No files found.
openair2/LAYER2/NR_MAC_gNB/config.c
View file @
d3f90a90
...
@@ -592,19 +592,9 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
...
@@ -592,19 +592,9 @@ int rrc_mac_config_req_gNB(module_id_t Mod_idP,
if
(
CellGroup
)
{
if
(
CellGroup
)
{
const
NR_ServingCellConfig_t
*
servingCellConfig
=
NULL
;
const
NR_ServingCellConfig_t
*
servingCellConfig
=
NULL
;
if
(
CellGroup
->
spCellConfig
&&
CellGroup
->
spCellConfig
->
spCellConfigDedicated
)
{
if
(
CellGroup
->
spCellConfig
&&
CellGroup
->
spCellConfig
->
spCellConfigDedicated
)
servingCellConfig
=
CellGroup
->
spCellConfig
->
spCellConfigDedicated
;
servingCellConfig
=
CellGroup
->
spCellConfig
->
spCellConfigDedicated
;
const
struct
NR_UplinkConfig__uplinkBWP_ToAddModList
*
ubwpList
=
servingCellConfig
->
uplinkConfig
->
uplinkBWP_ToAddModList
;
if
(
ubwpList
)
{
AssertFatal
(
ubwpList
->
list
.
count
>
0
,
"uplinkBWP_ToAddModList no BWPs!
\n
"
);
for
(
int
i
=
0
;
i
<
ubwpList
->
list
.
count
;
++
i
)
{
const
NR_BWP_Uplink_t
*
ubwp
=
ubwpList
->
list
.
array
[
i
];
calculate_preferred_ul_tda
(
Mod_idP
,
ubwp
);
}
}
}
NR_UE_info_t
*
UE_info
=
&
RC
.
nrmac
[
Mod_idP
]
->
UE_info
;
NR_UE_info_t
*
UE_info
=
&
RC
.
nrmac
[
Mod_idP
]
->
UE_info
;
if
(
add_ue
==
1
&&
get_softmodem_params
()
->
phy_test
)
{
if
(
add_ue
==
1
&&
get_softmodem_params
()
->
phy_test
)
{
const
int
UE_id
=
add_new_nr_ue
(
Mod_idP
,
rnti
,
CellGroup
);
const
int
UE_id
=
add_new_nr_ue
(
Mod_idP
,
rnti
,
CellGroup
);
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_dlsch.c
View file @
d3f90a90
...
@@ -60,8 +60,7 @@ const int set_dl_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int
...
@@ -60,8 +60,7 @@ const int set_dl_tda(gNB_MAC_INST *nrmac, NR_ServingCellConfigCommon_t *scc, int
scc
->
tdd_UL_DL_ConfigurationCommon
?
&
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
:
NULL
;
scc
->
tdd_UL_DL_ConfigurationCommon
?
&
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
:
NULL
;
if
(
tdd
)
{
if
(
tdd
)
{
int
nr_mix_slots
=
tdd
->
nrofDownlinkSymbols
!=
0
;
// there are dl symbols in mixed slot
if
(
tdd
->
nrofDownlinkSymbols
>
1
)
{
// if there is a mixed slot where we can transmit DL
if
(
nr_mix_slots
!=
0
)
{
// if there is a mixed slot
int
nr_slots_period
=
n
/
get_nb_periods_per_frame
(
tdd
->
dl_UL_TransmissionPeriodicity
);
int
nr_slots_period
=
n
/
get_nb_periods_per_frame
(
tdd
->
dl_UL_TransmissionPeriodicity
);
if
((
slot
%
nr_slots_period
)
==
tdd
->
nrofDownlinkSlots
)
if
((
slot
%
nr_slots_period
)
==
tdd
->
nrofDownlinkSlots
)
return
1
;
return
1
;
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_phytest.c
View file @
d3f90a90
...
@@ -436,7 +436,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
...
@@ -436,7 +436,7 @@ bool nr_ul_preprocessor_phytest(module_id_t module_id, frame_t frame, sub_frame_
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
NR_UE_sched_ctrl_t
*
sched_ctrl
=
&
UE_info
->
UE_sched_ctrl
[
UE_id
];
const
int
tda
=
s
ched_ctrl
->
active_ubwp
?
RC
.
nrmac
[
module_id
]
->
preferred_ul_tda
[
sched_ctrl
->
active_ubwp
->
bwp_Id
][
slot
]
:
1
;
const
int
tda
=
s
et_ul_tda
(
nr_mac
,
scc
,
slot
)
;
if
(
tda
<
0
)
if
(
tda
<
0
)
return
false
;
return
false
;
const
struct
NR_PUSCH_TimeDomainResourceAllocationList
*
tdaList
=
const
struct
NR_PUSCH_TimeDomainResourceAllocationList
*
tdaList
=
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_primitives.c
View file @
d3f90a90
...
@@ -2917,14 +2917,13 @@ void nr_mac_update_timers(module_id_t module_id,
...
@@ -2917,14 +2917,13 @@ void nr_mac_update_timers(module_id_t module_id,
cg
->
spCellConfig
->
spCellConfigDedicated
&&
cg
->
spCellConfig
->
spCellConfigDedicated
&&
cg
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
?
cg
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
?
cg
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
initialUplinkBWP
:
NULL
;
cg
->
spCellConfig
->
spCellConfigDedicated
->
uplinkConfig
->
initialUplinkBWP
:
NULL
;
int
**
preferred_ul_tda
=
RC
.
nrmac
[
module_id
]
->
preferred_ul_tda
;
NR_pusch_semi_static_t
*
ups
=
&
sched_ctrl
->
pusch_semi_static
;
NR_pusch_semi_static_t
*
ups
=
&
sched_ctrl
->
pusch_semi_static
;
int
dci_format
=
get_dci_format
(
sched_ctrl
);
int
dci_format
=
get_dci_format
(
sched_ctrl
);
const
uint8_t
num_dmrs_cdm_grps_no_data
=
(
ubwp
||
ubwpd
)
?
1
:
2
;
const
uint8_t
num_dmrs_cdm_grps_no_data
=
(
ubwp
||
ubwpd
)
?
1
:
2
;
const
uint8_t
nrOfLayers
=
1
;
const
uint8_t
nrOfLayers
=
1
;
const
int
utda
=
ubwp
&&
preferred_ul_tda
[
ubwp
->
bwp_Id
][
slot
]
>=
0
?
const
int
utda
=
set_ul_tda
(
RC
.
nrmac
[
module_id
],
scc
,
slot
);
preferred_ul_tda
[
ubwp
->
bwp_Id
][
slot
]
:
(
ups
->
time_domain_allocation
>=
0
?
ups
->
time_domain_allocation
:
0
);
nr_set_pusch_semi_static
(
sib1
,
nr_set_pusch_semi_static
(
sib1
,
scc
,
scc
,
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/gNB_scheduler_ulsch.c
View file @
d3f90a90
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/mac_proto.h
View file @
d3f90a90
...
@@ -523,7 +523,7 @@ uint8_t set_dl_nrOfLayers(NR_UE_sched_ctrl_t *sched_ctrl);
...
@@ -523,7 +523,7 @@ uint8_t set_dl_nrOfLayers(NR_UE_sched_ctrl_t *sched_ctrl);
int
get_dci_format
(
NR_UE_sched_ctrl_t
*
sched_ctrl
);
int
get_dci_format
(
NR_UE_sched_ctrl_t
*
sched_ctrl
);
const
int
set_dl_tda
(
gNB_MAC_INST
*
nrmac
,
NR_ServingCellConfigCommon_t
*
scc
,
int
slot
);
const
int
set_dl_tda
(
gNB_MAC_INST
*
nrmac
,
NR_ServingCellConfigCommon_t
*
scc
,
int
slot
);
void
calculate_preferred_ul_tda
(
module_id_t
module_id
,
const
NR_BWP_Uplink_t
*
ubwp
);
const
int
set_ul_tda
(
gNB_MAC_INST
*
nrmac
,
NR_ServingCellConfigCommon_t
*
scc
,
int
slot
);
bool
find_free_CCE
(
module_id_t
module_id
,
sub_frame_t
slot
,
int
UE_id
);
bool
find_free_CCE
(
module_id_t
module_id
,
sub_frame_t
slot
,
int
UE_id
);
...
...
This diff is collapsed.
Click to expand it.
openair2/LAYER2/NR_MAC_gNB/nr_mac_gNB.h
View file @
d3f90a90
...
@@ -809,10 +809,6 @@ typedef struct gNB_MAC_INST_s {
...
@@ -809,10 +809,6 @@ typedef struct gNB_MAC_INST_s {
uint64_t
dlsch_slot_bitmap
[
3
];
uint64_t
dlsch_slot_bitmap
[
3
];
/// bitmap of ULSCH slots, can hold up to 160 slots
/// bitmap of ULSCH slots, can hold up to 160 slots
uint64_t
ulsch_slot_bitmap
[
3
];
uint64_t
ulsch_slot_bitmap
[
3
];
/// Lookup for preferred time domain allocation for UL BWP, dynamically
/// allocated. The index refers to the DL slot, and the indicated TDA's k2
/// points to the right UL slot
int
*
preferred_ul_tda
[
MAX_NUM_BWP
];
/// maximum number of slots before a UE will be scheduled ULSCH automatically
/// maximum number of slots before a UE will be scheduled ULSCH automatically
uint32_t
ulsch_max_frame_inactivity
;
uint32_t
ulsch_max_frame_inactivity
;
...
...
This diff is collapsed.
Click to expand it.
openair2/RRC/NR/nr_rrc_config.c
View file @
d3f90a90
...
@@ -372,38 +372,40 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
...
@@ -372,38 +372,40 @@ void nr_rrc_config_ul_tda(NR_ServingCellConfigCommon_t *scc, int min_fb_delay){
uint8_t
DELTA
[
4
]
=
{
2
,
3
,
4
,
6
};
// Delta parameter for Msg3
uint8_t
DELTA
[
4
]
=
{
2
,
3
,
4
,
6
};
// Delta parameter for Msg3
int
mu
=
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
genericParameters
.
subcarrierSpacing
;
int
mu
=
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
genericParameters
.
subcarrierSpacing
;
// UL TDA index 0 is basic slot configuration starting in symbol 0 til the last but one symbol
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
pusch_timedomainresourceallocation
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
pusch_timedomainresourceallocation
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
*
pusch_timedomainresourceallocation
->
k2
=
k2
;
*
pusch_timedomainresourceallocation
->
k2
=
k2
;
pusch_timedomainresourceallocation
->
mappingType
=
NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB
;
pusch_timedomainresourceallocation
->
mappingType
=
NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB
;
pusch_timedomainresourceallocation
->
startSymbolAndLength
=
get_SLIV
(
0
,
13
);
// basic slot configuration starting in symbol 0 til the last but one symbol
pusch_timedomainresourceallocation
->
startSymbolAndLength
=
get_SLIV
(
0
,
13
);
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation
);
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation
);
if
(
frame_type
==
TDD
)
{
if
(
frame_type
==
TDD
)
{
// TDD
if
(
scc
->
tdd_UL_DL_ConfigurationCommon
)
{
if
(
scc
->
tdd_UL_DL_ConfigurationCommon
)
{
int
ul_symb
=
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
nrofUplinkSymbols
;
int
ul_symb
=
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
nrofUplinkSymbols
;
pusch_timedomainresourceallocation
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
if
(
ul_symb
>
1
)
{
pusch_timedomainresourceallocation
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
// UL TDA index 1 for mixed slot (TDD)
*
pusch_timedomainresourceallocation
->
k2
=
k2
;
pusch_timedomainresourceallocation
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
pusch_timedomainresourceallocation
->
mappingType
=
NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB
;
pusch_timedomainresourceallocation
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
pusch_timedomainresourceallocation
->
startSymbolAndLength
=
get_SLIV
(
14
-
ul_symb
,
ul_symb
-
1
);
// starting in fist ul symbol til the last but one
*
pusch_timedomainresourceallocation
->
k2
=
k2
;
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation
);
pusch_timedomainresourceallocation
->
mappingType
=
NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB
;
pusch_timedomainresourceallocation
->
startSymbolAndLength
=
get_SLIV
(
14
-
ul_symb
,
ul_symb
-
1
);
// starting in fist ul symbol til the last but one
// for msg3 in the mixed slot
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation
);
int
nb_periods_per_frame
=
get_nb_periods_per_frame
(
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
dl_UL_TransmissionPeriodicity
);
int
nb_slots_per_period
=
((
1
<<
mu
)
*
10
)
/
nb_periods_per_frame
;
// UL TDA index 2 for msg3 in the mixed slot (TDD)
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation_msg3
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
int
nb_periods_per_frame
=
get_nb_periods_per_frame
(
scc
->
tdd_UL_DL_ConfigurationCommon
->
pattern1
.
dl_UL_TransmissionPeriodicity
);
pusch_timedomainresourceallocation_msg3
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
int
nb_slots_per_period
=
((
1
<<
mu
)
*
10
)
/
nb_periods_per_frame
;
*
pusch_timedomainresourceallocation_msg3
->
k2
=
nb_slots_per_period
-
DELTA
[
mu
];
struct
NR_PUSCH_TimeDomainResourceAllocation
*
pusch_timedomainresourceallocation_msg3
=
CALLOC
(
1
,
sizeof
(
struct
NR_PUSCH_TimeDomainResourceAllocation
));
if
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
min_fb_delay
)
pusch_timedomainresourceallocation_msg3
->
k2
=
CALLOC
(
1
,
sizeof
(
long
));
*
pusch_timedomainresourceallocation_msg3
->
k2
+=
nb_slots_per_period
;
*
pusch_timedomainresourceallocation_msg3
->
k2
=
nb_slots_per_period
-
DELTA
[
mu
];
AssertFatal
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
33
,
"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)
\n
"
,
if
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
min_fb_delay
)
*
pusch_timedomainresourceallocation_msg3
->
k2
);
*
pusch_timedomainresourceallocation_msg3
->
k2
+=
nb_slots_per_period
;
pusch_timedomainresourceallocation_msg3
->
mappingType
=
NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB
;
AssertFatal
(
*
pusch_timedomainresourceallocation_msg3
->
k2
<
33
,
"Computed k2 for msg3 %ld is larger than the range allowed by RRC (0..32)
\n
"
,
pusch_timedomainresourceallocation_msg3
->
startSymbolAndLength
=
get_SLIV
(
14
-
ul_symb
,
ul_symb
-
1
);
// starting in fist ul symbol til the last but one
*
pusch_timedomainresourceallocation_msg3
->
k2
);
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation_msg3
);
pusch_timedomainresourceallocation_msg3
->
mappingType
=
NR_PUSCH_TimeDomainResourceAllocation__mappingType_typeB
;
pusch_timedomainresourceallocation_msg3
->
startSymbolAndLength
=
get_SLIV
(
14
-
ul_symb
,
ul_symb
-
1
);
// starting in fist ul symbol til the last but one
ASN_SEQUENCE_ADD
(
&
scc
->
uplinkConfigCommon
->
initialUplinkBWP
->
pusch_ConfigCommon
->
choice
.
setup
->
pusch_TimeDomainAllocationList
->
list
,
pusch_timedomainresourceallocation_msg3
);
}
}
}
}
}
}
}
...
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